DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election without traverse of Species I-2 shown in Figs. 26-40 in the Response to Restriction Requirements filed on 02/05/26 is acknowledged.
Applicant stated that Claims 1-15 are read on the elected species. However, Species I-2 is not described as having “an etch stop dielectric layer located between the dielectric core and the vertical semiconductor channel” cited by Claim 10, though Species I-1 (in Fig. 25) and I-3 (at least in Fig. 46) have the etch stop dielectric layer 64.
Status of Claims
Claims 10 and 16-20 are withdrawn from consideration as being drawn to a nonelected invention.
Claims 1-9 and 11-15 are examined on merits herein.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “upper source-level semiconductor layer that ... embedding the source contact layer”, as Claim 14 recites, must be shown or the feature(s) canceled from the claim(s): Currently figures of the application show that the source contact layer is embedded into two stacked source-level semiconductor layers, not into the one upper layer.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 0188 of the published application US 2024/0334697 identifies an optional backside blocking dielectric by number 52, while other paragraphs identify it by number 44, since number 52 is assigned to an optional blocking dielectric layer of a memory filling.
Application is not clear with respect to dispositions of the source contact layer: Paragraphs 0163, 206, and 217, referring to Figs. 19, 38, and 40, accordingly, state that the source contact layer is embedded into the upper source-level semiconductor layer, while the cited figures explicitly show that the source contact layer 114 is embedded into two source-level semiconductor layers – layers 116 and 112.
Appropriate corrections are required.
Abstract
Abstract is objected to because of the following informality: Abstract contains a recitation: “a source structure having a portion surrounded by inner sidewalls of cylindrical vertical semiconductor channels”. Examiner suggests to consider two modifications of the statement: “a source structure having a portion surrounded by inner sidewalls of a cylindrical vertical semiconductor channel” or: “a source structure having portions surrounded by inner sidewalls of cylindrical vertical semiconductor channels” – as being seemingly closer to the disclosed structure of the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 14 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In re Claim 14: Claim 14 recites: “an upper source-level semiconductor layer that is interposed between the lower source-level semiconductor layer and alternating stack and embedding the source contact layer”. The recitation is unclear in the part where the upper source-level semiconductor layer embedding the source contact layer, since figures of all three species of the application show that the source contact layer is embedded into two semiconductor layers, not into one. Although the specification in various paragraphs supports the recitation of Claim 14, these paragraphs (as it is shown in the objection to the specification) refer to figures of the application contradicting the statements.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022], inconsistence of the claim with the specification (in the particular situation, - inconsistence between the claim and figures of the application which are also a part of the specification - makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
For this Office Action, the cited limitation was interpreted as: “an upper source-level semiconductor layer that is interposed between the lower source-level semiconductor layer and alternating stack and at least partially embedding the source contact layer”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
As far as Claim 14 is understood, Claims 1, 5, and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2022/0045097).
In re Claim 1, Choi teaches a semiconductor structure, comprising:
an alternating stack of insulating layers IL1 and electrically conductive layers EL (Figs. 3-4, paragraph 0034) located over source-level material layers SL (paragraph 0032);
a memory opening – called a channel hole CH (paragraph 0041) and filled with a material structure VS (Fig. 4, paragraph 0038) - vertically extending through the alternating stack and into an upper portion – comprising sublayers USL and SSL (paragraph 0033) of the source-level material layers SL; and
a memory opening fill structure VS (Fig. 4, paragraph 0038) located in the memory opening and comprising a vertical stack of memory elements CL (as shown in a cross-section of Fig. 6, paragraph 0045, a vertical stack of memory elements is well-known in the arts of a 3D memory, paragraph 0004) and a vertical semiconductor channel SP (as shown in a cross section of Fig. 6, paragraph 0048 as well as in Fig. 10), wherein
the source-level material layers SL comprise a source contact layer SSL (paragraph 0032) that includes (as shown in Fig. 10 and Annotated Fig. 10, presenting a lower portion of the memory opening fill structure, paragraph 0016; note that element SSL is shown in Annotated Fig. 10 based on SSL in Fig. 5):
Annotated Fig. 10
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an outer portion – limited by four horizontal lines - located outside a volume of the memory opening (Annotated Fig. 10), and
an inner portion located within the volume of the memory opening (Annotated Fig. 10) and is more proximal to a vertical axis passing through a geometrical center of the volume of the memory opening than an inner sidewall of the vertical semiconductor channel SP is to the vertical axis, because SSL is in direct contact with an insulation VI (paragraph 0042) located in a central part of the memory opening, while the channel SP (and including parts USP and LSP) is separated from VI by a barrier PD (paragraphs 0041, 0065).
In re Claim 5, Choi teaches the semiconductor structure of Claim 1, wherein (Annotated Fig. 10) the inner portion of the source contact layer comprises a lower cylindrical segment -LCS (as in Annotated Fig. 10, the cited part has a same circular border as layer BL, see Fig. 8 directed to a top view of the memory fill opening, where the cylinder has top and bottom surfaces shown by two horizontal dotted lines) - and an upper tapered segment UTS (as in Annotated Fig. 10) having a tapered convex surface.
In re Claim 12, Choi teaches the semiconductor structure of Claim 1, wherein (Fig. 10 and Annotated Fig. 10):
the memory opening fill structure comprises a dielectric liner TL (being a tunnel insulating layer, paragraph 0044) that is interposed between the vertical stack of memory elements CL (paragraph 0044) and the vertical semiconductor channel SP (paragraph 0042); and
the source contact layer SSL comprises a vertically-extending fin -Fin, as in Annotated Fig. 10 - that contacts a surface segment (at least in a few points) of an outer sidewall of the vertical semiconductor channel SP and contacts a surface segment (at least in a few points) of the dielectric liner TL.
In re Claim 13, Choi teaches the semiconductor structure of Claim 1, wherein (Fig. 10 and Annotated Fig. 10) the inner portion of the source contact layer SSL is in contact with a segment of an inner sidewall of the vertical semiconductor channel SP – since the inner portion of the SSL passes through the SP (as shown in Fig. 10; paragraph 0065).
In re Claim 14, Choi teaches the semiconductor structure of Claim 1, wherein the source-level material layers SL further comprise (Fig. 4, paragraph 0032):
a lower source-level semiconductor layer LSL (paragraph 0032) that underlies the source contact layer SSL; and
an upper source-level semiconductor layer – comprising stacked sublayers USL and SSL - that is interposed between the lower source-level semiconductor layer LSL and alternating stack ST and embedding (“at least, partially”, in accordance with the claim interpretation) the source contact layer SSL.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 2022/0238548).
In re Claim 1, Liu teaches a semiconductor structure, comprising (Fig. 1):
an alternating stack 114 of insulating layers 116 and electrically conductive layers 118 (paragraph 0055) located over source-level material layers 120, 130, 134 (paragraph 0056);
a memory opening (incorporating pillar 132 (paragraph 0056) vertically extending through the alternating stack and into an upper portion 134 of the source-level material layers; and
a memory opening fill structure located in the memory opening and comprising a
vertical stack of memory elements 148 (paragraph 0067) and a vertical semiconductor channel 110 (paragraph 0056), wherein
the source-level material layers comprise a source contact layer 134 that includes
an outer portion (creating at least a portion of a horizontal plate 134) located outside a volume of the memory opening – e.g., that is limited at least by an outside sidewall of layer 150 (paragraph 0067) - and
an inner portion located within the volume of the memory opening and is more proximal to a vertical axis passing through a geometrical center of the volume of the memory opening than an inner sidewall of the vertical semiconductor channel 110 is to the vertical axis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Zhang et al. (US 2018/0269297).
In re Claim 11, Liu teaches the semiconductor structure of Claim 1 as cited above, including the source contact structure.
Liu does not teach that the source contact layer comprises: a source contact metallic barrier layer; and a source contact fill material layer comprising a metal embedded within the source contact metallic barrier layer.
Zhang teaches (Fig. 6, paragraphs 0027, 0040 and 0055-0056) a source contact layer 620 comprising a source contact metallic barrier layer 710 (being a metal silicide, paragraph 0056); and a source contact fill material layer 770 comprising a metal (such as ruthenium, or other metals (paragraph 0006, Claims 11-12) embedded within the source contact metallic barrier layer 710.
Liu and Zhang are analogous arts directed to electrical contacts to semiconductor materials, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Liu structure in view of the Zhang teaching, since they are from the same field of endeavor, and Zhang created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Liu structure by replacing its semiconductor source contact layer with a source contact layer comprised a source contact metallic barrier layer within which a source metal is embedded (per Zhang), if such source contact layer is preferred for the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Liu.
In re Claim 15, Liu teaches the semiconductor structure of Claim 1 as cited above, including the outer portion of the source contact layer 134.
Liu further teaches (or makes it obvious) that the outer portion of the source contact layer 134 (Fig. 2), extending under all memory openings (paragraph 0058) comprises a stem portion – Stem (as in Annotated Fig. 3, being a top view of the structure, but the source contact layer extends under all memory openings, and, accordingly, it can be shown by dotted lines) - that laterally extends along a first horizontal direction X and multiple branch portions – Branches (as in Annotated Fig. 3)
Annotated Fig 3
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that laterally extend along a second horizontal direction Y that is different from the first horizontal direction X; and the semiconductor structure further comprises additional memory openings – AMO, as in Annotated Fig. 3 – and additional memory opening fill structures (within AMO, identified as 132, paragraph 0058) that are located in the additional memory openings, wherein, as it is obvious from the application, each of the additional memory opening fill structures 132 comprises a respective additional vertical semiconductor channel that contacts a respective branch portion of the source contact layer.
Allowable Subject Matter
Claims 2 and 6 contain allowable subject matter, while claims 3-4 and 7-9 depend, correspondingly, on Claim 2 or 6. All these claims are objected by the current Office Action. Claims 2 and 6 (and all claims dependent on them) will be allowed if amended to incorporate all limitations of Claim 1, on which Claims 2 and 6 depend.
Reason for indicating Allowable Subject Matter
Re Claim 2: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 2 as: “an interconnection portion of the source contact layer that is located within a lateral opening through the vertical semiconductor channel”, in combination with other limitations of Claim 2 and in combination with all limitations of Claim 1, on which Claim 2 depends.
Re Claim 6: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 6 as: “a dielectric core... has a lopsided bottom portion so that the dielectric core has a lesser vertical extent on a side that is proximal to the outer portion of the source contact layer than on a side that is distal from the outer portion of the source contact layer”, in combination with other limitations of Claim 6 and with all limitations of Claim 1, on which Claim 6 depends.
The prior arts of record, in addition to the prior arts cited by the current Office Action above, also include: Cui (US 2022/0045091), Hong et al. (US 2022/0108741), Choi (US 2019/0288000), Huang et al. (US 9,741,737), and Matsumoto et al. (US 2018/0122904).
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 02/27/26