Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-20 are pending in this application.
Applicant’s election without traverse of Group I (claims 1-14) in the reply filed on November 11, 2025 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on November 12, 2025.
The Examiner notes that claims 1-14 are examined and claims 15-20 are withdrawn.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on July 31, 2023, October 18, 2023, June 19, 2024, and November 7, 2025 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0045097 A1) in view of Kanakamedala (US 9,824,966 B1).
With respect to claim 1, Choi teaches in Fig. 10:
A semiconductor structure, comprising:
an alternating stack of insulating layers (first insulating layers IL1) and electrically conductive layers (electrodes EL) located over a source semiconductor layer (upper and lower semiconductor layers USL and LSL);
a memory opening (channel holes CH) vertically extending through the alternating stack and the source semiconductor layer;
a memory opening fill structure located in the memory opening and comprising, from outside to inside, a vertical stack of memory elements (blocking layer BL, charge layer CL), a vertical semiconductor channel (upper semiconductor pattern USP) having a first tubular configuration, an etch stop dielectric layer (upper barrier pattern UPD, para. 59 “The barrier pattern PD may be formed of or include a material, which has a high etch resistance property to an etchant (e.g. a chemical etchant such as a wet etchant) which is used in an etching process to form the source semiconductor layer SSL,”) having a second tubular configuration, and a dielectric core (insulating gap fill pattern VI);
and a conductive semiconductor source structure contacting the etch stop dielectric layer (UPD), and the vertical semiconductor channel (USP).
Choi fails to teach:
and a metallic source structure contacting the source semiconductor layer, the etch stop dielectric layer, and the vertical semiconductor channel.
Kanakamedala teaches that it is known to use metal for a source contact layer (col. 1 line 67-col. 2 line 1). The metal source contact layer of Kanakamedala is analogous to the source semiconductor layer SSL of Choi.
Modifying Choi by Kanakamedala such that the SSL is made of metal teaches:
and a metallic source structure (SSL of Obu modified to be made of metal) contacting the source semiconductor layer (USL and LSL), the etch stop dielectric layer (UPD), and the vertical semiconductor channel (USP).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make the source contact layer of Choi with metal as taught by Kanakamedala, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
With respect to claim 2, Choi/Kanakamedala further teaches:
wherein the vertical semiconductor channel (bottom surface of USP is annular) comprises an annular end surface in contact with the metallic source structure (source structure SSL modified to be made of metal as taught by Kanakamedala).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Choi in view of Kanakamedala as explained above.
With respect to claim 3, Choi/Kanakamedala further teaches:
wherein a cylindrical segment of an inner sidewall of the vertical semiconductor channel (sidewall of USP) is in contact with the metallic source structure (in contact at the bottom of the sidewall, and in electrical contact through the bulk of the channel).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Choi in view of Kanakamedala as explained above.
With respect to claim 4, Choi/Kanakamedala further teaches:
wherein the etch stop dielectric layer comprises an annular end surface (bottom surface of UPD is annular) in contact with the metallic source structure (source structure SSL modified to be made of metal as taught by Kanakamedala).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Choi in view of Kanakamedala as explained above.
With respect to claim 5, Choi/Kanakamedala further teaches:
wherein the dielectric core (VI) comprises an outer sidewall in contact with the metallic source structure (source structure SSL modified to be made of metal as taught by Kanakamedala).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Choi in view of Kanakamedala as explained above.
With respect to claim 6, Choi further teaches:
the dielectric core (VI) comprises an end surface that is free of any opening therein (bottom surface of VI has no opening);
and a core void (air gap OV) is encapsulated by the dielectric core (VI).
With respect to claim 7, Choi further teaches:
wherein the memory opening fill structure comprises a dielectric liner (tunneling layer TL) that is interposed between the vertical stack of memory elements (BL and CL) and the vertical semiconductor channel (USP).
With respect to claim 12, Choi further teaches:
the memory opening fill structure further comprises a drain region (conductive pad PAD connected to the bitline contact plug PAD. The Examiner notes that although Choi does not explicitly refer to the conductive pad PAD as the drain, the ordinary artisan would understand that it would be obvious for PAD to act as the drain in this memory cell) that is vertically spaced from the metallic source structure (SSL modified to be made from metal) by the dielectric core (VI) and contacts an end portion of the vertical semiconductor channel (USL);
the etch stop dielectric layer (UPD) is in contact with the drain region (PAD);
the memory opening fill structure is located in a memory die (cell array structure CS);
and a logic die (peripheral circuit structure PS)is bonded to the memory die over the drain region (see Fig 21, the Examiner notes that the term “over” is dependent on orientation of the device and therefore Choi reads on the limitation).
With respect to claim 13, Choi/Kanakamedala further teaches:
wherein an entirety of an interface between the metallic source structure and the vertical semiconductor channel (interface of SSL modified as taught by Kanakamedala to be metal and VI) is located between a first horizontal plane including a top surface of the source semiconductor layer (top surface of USL) and a second horizontal plane including a bottom surface of the source semiconductor layer (bottom surface of LSL).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Choi in view of Kanakamedala as explained above.
With respect to claim 14, Choi/Kanakamedala further teaches:
wherein the metallic source structure comprises (SSL modified by Kanakamedala to be metal): a planar portion that extends horizontally underneath the source semiconductor layer; and a tubular portion that extends vertically from the planar portion into a gap between the vertical semiconductor channel and the dielectric core (see annotated Fig. 10 below).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Choi in view of Kanakamedala as explained above.
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Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0045097 A1) and Kanakamedala (US 9,824,966 B1) as applied to claim 7 above and further in view of Obu (US 11,127,759 B2).
With respect to claim 8, Choi/Kanakamedala teaches all limitations of claim 7 upon which claim 8 depends. Choi/Kanakamedala fails to teach:
wherein the dielectric liner is vertically spaced from the metallic source structure by a tubular spacer that laterally surrounds an end portion of the vertical semiconductor channel and contacts a cylindrical surface segment of the source semiconductor layer.
Obu teaches in Fig. 15D:
wherein the dielectric liner (tunneling dielectric layer 56) is vertically spaced from the metallic source structure (source contact layer 114) by a tubular spacer (tubular spacer 53, which is between the upper portion of 56 and 114) that laterally surrounds an end portion of the vertical semiconductor channel (portion of channel 60 at the source level) and contacts a cylindrical surface segment (inner surface) of the source semiconductor layer (source level semiconductor layer 116).
Choi/Kanakamedala discloses the claimed invention except for the tubular spacers. Obu discloses that it is known in the art to provide a tubular spacer between the source contact layer and the upper portion of a channel pillar. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the device of Choi/Kanakamedala with the tubular spacer of Obu, in order to help create an optimized shape for the source contact. See MPEP 2144.
With respect to claim 9, Obu further teaches:
wherein the tubular spacer comprises a dielectric material (col. 19, line 18 teaches that the tubular spacers are a semiconductor oxide).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Choi in view of Kanakamedala and Obu as explained above.
With respect to claim 10, Obu further teaches:
wherein the tubular spacer comprises a doped semiconductor material (col. 19, ln. 18-21 teaches that the tubular spacers are made by oxidizing exposed portions of the semiconductor layer 116, which is made from doped semiconductor material, per col. 9, lines 23-26).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Choi in view of Kanakamedala and Obu as explained above.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0045097 A1) in view of Kanakamedala (US 9,824,966 B1) as applied to claim 1 above and further in view of Nishikawa (US 10,629,675 B1).
With respect to claim 11, Choi/Kanakamedala teaches all limitations of independent claim 1 upon which claim 11 depends. Choi teaches that the etch stop layer may include SiC, SiCN, SiOC, or SiOCN and therefore does not teach:
wherein the etch stop dielectric layer comprises a dielectric metal oxide material.
Nishikawa teaches:
wherein the etch stop dielectric layer comprises a dielectric metal oxide material. (col. 10, lns, 11-16 “The lower sacrificial liner 103 and the upper sacrificial liner 105 include materials that can function as an etch stop material during removal of the source-level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can include silicon oxide, silicon nitride, and/or a dielectric metal oxide.” )
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make the etch stop dielectric layer of Choi with a dielectric metal oxide as taught by Nishikawa, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897