DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 8, 9, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow et al (US 2019/0312023 A1; hereinafter referred to as Morrow) in view of Goktepeli (20190097592)
Regarding Claim 1, Morrow discloses A radio frequency (RF) switch (Fig. 12, RFIC 1225, also “RFIC 1225 include cells having interconnect layout in accordance with embodiments described herein” [0054] ln 16-19), comprising:
a two-dimensional (2D) gate array (Fig. 2A, gate tracks 150) surrounding a plurality of source/drain regions (“first M0 track 160 couples to a source terminal” [0003] ln 09-10, also 1040 and 1060 in Figs 11B-11C) and a plurality of drain/source regions (“second M0 track 160 couples to a drain terminal” [0003] ln 10-11);
backside source/drain contacts (examiner interprets that backside source/drain contacts are inherent in coupling source/drain to backside metallization 1125 in Figs 11B-11C, also [0052] ln 07-10) coupled to the plurality of source/drain regions (1060) at a backside of the 2D gate array;
backside metallization layers (1125 in Figs 11B-11C) coupled to the backside source/drain contacts (“embodiments that couple source/drain 1060 to back-side metallization” [0051] ln 09-10);
frontside drain/source contacts (Fig. 11B, 1050, also [0052] 10-13) coupled to the plurality of drain/source regions (Fig. 11B, 1040) at a frontside, opposite the backside, of the 2D gate array; and
frontside metallization layers (Figs 11A-11C, 1190, also [0052] ln 12, also “front-side metallization level (e.g. M0) track 1190” [0052] ln 12) coupled to the frontside drain/source contacts (1050).
Morrow fails to disclose the newly added limitation with respect to zero level via (V0). However, Goktepeli discloses an RF Device where in paragraphs 0039 and 0057 the required zero level via is disclosed
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required zero level via in Morro as taught by Goktepeli in order to have routing efficiency, in order to have a smaller geometry and higher speed.
Regarding Claim 7, Morrow discloses the RF switch of claim 1. Morrow further discloses integrated into an RF front end module (Fig 12 shows integration into RFIC 1225 that serves as the front end module for an antenna labelled “To antenna”. Also, “RFIC 1225 include cells having interconnect layout in accordance with embodiments described herein” [0054] ln 16-19).
Regarding Claim 8, Morrow discloses the RF switch of claim 7. Morrow further discloses in which the RF front end module (1225) is incorporated (Fig. 12 shows incorporation into 1210 and 1205) in at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer (Fig. 12, mobile computing platform 1205). Also, “mobile computing platform 1205 … may include a chip-level or package-level integrated system 1210” [0053] ln 10-18.
Regarding Claim 9, Morrow discloses a method of constructing a radio frequency (RF) switch (Fig. 12, RFIC 1225, also “RFIC 1225 include cells having interconnect layout in accordance with embodiments described herein” [0054] ln 16-19), the method comprising:
forming a two-dimensional (2D) gate array (Fig. 2A, gate tracks 150) surrounding a plurality of source/drain regions (“first M0 track 160 couples to a source terminal” [0003] ln 09-10, also 1040 and 1060 in Figs 11B-11C) and a plurality of drain/source regions (“second M0 track 160 couples to a drain terminal” [0003] ln 10-11);
forming backside source/drain contacts (Figs 11B-11C, 1125, also [0052] ln 07-10) coupled to the plurality of source/drain regions (1060) at a backside of the 2D gate array;
forming backside metallization layers (1125) coupled to the backside source/drain contacts (examiner interprets that backside source/drain contacts are inherent in coupling source/drain to backside metallization 1125 in Figs 11B-11C, also [0052] ln 07-10);
forming frontside drain/source contacts (Fig. 11B, 1050, also [0052] 10-13) coupled to the plurality of drain/source regions (Fig. 11B, 1040) at a frontside, opposite the backside, of the 2D gate array; and
forming frontside metallization layers (Figs 11A-11C, 1190, also [0052] ln 12, also “front-side metallization level (e.g. M0) track 1190” [0052] ln 12) coupled to the frontside drain/source contacts (1050).
Regarding Claim 15, Morrow discloses the method of claim 9. Morrow further discloses integrating the RF switch into an RF front end module (Fig 12 shows integration into RFIC 1225 that serves as the front end module for an antenna labelled “To antenna”. Also, “RFIC 1225 include cells having interconnect layout in accordance with embodiments described herein” [0054] ln 16-19).
Regarding Claim 16, Morrow discloses the method of claim 15. Morrow further discloses further comprising incorporating (Fig. 12 shows incorporation into 1210 and 1205) the RF front end module (1225) in at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer (Fig. 12, mobile computing platform 1205). Also, “mobile computing platform 1205 … may include a chip-level or package-level integrated system 1210” [0053] ln 10-18.
Claims 2, 5 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow et al. (US 2019/0312023 A1; hereinafter referred to as Morrow) in view of Goktelepli 20190097592 as applied above furtherin view of Goktepeli et al. (US 2018/0175034 A1; hereinafter referred to as Goktepeli_034).
Regarding Claim 2, Morrow discloses the RF switch of claim 1. Morrow does not disclose in which the frontside metallization layers comprise:
middle-of-line (MOL) metallization layers coupled to the frontside drain/source contacts); and
back-end-of-line (BEOL) metallization layers coupled to the MOL metallization layers.
Goktepeli_034 teaches an integrated circuit device including dual-side processing with frontside and backside components, and is therefore analogous art, specifically Goktepeli_034 teaches (Fig. 4 and Fig. 6A):
middle-of-line (MOL) metallization layers coupled to the frontside drain/source contacts (412, “middle end of line MEOL coupled to S/D regions” [0050] ln 01-03); and
back-end-of-line (BEOL) metallization layers coupled to the MOL metallization layers (“MEOL/BEOL interconnects coupled to S/D regions of active devices” [0050] ln 01-04).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ transistor structures containing backside and frontside source/drain contacts as disclosed by Morrow and Goktepeli ‘592 combination, and to include middle-of-line (MOL) and back-end-of-line metallization layers as taught by Goktepeli_034 because middle-of-line (MOL) and back-end-of-line (BEOL) metallization layers are crucial for connecting the individual transistors (built in front-end-of-line, or FEOL) into complex, functional integrated circuits (ICs) by providing the wiring network, enabling high-speed communication, distributing power, and ensuring signal integrity, with MOL handling local contacts and BEOL forming the multi-layered global grid, essential for performance and miniaturization.
Regarding Claim 5, Morrow discloses the RF switch of claim 1. Morrow does not disclose further comprising a backside gate coupled to the 2D gate array.
Goktepeli_034 teaches a backside gate (Fig 6B, labeled “Gate” of transistor 630) coupled (by means of conductor 640) to the 2D gate array (examiner interprets location of these gates to be where front-side transistors 610 reside in Fig 6B). Also, “640 electrically couples gate of front-side transistor 610 to gate of back-side transistor 630 [0062] ln 06-08).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ an RF switch composed of a 2D gate array as disclosed by Morrow, and to include coupling between backside gates and the 2D gate array on a front-side as taught by Goktepeli_034 because backside gates coupled to frontside 2D gate arrays improves power efficiency due to enhanced signal routing, and enables higher transistor density.
Regarding Claim 10, Morrow discloses the method of claim 9. Morrow does not disclose in which forming the frontside metallization layers comprises:
forming middle-of-line (MOL) metallization layers coupled to the frontside drain/source contacts; and
forming back-end-of-line (BEOL) metallization layers coupled to the MOL metallization layers.
Goktepeli_034 teaches an integrated circuit device including dual-side processing with frontside and backside components, and is therefore analogous art, specifically Goktepeli_034 teaches (Fig. 4 and Fig. 6A:
forming middle-of-line (MOL) metallization layers coupled to the frontside drain/source contacts (412, “middle end of line MEOL coupled to S/D regions” [0050] ln 01-03); and
forming back-end-of-line (BEOL) metallization layers coupled to the MOL metallization layers (“MEOL/BEOL interconnects coupled to S/D regions of active devices” [0050] ln 01-04).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ transistor structures containing backside and frontside source/drain contacts as disclosed by Morrow, and to include middle-of-line (MOL) and back-end-of-line metallization layers as taught by Goktepeli_034 because middle-of-line (MOL) and back-end-of-line (BEOL) metallization layers are crucial for connecting the individual transistors (built in front-end-of-line, or FEOL) into complex, functional integrated circuits (ICs) by providing the wiring network, enabling high-speed communication, distributing power, and ensuring signal integrity, with MOL handling local contacts and BEOL forming the multi-layered global grid, essential for performance and miniaturization.
Regarding Claim 13, Morrow discloses the method of claim 9. Morrow does not disclose further comprising forming a backside gate coupled to the 2D gate array.
Goktepeli_034 teaches forming a backside gate (Fig 6B, labeled “Gate” of transistor 630) coupled (by means of conductor 640) to the 2D gate array (examiner interprets location of these gates to be where front-side transistors 610 reside in Fig 6B). Also, “640 electrically couples gate of front-side transistor 610 to gate of back-side transistor 630 [0062] ln 06-08).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ an RF switch composed of a 2D gate array as disclosed by Morrow, and to include coupling between backside gates and the 2D gate array on a front-side as taught by Goktepeli_034 because backside gates coupled to frontside 2D gate arrays improves power efficiency due to enhanced signal routing, and enables higher transistor density.
Claim 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow et al. (US 2019/0312023 A1) in view of Goktepeli 20190097592 further in view of Goktepeli_034 et al. (US 2018/0175034 A1), and further in view of Goktepeli et al. (US 2018/0061766 A1; hereinafter referred to as Goktepeli_766).
Regarding Claim 3, Morrow and Goktepeli ‘592 combination in view of Goktepeli_034 discloses the RF switch of claim 2. Morrow in view of Goktepeli_034 does not disclose in which the MOL metallization layers comprise a plurality of zero vias (V0) coupled to the frontside drain/source contacts.
Goktepeli_766 teaches an integrated circuit device including dual-side processing with frontside and backside components, and is therefore analogous art, specifically Goktepeli_766 teaches (Fig 8B) MOL metallization layers (“front-side MEOL contacts .. back-side MEOL contacts ” [0102] ln 08-10, note: examiner interprets claimed middle-of-line MOL to be equivalent to middle-end-of-line MEOL) comprise a plurality of zero vias (V0) coupled to the frontside drain/source contacts (“front-to-back via or shared contact. The shared contact connects front-side and back-side transistors” [0102] ln 11-12).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ transistor structures containing backside/frontside source/drain contacts and middle-of-line (MOL) metallization disclosed by Morrow and Goktepeli ‘592 combination in view of Goktepeli_034, and to include vias coupled to the frontside drain/source contact as taught by Goktepeli_766 because middle-of-line (MOL) vias connected to source/drain contacts create low-resistance paths for current, thus reducing parasitic resistance and improving chip performance by ensuring efficient power delivery and signal routing within the integrated circuit.
Regarding Claim 11, Morrow and Goktepeli ‘592 combiantion in view of Goktepeli_034 discloses the method of claim 10. Morrow in view of Goktepeli_034 does not disclose in which the MOL metallization layers comprise a plurality of zero vias (V0) coupled to the frontside drain/source contacts.
Goktepeli_766 teaches an integrated circuit device including dual-side processing with frontside and backside components, and is therefore analogous art, specifically Goktepeli_766 teaches (Fig 8B) MOL metallization layers (“front-side MEOL contacts .. back-side MEOL contacts ” [0102] ln 08-10, note: examiner interprets claimed middle-of-line MOL to be equivalent to middle-end-of-line MEOL) comprise a plurality of zero vias (V0) coupled to the frontside drain/source contacts (“front-to-back via or shared contact. The shared contact connects front-side and back-side transistors” [0102] ln 11-12).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ transistor structures containing backside/frontside source/drain contacts and middle-of-line (MOL) metallization disclosed by Morrow and Goktepeli ‘592combination in view of Goktepeli_034, and to include vias coupled to the frontside drain/source contact as taught by Goktepeli_766 because middle-of-line (MOL) vias connected to source/drain contacts create low-resistance paths for current, thus reducing parasitic resistance and improving chip performance by ensuring efficient power delivery and signal routing within the integrated circuit.
Claim 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow et al. (US 2019/0312023 A1) in view of Goktepeli (20190097592) further Goktepeli et al. (US 2018/0061766 A1; hereinafter referred to as Goktepeli_766).
Regarding Claim 4, Morrow and Goktepeli ‘592 combination discloses the RF switch of claim 1. Morrow does not disclose in which the backside metallization layers comprise middle-of-line (MOL) metallization layers coupled to the backside source/drain contacts.
Goktepeli_766 teaches an integrated circuit device including dual-side processing with frontside and backside components, and is therefore analogous art, specifically Goktepeli_766 teaches (Fig 8B) backside metallization layers comprise middle-of-line (MOL) metallization layers coupled to the backside source/drain contacts (“backside contact etch (to form backside MEOL contact) processes are utilized for the formation of the shared contact. The shared contact connects the front-side and backside transistors” [0102] ln 09-12).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ an RF switch as disclosed by Morrow and Goktepeli ‘592 combination, and to include backside middle-of-line (MOL) metallization to the backside source/drain contacts as taught by Goktepeli_766 because it firstly improves electrical performance by reducing parasitic effects and secondly enhances thermal management, which are both especially beneficial for high-frequency, high-power RF integrated circuits.
Regarding Claim 12, Morrow and Goktepeli ‘592 combination discloses the method of claim 9. Morrow does not disclose in which forming the backside metallization layers comprises forming middle-of-line (MOL) metallization layers coupled to the backside source/drain contacts.
Goktepeli_766 teaches forming the backside metallization layers comprises forming middle-of-line (MOL) metallization layers coupled to the backside source/drain contacts (“backside contact etch (to form backside MEOL contact) processes are utilized for the formation of the shared contact. The shared contact connects the front-side and backside transistors” [0102] ln 09-12).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ an RF switch as disclosed by Morrow and Goktepeli ‘592 combination, and to include backside middle-of-line (MOL) metallization to the backside source/drain contacts as taught by Goktepeli_766 because it firstly improves electrical performance by reducing parasitic effects and secondly enhances thermal management, which are both especially beneficial for high-frequency, high-power RF integrated circuits.
Claim 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow et al. (US 2019/0312023 A1) in view of Goktepeli (201900097592) in view of Su et al. (2022/0271138 A1; hereinafter referred to as Su).
Regarding Claim 6, Morrow and Goktepeli ‘592 combination discloses the RF switch of claim 1. Morrow does not disclose further comprising a backside gate coupled to the backside source/drain contacts.
Su teaches an integrated circuit device including dual-side processing with frontside and backside components, and is therefore analogous art, specifically Su teaches (Figs 14-15) a backside gate (Fig 15, 294-1) coupled (by means of conductor 304) to the backside source/drain contacts (274-1). Also, “conductive feature 302 electrically coupled to backside gate 294-1 and backside source/drain 274-1, thereby interconnecting them” [0033] ln 04-07.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ an RF switch as disclosed by Morrow and Goktepeli ‘592 combination, and to include backside gate coupled to backside source/drain contacts as taught by Su because a backside gate-to-backside source/drain connection is used in advanced integrated circuits (like 2nm and beyond) to decongest the frontside (top) metal layers, improve power delivery (reduce IR drop), increase signal routing efficiency, and enable higher transistor density, by moving power connections to the backside of the wafer. This allows for thicker, lower-resistance power lines and frees up space on the frontside for signals, leading to better performance and power efficiency.
Regarding Claim 14, Morrow and Goktepeli ‘592 combination discloses the method of claim 9. Morrow does not disclose further comprising forming a backside gate coupled to the backside source/drain contacts.
Su teaches forming a backside gate (Fig 15, 294-1) coupled (by means of conductor 304) to the backside source/drain contacts (274-1). Also, “conductive feature 302 electrically coupled to backside gate 294-1 and backside source/drain 274-1, thereby interconnecting them” [0033] ln 04-07.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ an RF switch as disclosed by Morrow and Goktepeli ‘592 combination, and to include backside gate coupled to backside source/drain contacts as taught by Su because a backside gate-to-backside source/drain connection is used in advanced integrated circuits (like 2nm and beyond) to decongest the frontside (top) metal layers, improve power delivery (reduce IR drop), increase signal routing efficiency, and enable higher transistor density, by moving power connections to the backside of the wafer. This allows for thicker, lower-resistance power lines and frees up space on the frontside for signals, leading to better performance and power efficiency.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 6/10/2026
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