DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1 and 8 in the Applicant’s response dated 16 June 2026. The claim amendments have been addressed below.
Claim Objections
Claim 8 is objected to because of the following informalities:
Claim 8 appears to contact an antecedent basis error wherein claim 8 recites “… opposite the first edge”, wherein the Examiner believes claim 8 is intended to recite “… opposite the first bottom edge”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshi Miyazaki (US 2014/0210062 A1; hereinafter “Miyazaki”) in view of Sheng Tsung Liu (US 2005/0127494 A1; hereinafter “Liu”).
Regarding Claim 1, Miyazaki teaches a semiconductor package, comprising:
an integrated circuit (IC) die (101, Fig. 1A, para [0043] describes a semiconductor chip 101) covered by a mold compound (120, Fig. 1A, para [0043] describes an insulating package 120 encapsulating the IC die 101) to form a four-sided package with a top surface at a top side of the package (TS, annotated Fig. 1A depicts a top surface TS at a top side of the package 120 upon inverting Fig. 1A as shown in annotated Fig. 1A) and a bottom surface (BS, annotated Fig. 1A depicts a bottom surface BS at a bottom side of the package 120 upon inverting Fig. 1A as shown in annotated Fig. 1A);
a first group of no-lead contacts (FG and 310b, annotated Fig. 1B, para [0047] describes first leads 310b wherein the first leads comprise a first group FG) exposed on a first side and on the bottom surface of the package (FS, annotated Fig. 1B depicts a bottom surface BS of semiconductor package 100 wherein the first group FG of first leads 310b are exposed on a first side FS and the bottom surface BS);
a second group of no-lead contacts (SG and 310b, annotated Fig. 1B, para [0047] describes first leads 310b wherein the first leads comprise a second group SG) exposed on a second side and on the bottom surface of the package, wherein the second side is opposite the first side (SS, annotated Fig. 1B depicts the bottom surface BS of the semiconductor package 100 wherein the second group SG of first leads 310b are exposed on a second side SS, opposite the first side FS, and the bottom surface BS);
a first external lead extending from a third side of the package (311b and TRS, Fig. 1A and annotated Fig. 1B, para [0047] describes second leads 311b which can be seen extending from a third side TRS of the package 100 in Fig. 1A and annotated Fig. 1B); and
a second external lead extending from a fourth side of the package opposite the third side (311b and FRS, Fig. 1A and annotated Fig. 1B, para [0047] describes second leads 311b which can be seen extending from a fourth side FRS, opposite the third side TRS of the package 100 in Fig. 1A and annotated Fig. 1B), the first and second external leads bent to extend above the top surface of the package (170, Fig. 1A, para [0054] describes wherein a height 180 of the device 100 includes a height of the bend leads at a horizontal plane 170 wherein a resulting height is due to first and second external leads 311b being bent to extend above the top surface TS of the package 100).
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Miyazaki fails to explicitly disclose the first external lead extending from the bottom side; and the second external lead extending from the bottom side.
However, Liu teaches a similar semiconductor package comprising:
a first external lead extending from a third side of the package (314, FEL and THS2, annotated Fig. 5, para [0024] describes a first external lead 314 and FEL extending from a third side THS2 of a semiconductor package 220), the first external lead extending from the bottom side (FEL and BS2, annotated Fig. 5, para [0024] describes the first external lead FEL extending from a bottom side BS2 of the semiconductor package 220); and
a second external lead extending from a fourth side of the package opposite the third side (314, SEL and FS2, annotated Fig. 5, para [0024] describes a second external lead 314 and SEL extending from a fourth side FS2 opposite the third side THS2 of the semiconductor package 220), the second external lead extending from the bottom side (SEL and BS2, annotated Fig. 5, para [0024] describes the second external lead SEL extending from a bottom side BS2 of the semiconductor package 220).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki with Liu to further disclose a semiconductor package comprising a first external lead extending from a bottom side of a semiconductor package and a second external lead extending from the bottom side in order to provide the advantage of providing an inner contact exposed on a bottom surface of a semiconductor device and a set of external leads extending from a same bottom surface and side surfaces of the semiconductor package to effectively increase the solder fillet height when mounding a semiconductor package so as to increase the strength and reliability of a solder connection between a semiconductor package and a printed circuit board (Liu, para [0026]).
Regarding Claim 2, the combination of Miyazaki and Liu teaches the semiconductor package of claim 1, wherein the first and second external leads are shaped as gull-wing leads each having a top end that bends away from the package (Miyazaki, 311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of gull-wing leads).
Regarding Claim 3, the combination of Miyazaki and Liu teaches the semiconductor package of claim 1, wherein the first and second external leads are J-shape leads each having a top end that bends over the top surface of the package (Miyazaki, 311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of J-shaped leads wherein a J-shaped lead would have a top that bends over the top surface of the package).
Regarding Claim 4, the combination of Miyazaki and Liu teaches the semiconductor package of claim 1, further comprising:
an opening formed in one or more of the first and second external leads (Miyazaki, OP, annotated Fig. 1B depicts an opening OP formed between one or more of the first and second external leads 311b).
Regarding Claim 5, the combination of Miyazaki and Liu teaches the semiconductor package of claim 1, wherein the first external lead and one or more of the first group of no-lead contacts are part of a continuous leadframe segment that is attached to the IC die (Miyazaki, Fig. 3A, para [0047] describes a continuous leadframe 300 comprising first leads 310 and second leads 311 attached to an IC die 101 as also shown in Fig. 1A).
Regarding Claim 8, Miyazaki teaches a semiconductor package, comprising:
a semiconductor die electrically coupled to one or more leadframe segments (101, Fig. 1A and Fig. 3A, para [0043] describes a semiconductor chip 101 and para [0043] describes wherein the chip 101 may be coupled to leads of a leadframe 300 through wire bonds 130);
an encapsulant covering the semiconductor die and at least a portion of the leadframe segments (120, Fig. 1A, para [0043] describes an insulating package 120 encapsulating the IC die 101 and portions of leadframe segments 310b and 311b);
the leadframe segments forming a first set of no-lead contacts along a first bottom edge of the package (310b, annotated Fig. 1A and annotated Fig. 1B II, para [0047] describes a first set of no lead contacts 310b and FG2 along a first bottom edge FE2).
the leadframe segments forming a first external lead (311b, annotated Fig. 1A and annotated Fig. 1B II, para [0047] describes a first external lead 311b extending from a second bottom edge SE2 as shown in annotated Fig. 1B II); and
a second external lead on a second bottom edge of the package opposite the first edge (311b, annotated Fig. 1A and annotated Fig. 1B II, para [0047] describes a second external lead 311b on a second bottom edge SE2 opposite the first bottom edge FE2 as shown in annotated Fig. 1B II), the first and second external leads extending above a top surface of the encapsulant (170, Fig. 1A, para [0054] describes wherein a height 180 of the device 100 includes a height of the bend leads at a horizontal plane 170 wherein a resulting height is due to first and second external leads 311b being bent to extend above the top surface TS of the package 100).
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Miyazaki fails to explicitly disclose a first external lead extending from the first bottom edge of the package; and a second external lead on a second bottom edge of the package opposite the first edge.
However, Liu teaches a similar semiconductor package, comprising:
a first external lead (FEL2 and 314, annotated Fig. 5 II, para [0024] describes a first external lead 314 and FEL2) extending from the first bottom edge of the package (FBE2, FEL2 and 312, annotated Fig. 5 II, para [0024] describes inner lead portions 312 comprising a no-lead contact along a first bottom edge FBE2 of a semiconductor package 220 wherein the first external lead FEL2 extends from the same first bottom edge FBE2); and
a second external lead (SEL2 and 314, annotated Fig. 5 II, para [0024] describes a second external lead 314 and SEL2) on a second bottom edge of the package opposite the first second edge (SBE2 and SEL2, annotated Fig. 5 II, depicts a second bottom edge SBE2 opposite the first bottom edge FBE2 wherein the second external lead SEL2 extends from the second bottom edge SBE2).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki with Liu to further disclose a semiconductor package comprising a first external lead extending from a first bottom edge of a package; and a second external lead on a second bottom edge of the package opposite the first second edge in order to provide the advantage of providing an inner contact exposed on a bottom surface of a semiconductor device and a set of external leads extending from a same bottom surface and side surfaces of the semiconductor package to effectively increase the solder fillet height when mounding a semiconductor package so as to increase the strength and reliability of a solder connection between a semiconductor package and a printed circuit board (Liu, para [0026]).
Regarding Claim 9, the combination of Miyazaki and Liu teaches the semiconductor package of claim 8, wherein the first and second external leads are shaped as gull-wing leads (Miyazaki, 311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of gull-wing leads).
Regarding Claim 10, the combination of Miyazaki and Liu teaches the semiconductor package of claim 9, wherein the gull-wing leads each have a top end that bends away from the package (Miyazaki, 311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of gull-wing leads wherein the gull-wing leads have a top end that bends away from the package as shown in Fig. 1A).
Regarding Claim 11, the combination of Miyazaki and Liu teaches the semiconductor package of claim 8, wherein the first and second external leads are J-shape leads (Miyazaki, 311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of J-shaped leads).
Regarding Claim 12, the combination of Miyazaki and Liu teaches the semiconductor package of claim 11, wherein the J-shape leads each have a top end that bends over the top surface of the encapsulant (Miyazaki, 311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of J-shaped leads wherein a J-shaped lead would have a top that bends over the top surface of the package).
Regarding Claim 13, the combination of Miyazaki and Liu teaches the semiconductor package of claim 8, further comprising:
a second set of no-lead contacts along a fourth bottom edge of the package opposite the first edge (Miyazaki, 310b and SG2, annotated Fig. 1B II, para [0047] describes a second set of no lead contacts 310b and SG2 along a fourth bottom edge FRE2, opposite the first edge FE2).
Regarding Claim 14, the combination of Miyazaki and Liu teaches the semiconductor package of claim 8, further comprising:
an opening formed in one or more of the first and second external leads (Miyazaki, OP2, annotated Fig. 1B II depicts an opening OP2 formed between one or more of the first and second external leads 311b).
Regarding Claim 15, the combination of Miyazaki and Liu teaches the semiconductor package of claim 8, wherein the first external lead is electrically coupled to one or more of the first set of no-lead contacts (Miyazaki, 310b and 311b, Fig. 3A depicts wherein the first external lead comprised of second leads 311b may be electrically coupled to one or more of the first set of no-lead contacts 310a through bonding wires 130, terminals 106 and semiconductor die 101 and further wherein para [0044] describes the leadframe 300 as being electrically conductive further putting a first external lead and the no-lead contacts in electrical connection).
Regarding Claim 16, the combination of Miyazaki and Liu teaches the semiconductor package of claim 8, wherein the first external lead and one or more of the first set of no-lead contacts are part of a continuous leadframe segment (Miyazaki, 300, 310 and 311, Fig. 3A, para [0047] describes a continuous leadframe 300 comprising first leads 310 and second leads 311 attached to an IC die 101 as also shown in Fig. 1A).
Regarding Claim 20, the combination of Miyazaki and Liu teaches the semiconductor package of claim 8, further comprising: an electrical device attached to top ends of the first and second external leads above the top surface of the encapsulant (Liu, 720 and 314, Fig. 7 and annotated Fig. 5 II, para [0029] describes wherein Fig. 5 is substantially identical to the embodiment of Fig. 5 and para [0032] describes Fig. 7 is substantially identical to Fig. 3 wherein para [0032] further describes an electrical device 720 is attached to top ends of the first external lead 314 and FEL2 and the second external lead 314 and SEL2 from annotated Fig. 5 II above the top surface of the encapsulant 220).
Claims 6 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshi Miyazaki (US 2014/0210062 A1; hereinafter “Miyazaki”) in view of Sheng Tsung Liu (US 2005/0127494 A1; hereinafter “Liu”) and in further view of Jae Ung Lee et al. (US 8,921,955 B1; hereinafter “Lee”).
Regarding Claim 6, the combination of Miyazaki and Liu discloses all the limitations of claim 1.
Miyazaki and Liu fail to explicitly disclose the semiconductor package of claim 1, wherein the second external lead comprises: a half etched end portion within the mold compound, the end portion having half etched tabs that extend laterally from the second external lead and that are not exposed on the bottom surface of the package, and the second external lead is not directly electrically coupled to the IC die.
However, Lee teaches a similar semiconductor package, wherein the second external lead (112, annotated Fig. 9E, column 11, lines 60-63 describes a plurality of leads extending along a peripheral edge of the device wherein a second external lead SEL extends from a left side of the semiconductor package 300) comprises: a half etched end portion within the mold compound (312, annotated Fig. 9E, column 12, lines 6-9 describe wherein the leads 312 comprise half-etched inner end portions wherein the second external lead SEL comprises a half-etched inner end portion HEP encapsulated by a body 320 of the package 300 as described in column 13, lines 10-13), the end portion having half etched tabs that extend laterally from the second external lead and that are not exposed on the bottom surface of the package (312, annotated Fig. 9E depicts wherein the end portion having half-etched tabs HEP extend laterally from the second external lead and are encapsulated by encapsulant 320 therefore not being exposed on a bottom surface of the package 300), and the second external lead is not directly electrically coupled to the IC die (annotated Fig. 9E depicts wherein second external lead SEL is not directly electrically coupled to the IC die 330 or 340 as it has an end portion encapsulated by encapsulant 320 and does not comprise a wire conductive wire 350 bonding it to the IC dies such as first external lead FEL on the opposite side of the package 300).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki and Liu with Lee to further disclose a semiconductor package comprising a half-etched tab of a second external lead within a mold compound of the semiconductor package and not directly electrically coupled to the integrated circuit die in order to provide the well-known advantage of providing mechanical support and balance for mounting an external device to a semiconductor package providing further providing an additional point of contact increasing stability during an external device mounting process.
Regarding Claim 17, the combination of Miyazaki and Liu discloses all the limitations of claim 8.
Miyazaki and Liu fail to explicitly disclose the semiconductor package of claim 8, wherein the second external lead is not directly electrically coupled to semiconductor die.
However, Lee teaches a similar semiconductor package, wherein the second external lead is not directly electrically coupled to semiconductor die (annotated Fig. 9E depicts wherein a second external lead SEL is not directly electrically coupled to an IC die 330 or 340 as it has an end portion encapsulated by an encapsulant 320 and does not comprise a wire conductive wire 350 bonding it to the IC dies such as first external lead FEL on the opposite side of the package 300).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki and Liu with Lee to further disclose a semiconductor package comprising a second external lead not directly electrically coupled to an integrated circuit die in order to provide the well-known advantage of providing mechanical support and balance for mounting an external device to a semiconductor package providing further providing an additional point of contact increasing stability during an external device mounting process.
Regarding Claim 18, the combination of Miyazaki and Liu discloses all the limitations of claim 8.
Miyazaki and Liu fail to explicitly disclose the semiconductor package of claim 8, wherein the second external lead comprises: a half etched end portion within the encapsulant, the end portion having half etched tabs extending laterally from the second external lead and not exposed on a bottom surface of the package.
However, Lee teaches a similar semiconductor package, wherein the second external lead (112, annotated Fig. 9E, column 11, lines 60-63 describes a plurality of leads extending along a peripheral edge of the device wherein a second external lead SEL extends from a left side of the semiconductor package 300) comprises:
a half etched end portion within the encapsulant (312, annotated Fig. 9E, column 12, lines 6-9 describe wherein the leads 312 comprise half-etched inner end portions wherein the second external lead SEL comprises a half-etched inner end portion HEP encapsulated by a body 320 of the package 300 as described in column 13, lines 10-13), the end portion having half etched tabs extending laterally from the second external lead and not exposed on a bottom surface of the package (312, annotated Fig. 9E depicts wherein the end portion having half-etched tabs HEP extend laterally from the second external lead and are encapsulated by encapsulant 320 therefore not being exposed on a bottom surface of the package 300).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki and Liu with Lee to further disclose a semiconductor package comprising a half-etched tab of a second external lead extending laterally within an encapsulant of the semiconductor package in order to provide the well-known advantage of providing mechanical support and balance for mounting an external device to a semiconductor package providing further providing an additional point of contact increasing stability during an external device mounting process.
Claims 7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshi Miyazaki (US 2014/0210062 A1; hereinafter “Miyazaki”) in view of Sheng Tsung Liu (US 2005/0127494 A1; hereinafter “Liu”) and in further view of Yeou Chian Chang et al. (US 2022/0359350 A1; hereinafter “Chang”).
Regarding Claim 7, the combination of Miyazaki and Liu discloses all the limitations of claim 1.
Miyazaki and Liu fail to explicitly disclose the semiconductor package of claim 1, wherein each of the no-lead contacts comprise half etched portions that are not exposed through the mold compound on the bottom surface of the package.
However, Chang teaches a similar semiconductor package, wherein each of the no-lead contacts comprise half etched portions that are not exposed through the mold compound on the bottom surface of the package (108, Fig. 8, para [0010] describes wherein a plurality of leads 104 disposed on a bottom edge of a semiconductor package 100 further comprises an inner half-etched, reduced thickness portion 108 that is not exposed through a mold compound 702 on a bottom surface of the package).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki and Liu with Chang to further disclose a semiconductor package wherein no-lead contacts comprise half-etched portions that are not exposed through a mold compound in order to provide the advantage of providing for a secure connection between a die pad and a long half-etched lead which further reinforces the half-etched leads and provides for a device with improved yields, lower costs, and greater overall reliability (Chang, para [0025]).
Regarding Claim 19, the combination of Miyazaki and Liu discloses all the limitations of claim 8.
Miyazaki and Liu fail to explicitly disclose the semiconductor package of claim 8, wherein each of the first set of no-lead contacts comprise half etched portions that are not exposed through the encapsulant on a bottom surface of the package.
However, Chang teaches a similar semiconductor package wherein each of the first set of no-lead contacts comprise half etched portions that are not exposed through the encapsulant on a bottom surface of the package (108, Fig. 8, para [0010] describes wherein a plurality of leads 104 disposed on a bottom edge of a semiconductor package 100 further comprises an inner half-etched, reduced thickness portion 108 that is not exposed through an encapsulant 702 on a bottom surface of the package).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki and Liu with Chang to further disclose a semiconductor package wherein no-lead contacts comprise half-etched portions that are not exposed through an encapsulant in order to provide the advantage of providing for a secure connection between a die pad and a long half-etched lead which further reinforces the half-etched leads and provides for a device with improved yields, lower costs, and greater overall reliability (Chang, para [0025]).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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