DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A and Species II in the reply filed on 8 December 2025 is acknowledged. The traversal is on the grounds that a valid restriction must be based on the claims and not the Figures. Second, the Applicant traverses on the grounds that there is no evidence of requiring search in different classes/subclasses in the restriction wherein the Applicant quotes MPEP 808.01(a), MPEP 803 and MPEP 808.02 for grounds for this traversal. This is not found persuasive because the Applicant has quoted that a valid restriction must be based on the claims and not the Figures but has failed to recite the section of the MPEP from which this information is drawn and has not provided any evidence to support this claim.
However, with respect to the Applicant’s second argument for traversal on the grounds that there is no evidence of requiring search in different classes/subclasses in the restriction wherein the Applicant quotes MPEP 808.01(a), MPEP 803 and MPEP 808.02 for grounds for this traversal, the Examiner notices upon conducting a search for Species A and Species II, the Examiner was able to find prior art related to Species B and Species I and has therefore found the Applicant’s second argument to be persuasive and has withdrawn the restriction requirement with respect to claims 3 and 11-13.
The restriction requirement has been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 8-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hiroshi Miyazaki (US 2014/0210062 A1; hereinafter “Miyazaki”).
Regarding Claim 1, Miyazaki teaches a semiconductor package, comprising:
an integrated circuit (IC) die (101, Fig. 1A, para [0043] describes a semiconductor chip 101) covered by a mold compound (120, Fig. 1A, para [0043] describes an insulating package 120 encapsulating the IC die 101) to form a four-sided package with a top surface (TS, annotated Fig. 1A depicts a top surface TS) and a bottom surface (BS, annotated Fig. 1A depicts a bottom surface BS);
a first group of no-lead contacts (FG and 310b, annotated Fig. 1B, para [0047] describes first leads 310b wherein the first leads comprise a first group FG) exposed on a first side and on the bottom surface of the package (FS, annotated Fig. 1B depicts a bottom surface BS of semiconductor package 100 wherein the first group FG of first leads 310b are exposed on a first side FS and the bottom surface BS);
a second group of no-lead contacts (SG and 310b, annotated Fig. 1B, para [0047] describes first leads 310b wherein the first leads comprise a second group SG) exposed on a second side and on the bottom surface of the package, wherein the second side is opposite the first side (SS, annotated Fig. 1B depicts the bottom surface BS of the semiconductor package 100 wherein the second group SG of first leads 310b are exposed on a second side SS, opposite the first side FS, and the bottom surface BS);
a first external lead extending from a third side of the package (311b and TRS, Fig. 1A and annotated Fig. 1B, para [0047] describes second leads 311b which can be seen extending from a third side TRS of the package 100 in Fig. 1A and annotated Fig. 1B); and
a second external lead extending from a fourth side of the package opposite the third side (311b and FRS, Fig. 1A and annotated Fig. 1B, para [0047] describes second leads 311b which can be seen extending from a fourth side FRS, opposite the third side TRS of the package 100 in Fig. 1A and annotated Fig. 1B), the first and second external leads bent to extend above the top surface of the package (170, Fig. 1A, para [0054] describes wherein a height 180 of the device 100 includes a height of the bend leads at a horizontal plane 170 wherein a resulting height is due to first and second external leads 311b being bent to extend above the top surface TS of the package 100).
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Regarding Claim 2, Miyazaki teaches the semiconductor package of claim 1, wherein the first and second external leads are shaped as gull-wing leads each having a top end that bends away from the package (311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of gull-wing leads).
Regarding Claim 3, Miyazaki teaches the semiconductor package of claim 1, wherein the first and second external leads are J-shape leads each having a top end that bends over the top surface of the package (311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of J-shaped leads wherein a J-shaped lead would have a top that bends over the top surface of the package).
Regarding Claim 4, Miyazaki teaches the semiconductor package of claim 1, further comprising:
an opening formed in one or more of the first and second external leads (OP, annotated Fig. 1B depicts an opening OP formed between one or more of the first and second external leads 311b).
Regarding Claim 5, Miyazaki teaches the semiconductor package of claim 1, wherein the first external lead and one or more of the first group of no-lead contacts are part of a continuous leadframe segment that is attached to the IC die (Fig. 3A, para [0047] describes a continuous leadframe 300 comprising first leads 310 and second leads 311 attached to an IC die 101 as also shown in Fig. 1A).
Regarding Claim 8, Miyazaki teaches a semiconductor package, comprising:
a semiconductor die electrically coupled to one or more leadframe segments (101, Fig. 1A and Fig. 3A, para [0043] describes a semiconductor chip 101 and para [0043] describes wherein the chip 101 may be coupled to leads of a leadframe 300 through wire bonds 130);
an encapsulant covering the semiconductor die and at least a portion of the leadframe segments (120, Fig. 1A, para [0043] describes an insulating package 120 encapsulating the IC die 101 and portions of leadframe segments 310b and 311b);
the leadframe segments forming a first set of no-lead contacts along a first bottom edge of the package (310b, annotated Fig. 1A and annotated Fig. 1B II, para [0047] describes a first set of no lead contacts 310b and FG2 along a first bottom edge FE2).
the leadframe segments forming a first external lead on a second bottom edge of the package (311b, annotated Fig. 1A and annotated Fig. 1B II, para [0047] describes a first external lead 311b formed on a second bottom edge SE2 when viewed from below the bottom edge as shown in annotated Fig. 1B II wherein first external lead 311b extends from a second bottom edge SE2); and
a second external lead on a third bottom edge of the package opposite the second edge (311b, annotated Fig. 1A and annotated Fig. 1B II, para [0047] describes a second external lead 311b formed on a third bottom edge TE2 when viewed from below the bottom edge as shown in annotated Fig. 1B II wherein second external lead 311b extends from a third bottom edge TE2, as shown in annotated Fig. 1B II), the first and second external leads extending above a top surface of the encapsulant (170, Fig. 1A, para [0054] describes wherein a height 180 of the device 100 includes a height of the bend leads at a horizontal plane 170 wherein a resulting height is due to first and second external leads 311b being bent to extend above the top surface TS of the package 100).
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Regarding Claim 9, Miyazaki teaches the semiconductor package of claim 8, wherein the first and second external leads are shaped as gull-wing leads (311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of gull-wing leads).
Regarding Claim 10, Miyazaki teaches the semiconductor package of claim 9, wherein the gull-wing leads each have a top end that bends away from the package (311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of gull-wing leads wherein the gull-wing leads have a top end that bends away from the package as shown in Fig. 1A).
Regarding Claim 11, Miyazaki teaches the semiconductor package of claim 8, wherein the first and second external leads are J-shape leads (311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of J-shaped leads).
Regarding Claim 12, Miyazaki teaches the semiconductor package of claim 11, wherein the J-shape leads each have a top end that bends over the top surface of the encapsulant (311b, Fig. 1A and Fig. 4G, para [0062] describes wherein external leads 311b during their forming as shown by 411b in Fig. 4G, may be formed into the shape of J-shaped leads wherein a J-shaped lead would have a top that bends over the top surface of the package).
Regarding Claim 13, Miyazaki teaches the semiconductor package of claim 8, further comprising:
a second set of no-lead contacts along a fourth bottom edge of the package opposite the first edge (310b and SG2, annotated Fig. 1B II, para [0047] describes a second set of no lead contacts 310b and SG2 along a fourth bottom edge FRE2, opposite the first edge FE2).
Regarding Claim 14, Miyazaki teaches the semiconductor package of claim 8, further comprising:
an opening formed in one or more of the first and second external leads (OP2, annotated Fig. 1B II depicts an opening OP2 formed between one or more of the first and second external leads 311b).
Regarding Claim 15, Miyazaki teaches the semiconductor package of claim 8, wherein the first external lead is electrically coupled to one or more of the first set of no-lead contacts (310b and 311b, Fig. 3A depicts wherein the first external lead comprised of second leads 311b may be electrically coupled to one or more of the first set of no-lead contacts 310a through bonding wires 130, terminals 106 and semiconductor die 101 and further wherein para [0044] describes the leadframe 300 as being electrically conductive further putting a first external lead and the no-lead contacts in electrical connection).
Regarding Claim 16, Miyazaki teaches the semiconductor package of claim 8, wherein the first external lead and one or more of the first set of no-lead contacts are part of a continuous leadframe segment (Fig. 3A, para [0047] describes a continuous leadframe 300 comprising first leads 310 and second leads 311 attached to an IC die 101 as also shown in Fig. 1A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshi Miyazaki (US 2014/0210062 A1; hereinafter “Miyazaki”) in view of Jae Ung Lee et al. (US 8,921,955 B1; hereinafter “Lee”).
Regarding Claim 6, Miyazaki discloses all the limitations of claim 1.
Miyazaki fails to explicitly disclose the semiconductor package of claim 1, wherein the second external lead comprises: a half etched end portion within the mold compound, the end portion having half etched tabs that extend laterally from the second external lead and that are not exposed on the bottom surface of the package, and the second external lead is not directly electrically coupled to the IC die.
However, Lee teaches a similar semiconductor package, wherein the second external lead (112, annotated Fig. 9E, column 11, lines 60-63 describes a plurality of leads extending along a peripheral edge of the device wherein a second external lead SEL extends from a left side of the semiconductor package 300) comprises: a half etched end portion within the mold compound (312, annotated Fig. 9E, column 12, lines 6-9 describe wherein the leads 312 comprise half-etched inner end portions wherein the second external lead SEL comprises a half-etched inner end portion HEP encapsulated by a body 320 of the package 300 as described in column 13, lines 10-13), the end portion having half etched tabs that extend laterally from the second external lead and that are not exposed on the bottom surface of the package (312, annotated Fig. 9E depicts wherein the end portion having half-etched tabs HEP extend laterally from the second external lead and are encapsulated by encapsulant 320 therefore not being exposed on a bottom surface of the package 300), and the second external lead is not directly electrically coupled to the IC die (annotated Fig. 9E depicts wherein second external lead SEL is not directly electrically coupled to the IC die 330 or 340 as it has an end portion encapsulated by encapsulant 320 and does not comprise a wire conductive wire 350 bonding it to the IC dies such as first external lead FEL on the opposite side of the package 300).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki with Lee to further disclose a semiconductor package comprising a half-etched tab of a second external lead within a mold compound of the semiconductor package and not directly electrically coupled to the integrated circuit die in order to provide the well-known advantage of providing mechanical support and balance for mounting an external device to a semiconductor package providing further providing an additional point of contact increasing stability during an external device mounting process.
Regarding Claim 17, Miyazaki discloses all the limitations of claim 8.
Miyazaki fails to explicitly disclose the semiconductor package of claim 8, wherein the second external lead is not directly electrically coupled to semiconductor die.
However, Lee teaches a similar semiconductor package, wherein the second external lead is not directly electrically coupled to semiconductor die (annotated Fig. 9E depicts wherein a second external lead SEL is not directly electrically coupled to an IC die 330 or 340 as it has an end portion encapsulated by an encapsulant 320 and does not comprise a wire conductive wire 350 bonding it to the IC dies such as first external lead FEL on the opposite side of the package 300).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki with Lee to further disclose a semiconductor package comprising a second external lead not directly electrically coupled to an integrated circuit die in order to provide the well-known advantage of providing mechanical support and balance for mounting an external device to a semiconductor package providing further providing an additional point of contact increasing stability during an external device mounting process.
Regarding Claim 18, Miyazaki discloses all the limitations of claim 8.
Miyazaki fails to explicitly disclose the semiconductor package of claim 8, wherein the second external lead comprises: a half etched end portion within the encapsulant, the end portion having half etched tabs extending laterally from the second external lead and not exposed on a bottom surface of the package.
However, Lee teaches a similar semiconductor package, wherein the second external lead (112, annotated Fig. 9E, column 11, lines 60-63 describes a plurality of leads extending along a peripheral edge of the device wherein a second external lead SEL extends from a left side of the semiconductor package 300) comprises:
a half etched end portion within the encapsulant (312, annotated Fig. 9E, column 12, lines 6-9 describe wherein the leads 312 comprise half-etched inner end portions wherein the second external lead SEL comprises a half-etched inner end portion HEP encapsulated by a body 320 of the package 300 as described in column 13, lines 10-13), the end portion having half etched tabs extending laterally from the second external lead and not exposed on a bottom surface of the package (312, annotated Fig. 9E depicts wherein the end portion having half-etched tabs HEP extend laterally from the second external lead and are encapsulated by encapsulant 320 therefore not being exposed on a bottom surface of the package 300).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki with Lee to further disclose a semiconductor package comprising a half-etched tab of a second external lead extending laterally within an encapsulant of the semiconductor package in order to provide the well-known advantage of providing mechanical support and balance for mounting an external device to a semiconductor package providing further providing an additional point of contact increasing stability during an external device mounting process.
Claims 7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshi Miyazaki (US 2014/0210062 A1; hereinafter “Miyazaki”) in view of Yeou Chian Chang et al. (US 2022/0359350 A1; hereinafter “Chang”).
Regarding Claim 7, Miyazaki discloses all the limitations of claim 1.
Miyazaki fails to explicitly disclose the semiconductor package of claim 1, wherein each of the no-lead contacts comprise half etched portions that are not exposed through the mold compound on the bottom surface of the package.
However, Chang teaches a similar semiconductor package, wherein each of the no-lead contacts comprise half etched portions that are not exposed through the mold compound on the bottom surface of the package (108, Fig. 8, para [0010] describes wherein a plurality of leads 104 disposed on a bottom edge of a semiconductor package 100 further comprises an inner half-etched, reduced thickness portion 108 that is not exposed through a mold compound 702 on a bottom surface of the package).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki with Chang to further disclose a semiconductor package wherein no-lead contacts comprise half-etched portions that are not exposed through a mold compound in order to provide the advantage of providing for a secure connection between a die pad and a long half-etched lead which further reinforces the half-etched leads and provides for a device with improved yields, lower costs, and greater overall reliability (Chang, para [0025]).
Regarding Claim 19, Miyazaki discloses all the limitations of claim 8.
Miyazaki fails to explicitly disclose the semiconductor package of claim 8, wherein each of the first set of no-lead contacts comprise half etched portions that are not exposed through the encapsulant on a bottom surface of the package.
However, Chang teaches a similar semiconductor package wherein each of the first set of no-lead contacts comprise half etched portions that are not exposed through the encapsulant on a bottom surface of the package (108, Fig. 8, para [0010] describes wherein a plurality of leads 104 disposed on a bottom edge of a semiconductor package 100 further comprises an inner half-etched, reduced thickness portion 108 that is not exposed through an encapsulant 702 on a bottom surface of the package).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki with Chang to further disclose a semiconductor package wherein no-lead contacts comprise half-etched portions that are not exposed through an encapsulant in order to provide the advantage of providing for a secure connection between a die pad and a long half-etched lead which further reinforces the half-etched leads and provides for a device with improved yields, lower costs, and greater overall reliability (Chang, para [0025]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hiroshi Miyazaki (US 2014/0210062 A1; hereinafter “Miyazaki”) in view of Sreenivasan K. Allen Koduri (US 2020/0411420 A1; hereinafter “Koduri”).
Regarding Claim 20, Miyazaki discloses all the limitations of claim 8.
Miyazaki fails to explicitly disclose the semiconductor package of claim 8, further comprising: an electrical device attached to top ends of the first and second external leads above the top surface of the encapsulant.
However, Koduri teaches a similar semiconductor package further comprising:
an electrical device attached to top ends of the first and second external leads above the top surface of the encapsulant (1304, Fig. 14, para [0044] describes connecting a passive component 1304 to upper gull wing leads 120 and 140 extending above the top surface of an encapsulant 102).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Miyazaki with Koduri to further disclose a semiconductor package comprising an electrical device above the top surface of the encapsulant and coupled to external leads in order to provide the advantage of increasing functionality and performance with close coupling between a passive component and a semiconductor package (Koduri, para [0044] and para [0045]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Thursday 7:00 am - 5:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898