DETAILED ACTION
This Office action is in response to the Amendment submitted on 11 June 2026/ Claims 1-20 are pending in the application. Claims 16-20 have been withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Dependent claim 9 requires “a first chip bump group between the second semiconductor chip and the second package substrate. However, claim 9 is confusing, since independent claim 1, from which claim 9 depends, already requires the semiconductor package to comprise “a first chip bump group between the second semiconductor chip and the second package substrate”. Is dependent claim 9 intended for the semiconductor package to further comprise a second chip bump group?
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 9 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Dependent claim 9 requires “a first chip bump group between the second semiconductor chip and the second package substrate. However, claim 9 is confusing, since independent claim 1, from which claim 9 depends, already requires the semiconductor package to comprise “a first chip bump group between the second semiconductor chip and the second package substrate”. Therefore, dependent claim 9 fails to further limit the subject matter of independent claim 1 upon which claim 9 depends.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7-11 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Lu, US 2021/0125965, newly cited.
With respect to claim 1, Lu discloses a semiconductor package, shown in Fig. 7K, comprising:
a first package substrate 74/74g including a first area, see Fig. 7K and paragraph [0123];
a first semiconductor chip 10c on the first area;
a second package substrate 11 on an upper surface of the first semiconductor chip 10c, the second package substrate 11 including a second area and a first hole penetrating through the second area, see Fig. 7I and paragraphs [0036]-[0041];
a second semiconductor chip 10a on the second area;
a connection member 16 electrically connecting the first package substrate 74/74g and the second package substrate 11, the connection member being between the first package substrate 74/74g and the second package substrate 11, as shown in Fig. 7K;
a mold film 13 covering the second semiconductor chip 10a on the second package substrate 11, filling the first hole, and covering the first semiconductor chip 10c and the connection member 16 on the first package substrate 74/74g, see Figs. 7J and 7K; and
a first chip bump group 121 between the second semiconductor chip 10a and the second package substrate 11 such that an upper end of the first chip bump group 121 is in physical contact with a lower surface of the second semiconductor chip 10a and a lower end of the first chip bump group 121 is in physical contact with an upper surface of the second package substrate 11, as shown in annotated Fig. 7K below.
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With respect to claim 7, in the semiconductor package of Lu, the second area overlaps the second semiconductor chip 10a on an upper surface of the second package substrate 11 in a vertical view, as shown in annotated Fig. 7K below.
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With respect to claim 8, in the semiconductor package of Lu, the first hole is at a central part of the second area of the second package substrate 11, as shown in annotated Fig. 7K above.
With respect to claim 9, the semiconductor package of Lu further comprises a first chip bump group 121 between the second semiconductor chip10a and the second package substrate 11, as shown in Fig. 7K above..
With respect to claim 10, in the semiconductor package of Lu, the first chip bump group 121 includes a third chip bump 121 on a first side of the first hole and a fourth chip bump 121 on a second side of the first hole, see annotated Fig. 7K above.
With respect to claim 11, in the semiconductor package of Lu, the first hole extends along a first direction parallel to a lower surface of the second semiconductor chip 10a, the third chip bump 121 includes a plurality of third chip bumps 121 that are along the first direction, and the fourth chip bump 121 includes a plurality of fourth chip bumps 121 that are along the first direction, see annotated Fig. 7K above.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Yang, US 2024/0178083, newly cited.
With respect to claim 1, Yang discloses a semiconductor package, shown in Fig. 1, comprising:
a first package substrate 2 including a first area, see Fig. 1;
a first semiconductor chip 3 on the first area;
a second package substrate 5 on an upper surface of the first semiconductor chip 3, the second package substrate 5 including a second area and a first hole 54 penetrating through the second area, as shown in Fig. 1;
a second semiconductor chip 6 on the second area;
a connection member 73 electrically connecting the first package substrate 2 and the second package substrate 5, the connection member 73 being between the first package substrate 2 and the second package substrate 5, as shown in Fig. 1;
a mold film 8/13 covering the second semiconductor chip 6 on the second package substrate 5, filling the first hole 54, and covering the first semiconductor chip 3 and the connection member 73 on the first package substrate 2, see Fig. 1; and
a first chip bump group 64a/64b between the second semiconductor chip 6 and the second package substrate 5 such that an upper end of the first chip bump group 64b is in physical contact with a lower surface of the second semiconductor chip 6 and a lower end of the first chip bump group 64a/64b is in physical contact with an upper surface of the second package substrate 5, as shown in Fig. 1.
With respect to claim 2, the semiconductor package of Yang further comprises: a second hole 24 penetrating through the first package substrate 2, as shown in Fig. 1.
With respect to claim 3, in the semiconductor package of Yang, the second hole 24 penetrates through the first area, as shown in Fig. 1.
With respect to claim 4, in the semiconductor package of Yang, the mold film 8/13 fills the second hole 24.
With respect to claim 5, the semiconductor package of Yang, further comprises: a -second chip bump group 34a/34b formed between the first semiconductor chip 3 and the first package substrate 2, as shown in Fig. 1.
With respect to claim 6, in the semiconductor package of Yang, the second chip bump group 34a/34b includes a first chip bump 34b on a first side of the second hole 24 and a second chip bump 34a disposed on a second side of the second hole 24, as shown in Fig. 1.
With respect to claim 7, in the semiconductor package of Yang, the second area overlaps the second semiconductor chip 6 on an upper surface of the second package substrate 5 in a vertical view, as shown in Fig. 1.
With respect to claim 8, in the semiconductor package of Yang, the first hole 54 is at a central part of the second area of the second package substrate 5, as shown in Fig. 1.
With respect to claim 9, the semiconductor package of Yang further comprises a first chip bump group 64b between the second semiconductor chip 6 and the second package substrate 5, as shown in Fig. 1.
With respect to claim 10, in the semiconductor package of Yang, the first chip bump group 64a/64b includes a third chip bump 64b on a first side of the first hole 54 and a fourth chip bump 64a on a second side of the first hole 54, as shown in Fig. 1.
With respect to claim 11, in the semiconductor package of Yang, the first hole 54 extends along a first direction parallel to a lower surface of the second semiconductor chip 6, the third chip bump 64b includes a plurality of third chip bumps 64b that are along the first direction, and the fourth chip bump 64a includes a plurality of fourth chip bumps 64a that are along the first direction, see Figs. 1 and 2 of Yang.
With respect to claim 12, Yang discloses a semiconductor package, shown in Fig. 1, comprising:
a first package substrate 2;
an upper pad 431 exposed from an upper surface of the first package substrate 2;
a first semiconductor chip 3 on the upper surface of the first package substrate 2, as shown in Fig. 1;
a second package substrate 5 on an upper surface of the first semiconductor chip 3 and spaced apart from the upper surface of the first semiconductor chip 3, as shown in Fig. 1;
a lower pad 73 exposed from a lower surface 52/53 of the second package substrate 5, see Figs. 1 and 29;
a second semiconductor chip 6 on an upper surface of the second package substrate 5, as shown in Fig. 1;
a connection member 432 electrically connecting the first package substrate 2 and the second package substrate 5, the connection member 432 being in direct contact with the upper pad 431 and the lower pad 73; and
a mold film 8/13 covering the first semiconductor chip 3 and the connection member 432 on the first package substrate 2 and covering the second semiconductor chip 6 on the second package-substrate 5, as shown in Fig. 1; and
a first chip bump group 64b between the second semiconductor chip 6 and the second package substrate 5 such that an upper end of the first chip bump group 64b is in physical contact with a lower surface of the second semiconductor chip 6 and a lower end of the first chip bump group 64b is in physical contact with an upper surface of the second package substrate 5, as shown in Fig. 1,
wherein the first package substrate 2 includes a first hole 24 penetrating through the first package substrate 2 in a first direction,
the second package substrate 5 includes a second hole 54 penetrating through the second package substrate 5 in the first direction,
the first hole 24 overlaps the first semiconductor chip 3 in plan view (see Fig. 2), and the second hole 54 overlaps the second semiconductor chip 6 in plan view (see Fig. 4).
With respect to claim 13, in the semiconductor package of Yang, the mold film 8/13 fills both the first hole 24 and the second hole 54, as shown in Fig. 1.
With respect to claim 14, the semiconductor package of Yang further comprises: a second chip bump group 34b between a lower surface of the first semiconductor chip 3 and the upper surface of the first package substrate 2, the second chip bump group 34b electrically connecting the first semiconductor chip 3 and the first package substrate 2, as shown in Fig. 1.
With respect to claim 15, in the semiconductor package of Yang, the mold film 8/12 fills a space between the lower surface of the first semiconductor chip 3 and the upper surface of the first package substrate 2 and covers the second chip bump group 34b, as shown in Fig. 1.
Response to Arguments
Applicant’s arguments with respect to claims 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Upon the allowance of device claims 1-15, process claims 16-20 will be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product/apparatus claim for that process invention to be rejoined.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose various semiconductor packages having stacked semiconductor chips.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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