DETAILED ACTION
This Office action is in response to the election filed on 25 November 2025. Claims 1-20 are pending in the application. Claims 16-20 have been withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of the invention of Group I, on which claims 1-15 are readable, in the reply filed on 25 November 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-8, and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Haba et al., US 2015/0200183.
With respect to claim 1, Haba et al. disclose a semiconductor package, shown in Fig. 3A, comprising:
a first package substrate 112 including a first area;
a first semiconductor chip 140 on the first area;
a second package substrate 112 on an upper surface of the first semiconductor chip, the second package substrate 112 including a second area and a first hole penetrating through the second area;
a second semiconductor chip 140 on the second area;
a connection member 156 electrically connecting the first package substrate 112 and the second package substrate 112, the connection member being between the first package substrate 112 and the second package substrate 112; and
a mold film 152 covering the second semiconductor chip 140 on the second package substrate 112, filling the first hole, and covering the first semiconductor chip and the connection member 156 on the first package substrate 112, as shown in annotated Fig. 3A below, see paragraph [0052]-0053].
With respect to claim 2, the semiconductor package of Haba et al. further comprises: a second hole penetrating through the first package substrate 112, as shown in annotated Fig. 3A below.
With respect to claim 3, in the semiconductor package of Haba et al., the second hole penetrates through the first area (the area on which the first semiconductor chip is disposed, as shown in annotated Fig. 3A below.
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With respect to claim 4, in the semiconductor package of Haba et al., the mold film 152 fills the second hole, as shown in annotated Fig. 3 above.
With respect to claim 7, in the semiconductor package of Haba et al., the second area overlaps the second semiconductor chip 140 on an upper surface of the second package substrate 112 in a vertical view, as shown in annotated Fig. 3A below.
With respect to claim 8, in the semiconductor package of Haba et al., the first hole is at a central part of the second area of the second package substrate 112, see annotated Fig. 3A above which shows the first hole and annotated Fig. 3A below.
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With respect to claim 12, Haba et al. disclose a semiconductor package , shown in Fig. 3A, comprising:
a first package substrate 112;
an upper pad 128 exposed from an upper surface of the first package substrate 112;
a first semiconductor chip 140 on the upper surface of the first package substrate 112;
a second package substrate 112 on an upper surface of the first semiconductor chip 140 and spaced apart from the upper surface of the first semiconductor chip, as shown in Fig. 3A;
a lower pad 126 exposed from a lower surface of the second package substrate 112;
a second semiconductor chip 140 on an upper surface of the second package substrate 112;
a connection member 156 electrically connecting the first package substrate 112 and the second package substrate 112, the connection member 156 being in direct contact with the upper pad 126 and the lower pad 128; and
a mold film 152 covering the first semiconductor chip 140 and the connection member 156 on the first package substrate 112 and covering the second semiconductor chip 140 on the second package substrate 112,
wherein the first package substrate 112 includes a first hole penetrating through the first package substrate 112 in a first direction (horizontal direction),
the second package substrate 112 includes a second hole penetrating through the second package substrate in the first direction (horizontal direction),
the first hole overlaps the first semiconductor chip 140 in plan view (since the first semiconductor chip is centered over the first hole, as shown in annotated Fig. 3A below), and
the second hole overlaps the second semiconductor chip 140 in plan view (since the second semiconductor chip is centered over the second hole, as shown in annotated Fig. 3A below), see paragraph [0052]-0053] and annotated Fig. 3A below.
With respect to claim 13, as shown in annotated Fig. 3A below, in the semiconductor package of Haba et al., the mold film 152 fills both the first hole and the second hole.
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Claims 1 and 9-11 are is/are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Lee et al., US 2021/0272880.
With respect to claim 1, Lee et al. disclose a semiconductor package, shown in Fig. 1C, comprising:
a first package substrate 110 including a first area;
a first semiconductor chip 120 on the first area;
a second package substrate 180/210 on an upper surface of the first semiconductor chip 120, the second package substrate 180/210 including a second area 180 and a first hole penetrating through the second area 180;
a second semiconductor chip 220 on the second area;
a connection member CT1 electrically connecting the first package substrate 110 and the second package substrate 180/210, the connection member being between the first package substrate 110 and the second package substrate 180/210; and
a mold film MD1/MD2/MD3 covering the second semiconductor chip 220 on the second package substrate 180/210 (MD3), filling the first hole (in 180, MD1), and covering the first semiconductor chip 120 (MD1) and the connection member CT1 (MD2) on the first package substrate 110, as shown in annotated Fig. 1C of Lee et al.
With respect to claim 9, the semiconductor package of Lee et al. further comprises: a second chip bump group CT2 between the second semiconductor chip 220 and the second package substrate 180, as shown in Fig. 1C.
With respect to claim 10, the semiconductor package of Lee et al., the second chip bump group includes a third chip bump on a first side of the first hole and a fourth chip bump on a second side of the first hole, as shown in annotated Fig. 1C below.
With respect to claim 11, in the semiconductor package of Lee et al., the first hole extends along a first direction parallel to a lower surface of the second semiconductor chip 220 (horizontal direction),the third chip bump includes a plurality of third chip bumps that are along the first direction, and the fourth chip bump includes a plurality of fourth chip bumps that are along the first direction, as shown in annotated Fig. 1C below.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5-6 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Haba et al., US 2015/0200183, as applied to claims 1 and 12 above.
With respect to claims 5, in the semiconductor package of Haba et al. shown in Fig. 3A, Haba et al. lack anticipation of the semiconductor package further comprising: a first chip bump group formed between the first semiconductor chip 140 and the first package substrate 112. However, in an alternate embodiment disclosed by Haba et al., shown in Fig. 10, Haba et al. teach that the first semiconductor chip 540 can be electrically connected to package substrate 576 using a first chip bump group. Therefore, in light of the embodiment of Haba et al. shown in Fig. 10, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a first chip bump group could have been formed between the first semiconductor chip 140 and the first package substrate 112 in the semiconductor package of Haba et al. shown in Fig. 3A, since this is a known alternate way of electrically connecting a first semiconductor chip to an underlying package substrate.
With respect to claim 6, as shown in Fig. 10 of Haba et al., the first chip bump group includes a first chip bump on a first side of the second hole and a second chip bump disposed on a second side of the second hole, as shown in annotated Fig. 10 below. Therefore, in light of what is shown in Fig. 10 of Haba et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that electrically connecting the first semiconductor chip 140 in the semiconductor package shown in Fig. 3A of Haba et al. would include a first chip bump on a first side of the second hole and a second chip bump disposed on a second side of the second hole.
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With respect to claim 14, in the semiconductor package of Haba et al. shown in Fig. 3A, Haba et al. lack anticipation of the semiconductor package further comprising: a first chip bump group between a lower surface of the first semiconductor chip 140 and the upper surface of the first package substrate 212, the first chip bump group electrically connecting the first semiconductor chip 140 and the first package substrate 112. However, in an alternate embodiment disclosed by Haba et al., shown in Fig. 10, Haba et al. teach that the first semiconductor chip 540 can be electrically connected to package substrate 576 using a first chip bump group. Therefore, in light of the embodiment of Haba et al. shown in Fig. 10, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a first chip bump group could have been formed between the first semiconductor chip 140 and the first package substrate 112 in the semiconductor package of Haba et al. shown in Fig. 3A, the first chip bump group electrically connecting the first semiconductor chip 140 and the first package substrate 112, since Haba et al. clearly teach that this is a known alternate way of electrically connecting a first semiconductor chip to an underlying package substrate.
With respect to claim 15, in the semiconductor package of Haba et al., it is clearly shown in Fig. 3A that the mold film 152 fills a space between the lower surface of the first semiconductor chip 140 and the upper surface of the first package substrate 112. Furthermore, Haba et al. show in both Fig. 3A and Fig 10 that the means for electrically connecting the first semiconductor chip 140 to the first package substrate are covered by a mold film. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that to cover the first chip bump group with mold film 152, since Haba et al. show in Fig. 10 that the first chip bump group is encapsulated.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references discloses various stacked chip packages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898