DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner is in the opinion that paragraphs 0068, 0069 and 0092 along with Figs. 3A and (especially) 3B of the instant application as published (20240079237), potentially, contain allowable subject matter (especially with respect to the protective layers and especially in paragraph 0068). The applicant is kindly requested to schedule for an interview for further explanation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oka et al. (9,331,157).
Regarding Claim 1, in Figs. 1 and 2, column 6, line 20 to column 9, line 37 and in Fig. 4, column 9 line 66 to column 10, line 15, Oka et al. discloses a method of manufacturing an electronic device, comprising: forming, in a semiconductor body 100 of silicon carbide, a first implanted region 140/132 which extends into the semiconductor body facing a first side of the semiconductor body; forming, in contact with the semiconductor body at the first implanted region, a reaction layer 240 of a metal material; forming an ohmic contact 140 at the first implanted region, by performing a thermal process for allowing a reaction between the metal material and the material of the semiconductor body at the first implanted region for forming a silicide of the metal material (see Fig. 2, step 160 and column 9, lines 23-30); and forming one or more electrical structures 340/250 of the electronic device, the electrical structures including one or more materials that may be damaged by the thermal process (column 7, lines 49-64 and Fgis. 2, step S170 and column 9 lines 31-37), wherein the forming the ohmic contact is performed prior to the forming the one or more electrical structures of the electronic device (see Figs. 2, step 160).
With respect to the newly added limitation of a gate dielectric on the semiconductor body; a gate metallization with a first face on the gate dielectric, the first face of the gate metallization being opposite a second face; and an insulating layer covering the second face and a first sidewall of the gate metallization, although Figs. 1 and 2 do not show such insulating layer (i.e., inter layer insulating layer), such insulating layer is disclosed in Fig. 7, as element 810, where it is shown a gate dielectric 740 on the semiconductor body; a gate metallization 650 with a first face on the gate dielectric, the first face of the gate metallization being opposite a second face; and an insulating 810 layer covering the second face and a first sidewall of the gate metallization.
Please note that secondary reference used in rejection of claims 15-20 below, namely Wada 20150295059 (Figs 13 and 14, elements 40/41) also discloses interlayer insulating layer
Regarding Claim 2, the step of forming the one or more electrical structures 340/250comprises forming an electrical control terminal of the electronic device.
Regarding Claim 3, the electrical control terminal 340/250 of the electronic device is a gate terminal and comprises a gate dielectric 340 and a gate conductive layer 250 on the gate dielectric, the gate dielectric including the material which may be damaged by the thermal process.
Regarding Claim 4, the gate dielectric material 340 is a high-k (since it is not claimed a specific material. In other words, the examiner takes the view that element 340 which is a silicon dioxide material could be considered a high-k material)
Regarding Claim 6, in Oka et al., the step of forming a second implanted region 130 prior to the step of forming the first implanted region 140, the first implanted region being completely contained within the second implanted region.
Regarding Claim 7, in Oka et al, the second implanted region 130 is a body region of the electronic device and has a first electrical conductivity and a first concentration of doping species, the first implanted region 140 being one of: a source region having a second electrical conductivity opposite to the first electrical conductivity; and a body contact region having the first electrical conductivity and a second concentration of doping species greater than the first concentration of doping species.
Regarding Claim 8, in Oka et al, the control terminal 340/250 extends laterally to the first implanted region.
Regarding Claim 9, in Oka et al., the step of forming a conductive terminal in electrical contact with the ohmic contact. (See Fig. 7, columns 15, lines 1-10)
Regarding Claim 10, in Oka et al., in Figs. 1, 2 and 4, the one or more further electrical structures of the electronic device comprises depositing one or more dielectric or insulating materials, in particular by ALD technique
Regarding Claim 11, in Figs. 1, 2 and 4 of Oka et al., comprising the steps of forming, at and above the ohmic contact, a multilayer for completely covering the ohmic contact, the multilayer comprising a first protective layer of Silicon Oxide and a second protective layer of Silicon Nitride, the step of forming one or more further electrical structures of the electronic device being performed after forming the first and the second protective layers.
Regarding Claim 12, in Figs. 1, 2 and 4 of Oka et al., it is disclosed the step of forming, on the first side of the semiconductor body, a mask having a through opening at least one surface portion of the first implanted region, the reaction layer being formed above the mask and in contact with the surface portion; the method further comprising, prior to the step of forming the ohmic contact, the step of removing the mask and metal material of the unreacted reaction layer.
Regarding Claim 13, in Oka et al., the electronic device is a MOSFET.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Oka et al. (9,331,157) in view of Tenaglia (20140021623).
Regarding Claim 5, Oka et al. discloses everything except to disclose the required temperature range. However, Tenaglia discloses a method of forming electronic contact interface regions of an electronic device where in paragraph 0011 the required temperature range is disclosed.
It would have been obvious to one of having ordinary skill in the art at the claimed invention before the effective filing date of the claimed invention to have the required temperature range in Oka et al. as taught by Tenaglia in order to have ohmic contact with having reliable interface with the doped regions.
Regarding Claim 14, Oka et al. discloses everything except to disclose the required SiC material type. However, Tenaglia discloses a method of forming electronic contact interface regions of an electronic device where paragraph 0004 the required SiC material type is disclosed.
It would have been obvious to one of having ordinary skill in the art at the claimed invention was effectively filed to have the required SiC material type in Oka et al. as taught by Tenaglia in order to have ohmic contact with having reliable interface with the doped regions.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tenaglia (2014/0021623) in view of Wada (2015/0295059)
Regarding Claim 15, in Figs. 1-4, paragraphs 0007-0013, Tenaglia discloses a method, comprising: forming a first source region 5/6 in a first side of a semiconductor body, forming a metal layer 8/9/13 coupled to the first source region and the first side of the semiconductor body; forming a first ohmic contact 8/9/13 in the first source region; forming a gate dielectric layer 3a on the first side of the semiconductor body, the gate dielectric layer being coupled to the first ohmic contact; forming a conductive layer 3b on the gate dielectric layer; forming a first opening through the gate dielectric layer and the conductive layer, the first opening exposing the first ohmic contact; forming an insulating layer covering the gate dielectric layer and the conductive layer; and forming a metallization layer 8/9 on the insulating layer the metallization layer being coupled to the first ohmic contact (also see paragraph 0011).
Tenaglia fails to disclose the newly added limitation of a first insulating layer covering the gate dielectric layer and the conductive layer, the first insulating layer having a first sidewall opposite a second sidewall; forming a metallization layer on the first insulating layer the metallization layer being coupled to the first ohmic contact; and forming a second insulating layer on the metallization layer, the second insulating layer having a first sidewall coplanar with the first sidewall of the first insulating layer and second sidewall coplanar with the second sidewall of the first insulating layer, i.e. the coplanar relationship between the first interlayer insulating film and the second interlayer insulating film. However, such first and second insulating films are disclosed as elements 40 and 41 in Figs. 13 and 14 of Wada.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required first and second insulating layers in Tenaglia as taught by Wada in order to protect the gate structure.
Regarding Claim 16, in Tenaglia the forming the gate dielectric layer 3a includes photolithography.
Regarding Claim 17, the forming a first ohmic contact includes a high-temperature thermal annealing process, wherein a reaction occurs between the metal layer and the semiconductor body (see Figs.2, paragraphs 0009-0011).
Regarding Claim 18, in Figs 1-4 and paragraphs 0007-0013, Tenaglia discloses a method of forming electronic contact interface regions of an electronic device, comprising: forming a first body well 5/6 in a first side of a semiconductor body, the first body well having a first side coplanar with the first side of the semiconductor body; forming a first source region 5/6 in the first body well, the first source region having a first side coplanar with the first side of the semiconductor body; forming a first implanted region in the first source region, the first implanted region having a first side coplanar with the first side of the semiconductor body; forming a deposition mask layer on the first side of the semiconductor body, the deposition mask layer having a first opening exposing the first source region; forming a metal layer 8/9/13 on the deposition mask layer, the metal layer being coupled to the first source region through the first opening in the deposition mask layer; and forming a first ohmic contact 8/9/13 in the first source region.
Tenaglia fails to disclose the newly added limitation of forming a gate dielectric layer on the first side of the semiconductor body, the gate dielectric layer covering the first side of the first source region and exposing the first ohmic contact; forming a first gate metallization on the gate dielectric layer; and forming an insulating layer on the first gate metallization, the first insulating layer having a first sidewall coplanar with a first sidewall of the gate dielectric layer, i.e. the coplanar relationship between the first/second insulating layer and the gate dielectric layer. However, such coplanar relationship is disclosed in Figs. 13 and 14 of Wada as elements 20 (gate dielectric) and 40/41 (first/second (interlayer) insulating layers).
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required coplanar relationship in Tenaglia as taught by Wada in order to protect the gate structure.
Regarding Claim 19, in Figs. 1-4 of Tenaglia the metal layer and the deposition mask layer after the forming the first ohmic contact.
Regarding Claim 20, in Figs 1-4 of Tenaglia, first body well 5/6has a first doping type and a first doping concentration, and the first implanted region has the first doping type and a second doping concentration that is greater than the first doping concentration (see paragraph 0027)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 2/4/2026