Prosecution Insights
Last updated: May 29, 2026
Application No. 18/363,367

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

Non-Final OA §102§103
Filed
Aug 01, 2023
Priority
Mar 15, 2021 — JP 2021-041546 +1 more
Examiner
ARROYO, TERESA M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co. Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
353 granted / 491 resolved
+3.9% vs TC avg
Strong +23% interview lift
Without
With
+22.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
25 currently pending
Career history
533
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
80.4%
+40.4% vs TC avg
§102
9.4%
-30.6% vs TC avg
§112
7.3%
-32.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 491 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Group I (claims 1-14) in the reply filed on 3/19/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 8, 10-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP Publication No. 2012-033756 (Tsukahara, cited by Applicant). Tsukahara discloses (at least Figs. 1A-1C) 1. A semiconductor device comprising: a support member 14 including an obverse surface (top) facing one side in a thickness direction; a semiconductor element 18 including an element obverse surface (top) and an element reverse surface (bottom) that face away from each other in the thickness direction and a reverse surface electrode (drain electrode not shown, [0038]) disposed on the element reverse surface (bottom); and a conductive bonding material 28 that conductively bonds the obverse surface (top) of the support member 14 and the reverse surface electrode (drain electrode) to each other, wherein the semiconductor element 18 includes (4 side surfaces: right, left, top, bottom) a first element side surface and a second element side surface that face a first side and a second side (right and left), respectively, in a first direction (x) orthogonal to the thickness direction, and a third element side surface and a fourth element side surface that face a first side and a second side (top and bottom), respectively, in a second direction (y) orthogonal to the thickness direction and the first direction (x), as viewed in the thickness direction, the conductive bonding material 28 includes (4 edges: right, left, top, bottom) a first edge located on the first side in the first direction (x) relative to the first element side surface, a second edge located on the second side in the first direction (x) relative to the second element side surface, a third edge located on the first side in the second direction (y) relative to the third element side surface, and a fourth edge located on the second side in the second direction (y) relative to the fourth element side surface, a first distance between the first element side surface (right) and the first edge (right) in the first direction (x) is greater at opposite ends than at a center of the first element side surface (right) in the second direction (y), a second distance between the second element side surface (left) and the second edge (left) in the first direction (x) is greater at opposite ends than at a center of the second element side surface (left) in the second direction (y), a third distance between the third element side surface (top) and the third edge (top) in the second direction (y) is greater at opposite ends than at a center of the third element side surface (top) in the first direction (x), and a fourth distance between the fourth element side surface (bottom) and the fourth edge (bottom) in the second direction (y) is greater at opposite ends than at a center of the fourth element side surface (bottom) in the first direction (x). [i.e., the distance between the sides of the semiconductor element 18 to an edge of the exposed conductive material 28 is greater in a seepage region 28E at the four corners of the fixing region AR than along the groove 15 on the sides of the fixing region AR] Tsukahara discloses (at least Figs 1A-1C), [i.e., seepage region 28E is located in four corners, top right, bottom right, top left, bottom left] 2. The semiconductor device according to claim 1, wherein the first edge includes a first edge first portion, a first edge second portion and a first edge third portion, the first edge first portion extending in the second direction, the first edge second portion and the first edge third portion being connected to the first edge first portion, located outside the first edge first portion in the first direction, and located at an end closer to the third edge and at an end closer to the fourth edge, respectively, in the second direction, the second edge includes a second edge first portion, a second edge second portion and a second edge third portion, the second edge first portion extending in the second direction, the second edge second portion and the second edge third portion being connected to the second edge first portion, located outside the second edge first portion in the first direction, and located at an end closer to the third edge and at an end closer to the fourth edge, respectively, in the second direction, the third edge includes a third edge first portion, a third edge second portion and a third edge third portion, the third edge first portion extending in the first direction, the third edge second portion and the third edge third portion being connected to the third edge first portion, located outside the third edge first portion in the second direction, and located at an end closer to the first edge and at an end closer to the second edge, respectively, in the second direction, and the fourth edge includes a fourth edge first portion, a fourth edge second portion and a fourth edge third portion, the fourth edge first portion extending in the first direction, the fourth edge second portion and the fourth edge third portion being connected to the fourth edge first portion, located outside the fourth edge first portion in the second direction, and located at an end closer to the first edge and at an end closer to the second edge, respectively, in the second direction. Tsukahara discloses (at least Figs. 2A-2C), ([0075], the shape of the groove 15 may be asymmetrical in the inclination angle of the left and right side walls) 3. The semiconductor device according to claim 2, wherein the first edge second portion includes a first edge first inclined portion connected to the first edge first portion and extending in a third direction crossing the first direction and the second direction as viewed in the thickness direction, the first edge third portion includes a first edge second inclined portion connected to the first edge first portion and extending in a fourth direction crossing the first direction and the second direction as viewed in the thickness direction, the second edge second portion includes a second edge first inclined portion connected to the second edge first portion and extending in the fourth direction as viewed in the thickness direction, the second edge third portion includes a second edge second inclined portion connected to the second edge first portion and extending in the third direction as viewed in the thickness direction, the third edge second portion includes a third edge first inclined portion connected to the third edge first portion and extending in the third direction as viewed in the thickness direction, the third edge third portion includes a third edge second inclined portion connected to the third edge first portion and extending in the fourth direction as viewed in the thickness direction, the fourth edge second portion includes a fourth edge first inclined portion connected to the fourth edge first portion and extending in the fourth direction as viewed in the thickness direction, and the fourth edge third portion includes a fourth edge second inclined portion connected to the fourth edge first portion and extending in the third direction as viewed in the thickness direction. Tsukahara discloses (at least Figs. 1A-1C, 2A-2C), (the bonding material 28 is provided along the groove 15 on the sides and in four seepage regions 28E at the corners; a middle of the bonding material 28 on the sides is the intermediate portion; the bonding material 28 in the groove 15 is the extension) 4. The semiconductor device according to claim 3, wherein as viewed in the thickness direction, the conductive bonding material includes: a first intermediate portion located between the first element side surface and the first edge first portion, a second intermediate portion located between the second element side surface and the second edge first portion, a third intermediate portion located between the third element side surface and the third edge first portion, a fourth intermediate portion located between the fourth element side surface and the fourth edge first portion; a first extension including the first edge first inclined portion and the third edge first inclined portion and extending outward in the third direction from a first corner that is a boundary between the first element side surface and the third element side surface; a second extension including the first edge second inclined portion and the fourth edge first inclined portion and extending outward in the fourth direction from a second corner that is a boundary between the first element side surface and the fourth element side surface; a third extension including the second edge first inclined portion and the third edge second inclined portion and extending outward in the fourth direction from a third corner that is a boundary between the second element side surface and the third element side surface; and a fourth extension including the second edge second inclined portion and the fourth edge second inclined portion and extending outward in the third direction from a fourth corner that is a boundary between the second element side surface and the fourth element side surface. Tsukahara discloses ([0047]) 8. The semiconductor device according to claim 1, wherein the conductive bonding material 28 contains silver. Tsukahara discloses ([0036]-[0037]) 10. The semiconductor device according to claim 1, wherein the support member 14 is a first lead 12C including the obverse surface of the support member 14 and made of a metal plate. Tsukahara discloses ([0117]) 11. The semiconductor device according to claim 10, wherein the obverse surface of the first lead 12C includes a region overlapping with the conductive bonding material 28 as viewed in the thickness direction, and the region is formed with a plating layer. Tsukahara discloses (Figs. 1A-1C) 12. The semiconductor device according to claim 10, further comprising: a second lead 12A spaced apart from the first lead 12C as viewed in the thickness direction and made of a metal plate; and a first conductive member 16A, wherein the semiconductor element 18 includes a first obverse surface electrode 28 disposed on the element obverse surface, and the first conductive member 16A is connected to the first obverse surface electrode and the second lead 12A. Tsukahara discloses (Figs. 1A-1C) 13. The semiconductor device according to claim 12, further comprising: a third lead 12B spaced apart from the first lead 12C and the second lead 12A as viewed in the thickness direction and made of a metal plate; and a second conductive member 16B, wherein the semiconductor element 18 includes a second obverse surface electrode 28 disposed on the element obverse surface, and the second conductive member 16B is connected to the second obverse surface electrode 28 and the third lead 12B. Tsukahara discloses ([0038], not shown) 14. The semiconductor device according to claim 13, wherein the reverse surface electrode is a drain electrode (not shown), the first obverse surface electrode 28 is a source electrode, and the second obverse surface electrode 28 is a gate electrode. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Tsukahara fails to specifically disclose 5. The semiconductor device according to claim 4, wherein as viewed in the thickness direction, each of a first extension length from the first corner to an extremity of the first extension in the third direction, a second extension length from the second corner to an extremity of the second extension in the fourth direction, a third extension length from the third corner to an extremity of the third extension in the fourth direction, and a fourth extension length from the fourth corner to an extremity of the fourth extension in the third direction is 0.01 to 1 times a diagonal length from the first corner to the third corner of the semiconductor element. However, Tsukahara teaches the planar size of the support member 14 is slightly larger than the semiconductor element 18 mounted on the upper surface ([0034]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select 0.01 to 1 times a diagonal length from the first corner to the third corner of the semiconductor element as the extension length in Tsukahara. The motivation would be a matter of routine optimization. See MPEP 2144.05. Allowable Subject Matter Claims 6, 7 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. None of the cited prior art discloses or teaches 6. The semiconductor device according to claim 4, wherein a thickness of each of the first extension, the second extension, the third extension and the fourth extension is greater than a thickness of the first intermediate portion, the second intermediate portion, the third intermediate portion and the fourth intermediate portion. None of the cited prior art discloses or teaches 7. The semiconductor device according to claim 6, wherein the thickness of each of the first extension, the second extension, the third extension and the fourth extension is not greater than 2/3 of a thickness of the semiconductor element. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsukahara as applied to claim 1 above, and further in view of JP Publication No. 2019-029662 (Haga, cited by Applicant). Tsukahara fails to disclose 9. The semiconductor device according to claim 1, wherein the conductive bonding material comprises a sintered metal. Haga teaches A semiconductor device comprising: a conductive bonding material 3, wherein the conductive bonding material 3 comprises a sintered metal. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to choose a sintered material in Tsukahara. The motivation would be suitability for an intended purpose. See MPEP 2144.07. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. JP Publication Nos. 6-129107 (熊田 翔), 5-745238 (吉羽 茂治), 2009-170702 (Kikuchi), DE Publication Nos. 112021000198 (Yamano), 102007037538 (Kalich) teach a semiconductor device having conductive material seeping from the corners of a semiconductor element. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Aug 01, 2023
Application Filed
Apr 06, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
95%
With Interview (+22.9%)
3y 0m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 491 resolved cases by this examiner. Grant probability derived from career allowance rate.

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