DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed July 21, 2025 has been entered. Claims 1-20 remain pending in this application. Claims 1-2, 6, and 12-20 have been amended, with objections noted to follow. No claims have been added.
The prior office action dated May 6, 2025 identified the following informalities in the specification:
¶[0018] Brief Description of the Drawings: Figure 5A is described as, “Depicts a threshold voltage (Vt) distributions…” The subject-verb agreement in this description is incorrect. This error was not corrected by amendment despite other amendments made to this paragraph.
¶[0019] Brief Description of the Drawings: Figure 5B is described as, “Depicts a threshold voltage (Vt) distributions…” The subject-verb agreement in this description is incorrect. This error was not corrected by amendment despite other amendments made to this paragraph.
Amendments to the claims includes the annotation on Claim 14, (Currently Amended). Despite this annotation, changes to Claim 14 have not been marked as required by 37 C.F.R. 1.121. On comparison to the original text of Claim 14, as submitted on August 1, 2023, the July 21, 2025 version does not appear to have been changed and is perhaps labeled in error. For the purposes of this examination, Claim 14 will be treated as not having been amended.
Otherwise, applicant’s amendments to the Specification, Drawings, and Claims have overcome all remaining objections previously set forth in the Non-Final Office Action mailed May 6, 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-5 and 7-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 9,384,845 B2, to Niles Yang, et al. (hereafter Yang), in light of U.S. 2017/0090873 A1 to Lawrence T. Clark, et al. (hereafter Clark).
Regarding Independent Claim 1, Yang discloses an apparatus comprising:
one or more control circuits (Disclosing Controller circuit 100: Yang, col. 6:41-42; See Also Yang, Figure 1)
configured to connect to a memory structure having memory cells (Disclosing Controller 100 connected to memory structure 102: Yang, col. 6:41-42; See Also Yang, Figure 1),
wherein the one or more control circuits are configured (Disclosing memory cell source lines controlled by external circuits: Yang, col. 10:56-59) to:
perform a shallow erase of a group of the memory cells (Disclosing a partial erase scheme: Yang, col. 13:34-37; See Also Yang, Figure 13B)
while the group of memory cells are in a plurality of data states (Disclosing applying the partial erase scheme to memory cells in a plurality of data states: Yang, Figure 13A),
including apply one or more erase voltage pulses (Teaching applying a series of erase pulses during the partial erase phase: Yang, col.14:52);
add the group of the memory cells to a shallow erase pool (Disclosing the partially erased blocks added to a pool of partially erased blocks: Yang, col. 13:37-39)
after the shallow erase (Disclosing the partially erased block is added to pool of partially erased blocks following the partial erase operation: Yang, col. 34-39);
select the group of the memory cells from the shallow erase pool (Disclosing selecting the partially erased block from the pool of partially erased blocks: Yang, col. 15:6-8); and
perform a final erase of the group of the memory cells (Disclosing a final erase of the block of partially erased memory cells: Yang, 15:9-11; See Also Yang, Figure 13C)
after selection from the shallow erase pool (Disclosing the final erase step taking place following selection from the pool of partially erased blocks: Yang, col. 15:6-11),
including apply one or more erase voltage pulses each having a magnitude of at least the nominal erase voltage (Disclosing a final erase phase using a conventional erase scheme: Yang, col.15:9-10)
with an erase verify following each of the one or more erase voltage pulses (The final erase phase including erase verify: Yang, col.15:10-11).
Yang does not expressly disclose each of the shallow erase pulses having a magnitude of at least 5V below a nominal voltage. Clark, however, discloses a shallow erase phase wherein the pulses each have a magnitude of at least 5V below a nominal erase voltage (Disclosing a partial erase cycle of 2.2 volts compared to a standard erase cycle of 11.5 volts: Clark, ¶[0042]). Clark teaches greatly reducing the shallow erase voltage as compared to the nominal erase voltage and the duration of partial erase cycles reduces the erase rate (Clark, ¶[0039]).
Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the relatively large voltage differential of Clark with the shallow erase pool methodology of Yang, with a reasonable expectation of success. Each concept is a known invention in the careful erasing of NAND memory arrays, and combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2, Yang discloses the apparatus of claim 1, wherein the one or more control circuits are configured to:
complete the shallow erase (Disclosing the partial erase scheme being applied to the group of memory cells: Yang, col. 13:34-37)
with a single erase voltage pulse (Disclosing using the singular “a lower erase voltage” during the partial erase step, in combination with the suggestion of using fewer erase pulses suggests the use of a singular erase pulse: Yang, col. 14:56-58)
applied to the group of the memory cells (Disclosing the partial erase scheme being applied to the group of memory cells: Yang, col. 13:34-37)
without an erase verify (Disclosing performing the partial erase without an erase verification step: Yang, col. 13:63-65; See Also Yang, Figure 13B).
Regarding Claim 3, Yang discloses the apparatus of claim 1, wherein the one or more control circuits are configured to:
perform the shallow erase of the group of the memory cells (Disclosing the partial erase scheme being applied to the group of memory cells: Yang, col. 13:34-37)
with a first erase verify that tests the group of the memory cells at a first reference voltage (Disclosing testing the partial erase with a first erase verification voltage (ERV): Yang, col. 14:53-56); and
perform the final erase of the group of the memory cells (Disclosing a final erase step of the partially erased block: Yang, col. 15:9-11)
with a second erase verify that tests the group of the memory cells at a second reference voltage (Disclosing an erase verify step corresponding to an erased condition threshold voltage: Yang: col. 15:13-16)
that is lower than the first reference voltage (Disclosing a first erase verification voltage (ERV) that is higher than the erased threshold voltage range: Yang, col. 14:62-65).
Regarding Claim 4, Yang discloses the apparatus of claim 3, wherein
the first reference voltage is a positive voltage (Disclosing a first erase verification voltage that is a positive voltage: Yang, col. 14:65-67).
Regarding Claim 5, Yang discloses the apparatus of claim 4, wherein
the second reference voltage is a negative voltage (Disclosing an erased threshold voltage range that is negative: Yang, Figure 13C).
Regarding Claim 7, Yang discloses the apparatus of claim 1, wherein the one or more control circuits are further configured to:
erase the group of the memory cells (Disclosing the partial erase scheme being applied to the group of memory cells: Yang, col. 13:34-37)
to a non-negative median threshold voltage (Disclosing a first erase verification voltage that is a positive voltage: Yang, col. 14:65-67)
at a conclusion of the shallow erase (Disclosing the shallow erase step may be considered complete with a non-negative median threshold voltage: Yang, col. 14:65-67; See Also Yang, Figure 13B); and
erase the group of the memory cells (Disclosing a final erase step of the partially erased block: Yang, col. 15:9-11)
to a negative median threshold voltage (Disclosing an erased threshold voltage range that is negative: Yang, Figure 13C)
at a conclusion of the final erase (Disclosing an erase verify step corresponding to an erased condition threshold voltage: Yang: col. 15:13-16).
Regarding Claim 8, Yang discloses the apparatus of claim 1, wherein the one or more control circuits are further configured to:
erase the group of the memory cells (Disclosing the partial erase scheme being applied to the group of memory cells: Yang, col. 13:34-37)
to a non-negative mean threshold voltage (Disclosing a first erase verification voltage that is a positive voltage: Yang, col. 14:65-67)
at a conclusion of the shallow erase (Disclosing the shallow erase step may be considered complete with a non-negative median threshold voltage: Yang, col. 14:65-67; See Also Yang, Figure 13B); and
erase the group of the memory cells (Disclosing a final erase step of the partially erased block: Yang, col. 15:9-11)
such that substantially all of the memory cells in the group have negative threshold voltage (Disclosing an erased threshold voltage range that is negative: Yang, Figure 13C)
at a conclusion of the final erase (Disclosing an erase verify step corresponding to an erased condition threshold voltage: Yang: col. 15:13-16).
Regarding Claim 9, Yang discloses the apparatus of claim 1, wherein:
the memory cells are NAND memory cells (Disclosing the memory cells being arranged as NAND memory cells: Yang, col. 4:62-67; See Also Yang, Figure 4A);
the plurality of data states are associated with a corresponding plurality of threshold voltage distributions (Disclosing data cells programmed to a plurality of data states corresponding with threshold voltage distributions: Yang, Figures 6A-6C); and
the shallow erase compacts the plurality of threshold voltage distributions (Disclosing the partial erased state comprising compacted erase states: Yang, Figure 13B).
Regarding Claim 10, Yang discloses the apparatus of claim 1, wherein the one or more control circuits are configured to:
add additional shallow erased groups of memory cells to the shallow erase pool after adding the group of memory cells to the shallow erase pool (Disclosing adding a partially erased block to a pre-existing pool of partially erased blocks: Yang, col. 15:3-5; Since all blocks in the pool are described as partially erased, the ‘add additional’ after adding a first group is inherent); and
select the group of the memory cells from the shallow erase pool after adding the additional shallow erased groups of memory cells to the shallow erase pool (Disclosing subsequently selecting a partially erased block from the partially erased pool: Yang, col. 15:6-9).
Regarding Claim 11, Yang discloses the apparatus of claim 1, wherein the one or more control circuits are configured to:
maintain a fully erased pool of groups of memory cells (Disclosing a pool of fully erased memory blocks concurrently with a pool of partially erased memory cells: Yang, col. 15:32-35)
that have undergone the final erase after selection from the shallow erase pool (Suggesting the pool of fully erased memory blocks come from the pool of partially erased memory blocks: Yang, col. 15:20-23); and
program the groups of memory cells from the fully erased pool within a pre-determined time period (Disclosing programming the groups of fully erased memory cells within a pre-determined time period: Yang, col. 15:17-20).
Regarding Claim 12, Yang discloses the apparatus of claim 1, wherein the one or more control circuits are configured to:
select the group of the memory cells from the shallow erase pool (Disclosing selecting the partially erased block from the pool of partially erased blocks: Yang, col. 15:6-9)
responsive to identifying the group of memory cells in the shallow erase pool for near term programming (Disclosing selecting the partially erased block from the pool of partially erased blocks in response to a determination the block is to be programmed: Yang, col. 15:6-9), wherein
near term programming is to be performed within a pre-determined time period (Disclosing the partially erased block is subject to full erase and programming within a pre-determined time period: Yang, col. 15:15-19); and
program the group of the memory cells within the pre-determined time period after the final erase (Disclosing completing the program operation within a pre-determined time period following final erase: Yang, col. 15:16-23).
Regarding Independent Claim 13, Yang discloses a method for managing an erase pool of NAND memory blocks, the method comprising:
programming a group of memory cells (Disclosing first programming a block of memory cells: Yang, col. 14:46) in a first block of NAND memory cells (Disclosing memory cells being arranged as NAND memory cells: Yang, col. 4:62-67; See Also Yang, Figure 4A) to a plurality of data states (Disclosing a group of memory cells programmed to a plurality of data states: Yang, Figure 13A);
applying one or more shallow erase voltage pulses to the first block of NAND memory cells (Disclosing applying a series of limited erase voltages to the memory cells: Yang, col. 14:51-53)
while the group of memory cells are in the plurality of data states (Disclosing applying the first partial erase scheme to a group of memory cells in a plurality of data states: Yang, Figure 13A)
to shallow erase the first block (Disclosing the memory cells moving to an intermediate partially erased status: Yang, Figure 13B);
adding additional shallow erased blocks of NAND memory cells to the pool of shallow erased blocks after adding the first block to pool (Disclosing adding a partially erased block to a pre-existing pool of partially erased blocks: Yang, col. 15:3-5; Since all blocks in the pool are described as partially erased, the ‘add additional’ after adding a first group is inherent);
identifying the first block in the pool for near term programming after adding the additional shallow erased blocks to the pool (Disclosing subsequently selecting a partially erased block from the partially erased pool: Yang, col. 15:6-9); and
applying one or more nominal erase voltages to the first block (Disclosing a final erase of the block of partially erased memory cells: Yang, 15:9-11)
to fully erase the first block (Disclosing a final erase of the block of partially erased memory cells: Yang, 15:9-11; See Also Yang, Figure 13C)
in response to identifying the first block for near term programming (Disclosing selecting the partially erased block from the pool of partially erased blocks in response to a determination the block is to be programmed: Yang, col. 15:6-9),
including erase verifying following each of the one or more nominal erase voltage pulses, each nominal erase voltage pulse having a magnitude of at least the nominal erase voltage (Disclosing a final erase phase using a conventional erase scheme, including erase verification pulses: Yang, col.15:9-11).
Yang does not expressly disclose each of the shallow erase pulses having a magnitude of at least 5V below a nominal voltage. Clark, however, discloses a shallow erase phase wherein the pulses each have a magnitude of at least 5V below a nominal erase voltage (Disclosing a partial erase cycle of 2.2 volts compared to a standard erase cycle of 11.5 volts: Clark, ¶[0042]). Clark teaches greatly reducing the shallow erase voltage as compared to the nominal erase voltage and the duration of partial erase cycles reduces the erase rate (Clark, ¶[0039]).
Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the relatively large voltage differential of Clark with the shallow erase pool methodology of Yang, with a reasonable expectation of success. Each concept is a known invention in the careful erasing of NAND memory arrays, and combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 14, Yang discloses the method of claim 13, wherein
identifying the first block in the pool for near term programming (Disclosing subsequently selecting a partially erased block from the partially erased pool: Yang, col. 15:6-9)
includes identifying the block for programming within a pre-determined time period (Disclosing completing the program operation within a pre-determined time period following final erase: Yang, col. 15:16-23).
Regarding Claim 15, Yang discloses the method of claim 13, wherein:
applying the one or more shallow erase voltage pulses to the first block to shallow erase the first block (Disclosing a partial erase step in which first erase voltages are applied to a block of memory cells: Yang, col. 14:49-51) includes
erasing the memory cells in first block to a non-negative average threshold voltage (Disclosing testing the partial erase with a first erase verification voltage (ERV): Yang, col. 14:53-56; Where the ERV is non-negative: Yang, Figure 13B); and
applying the one or more nominal erase voltage pulses to the first block to fully erase the first block (Disclosing a conventional final erase voltage applied to fully erase the block: Yang, col. 15:9-11) includes
erasing substantially all of the memory cells in first block to a negative threshold voltage (Disclosing an erase verify step corresponding to an erased condition threshold voltage: Yang: col. 15:13-16; Where the erased condition threshold voltage is negative: Yang, Figure 13C).
Regarding Independent Claim 16, Yang discloses a non-volatile storage system, the system comprising:
a three-dimensional memory structure having NAND memory cells (Disclosing a three-dimensional memory structure including NAND memory cells: Yang, col. 16:3-7); and
one or more control circuits (Disclosing Controller circuit 100: Yang, col. 6:41-42; See Also Yang, Figure 1) configured to connect to the memory structure (Disclosing Controller 100 connected to memory structure 102: Yang, col. 6:41-42; See Also Yang, Figure 1), the one or more control circuits configured to:
program a block of NAND memory cells in the three-dimensional memory structure (Disclosing first programming a block of memory cells: Yang, col. 14:46) to programmed states (Disclosing a group of memory cells programmed to a plurality of data states: Yang, Figure 13A);
apply one or more shallow erase voltage pulses to the block (Disclosing applying a series of limited erase voltages to the memory cells: Yang, col. 14:51-53) while the block is in the programmed states (Disclosing applying the first partial erase scheme to a group of memory cells in a plurality of data states: Yang, Figure 13A);
add the block to a pool of shallow erased blocks (Disclosing the partially erased blocks added to a pool of partially erased blocks: Yang, col. 13:37-39) after applying the one or more shallow erase voltages (Disclosing the partially erased block is added to pool of partially erased blocks following the partial erase operation: Yang, col. 34-39);
select the block from the pool (Disclosing subsequently selecting a partially erased block from the partially erased pool: Yang, col. 15:6-9)
responsive to a determination that the block is to be programmed within an allotted time (Disclosing selecting the partially erased block from the pool of partially erased blocks in response to a determination the block is to be programmed: Yang, col. 15:6-9);
apply one or more full erase voltages to the block (Disclosing a conventional final erase voltage applied to fully erase the block: Yang, col. 15:9-11)
after the block has been selected from the pool (Disclosing applying the final erase voltage after selecting the partially erased block from the pool of partially erased blocks: Yang, col. 15:6-11)
with a final erase verify following each of the one or more full erase voltage pulses, each full erase voltage pulse having a magnitude of at least the full erase voltage (Disclosing a final erase phase using a conventional erase scheme: Yang, col.15:9-11); and
program the block (Disclosing programming the block subsequent to completing the full erase: Yang, col. 15:16)
within the allotted time after applying the one or more full erase voltage pulses (Disclosing completing the program operation within a pre-determined time period following final erase: Yang, col. 15:16-23).
Yang does not expressly disclose each of the shallow erase pulses having a magnitude of at least 5V below a nominal voltage. Clark, however, discloses a shallow erase phase wherein the pulses each have a magnitude of at least 5V below a nominal erase voltage (Disclosing a partial erase cycle of 2.2 volts compared to a standard erase cycle of 11.5 volts: Clark, ¶[0042]). Clark teaches greatly reducing the shallow erase voltage as compared to the nominal erase voltage and the duration of partial erase cycles reduces the erase rate (Clark, ¶[0039]).
Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the relatively large voltage differential of Clark with the shallow erase pool methodology of Yang, with a reasonable expectation of success. Each concept is a known invention in the careful erasing of NAND memory arrays, and combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 17, Yang discloses
(Currently Amended) The non-volatile storage system of claim 16, wherein
the one or more control circuits (Disclosing Controller 100 connected to memory structure 102: Yang, col. 6:41-42; See Also Yang, Figure 1) are configured to:
erase the memory cells in the block (Disclosing the partial erase scheme being applied to the group of memory cells: Yang, col. 13:34-37)
to a non-negative average threshold voltage (Disclosing a first erase verification voltage that is a positive voltage: Yang, col. 14:65-67)
as a result of applying the one or more shallow erase voltage pulses (Disclosing the shallow erase step may be considered complete with a non-negative median threshold voltage: Yang, col. 14:65-67; See Also Yang, Figure 13B); and
erase substantially all of the memory cells in the block (Disclosing a final erase step of the partially erased block: Yang, col. 15:9-11)
to a negative threshold voltage (Disclosing an erased threshold voltage range that is negative: Yang, Figure 13C)
as a result of applying the one or more full erase voltage pulses (Disclosing an erase verify step corresponding to an erased condition threshold voltage: Yang: col. 15:13-16).
Regarding Claim 18, Yang discloses the non-volatile storage system of claim 16, wherein applying the one or more shallow erase voltage pulses to the block while the block is in the programmed states includes the one or more control circuits:
applying a single shallow erase voltage pulse to the block of the memory cells (Disclosing using the singular “a lower erase voltage” during the partial erase step, in combination with the suggestion of using fewer erase pulses suggests the use of a singular erase pulse: Yang, col. 14:56-58) while the block is in the programmed states (Disclosing the partial erase scheme being applied to the group of memory cells: Yang, col. 13:34-37).
Regarding Claim 19, Yang discloses the non-volatile storage system of claim 16, wherein the one or more control circuits are configured to:
verify whether the block of the memory cells pass a shallow erase verify as a result of applying the one or more shallow erase voltage pulses (Disclosing testing the partial erase with a first erase verification voltage (ERV): Yang, col. 14:53-56),
the shallow erase verify tests for a positive reference voltage (Disclosing a first erase verification voltage that is a positive voltage: Yang, col. 14:65-67); and
the final erase verify tests for a negative reference voltage (Disclosing an erased threshold voltage range that is negative: Yang, Figure 13C).
Claim(s) 6 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 9,384,845 B2, to Niles Yang, et al. (hereafter Yang) and U.S. 2017/0090873 A1 to Lawrence T. Clark, et al. (hereafter Clark), further in light of U.S. 8,130,551 B2 to Ken Oowada, et al. (hereafter Oowada).
Regarding Claim 6, Yang discloses the apparatus of Claim 1, but does not disclose the further limitations of Claim 6. Oowada, however, discloses an apparatus as in Claim 1, wherein the one or more control circuits are further configured to:
step up a magnitude of the erase voltage pulses during the final erase by a step size that is significantly less than 5V (Disclosing a step-up between erase pulses of 0.5 or 1 volt: Oowada, col.10:65-11:4).
Oowada teaches the voltage step-up between pulses should be shallow to prevent over erasure of targeted memory cells (Oowada, col.11:10-12).
Therefore, it would have been obvious to one having ordinary skill in the art to combine the small erase voltage step-up of Oowada with the shallow/final erase methodology of Yang, with a reasonable expectation of success. Both inventions are known in the field of NAND memory array erasing operations, and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 20, Yang discloses the non-volatile storage system of claim 16 but does not expressly disclose the further limitations of claim 20. Oowada, however, discloses a non-volatile memory storage system wherein, wherein
the one or more control circuits (Teaching control circuitry 410 connected to memory array 300: Oowada, col. 5:25-35; See Also Figure 4) are configured to:
step up a magnitude of the full erase voltage pulses by a step size between erase loops (Teaching increasing the final erase voltages by a step size between erase loops: Oowada, col. 14:60-65; See Also Oowada, Figure 17); and
increase a magnitude of a first of the full erase voltage pulses (Teaching increasing the final erase voltages between the first phase of erase loops and the final phases of erase loops: Oowada, col. 14:60-65; See Also Oowada, Figure 17)
relative to a last of the shallow erase voltage pulses by more than the step size (Teaching the step size between the phase I erase voltage and the phase II erase voltage is greater than the step size between the phase I erase voltages: Oowada, col. 15:6-11; See Also Figure 17).
Oowada teaches this step increase in erase voltages allows erasing memory cells sufficiently deep without the need for additional verification testing at a deep negative voltage threshold. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to apply the stepped erase phases of Oowada to the shallow/final phased erase method of Yang with predictable results and a reasonable expectation of success.
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. 2023/0195328 A1 to Ching-Huang Lu, et al.: Teaching a first erase sub-operation to reduce the memory cell threshold voltage to a first threshold voltage, followed by a final erase operation.
U.S. 2020/0395087 A1 to Amiya Banerjee: Teaching a phase of soft-erase pulses to reduce the voltage threshold of a plurality of memory cells to a first intermediate level, followed by a final erase phase.
EP 1,752,989 A1 to Bovino Angelo, et al.: Disclosing a partial erase phase consisting of a single erase pulse.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/DOUGLAS KING/Primary Examiner, Art Unit 2824