DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 2, 9-10, and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/12/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 20160049421 A1; hereinafter Zhang).
Regarding claim 1, FIG. 3A of Zhang teaches a semiconductor structure (e.g. FIG. 3A), comprising: an alternating stack (120) of insulating layers (19) and electrically conductive layers (3a-3b, 33-34 ¶ [0057]); a memory opening (150) vertically extending through the alternating stack (120 ¶ [0019]); a memory opening fill structure (155) located in the memory opening (150) and comprising a memory film (13) and a vertical semiconductor channel (1 ¶ [0019]); and a backside semiconductor cap structure (102) having a top surface (top surface of 102) that is in contact with a bottom surface of the vertical semiconductor channel (bottom surface of 1 ¶ [0029]), wherein an entirety of the top surface of the backside semiconductor cap structure (top surface of 102) is located within a horizontal plane including a bottom surface of a bottommost insulating layer within the alternating stack (horizontal plane including bottom surface of bottommost 19, see FIG. 3A). The Examiner notes the term “contact” has been interpreted under broadest reasonable interpretation (BRI, MPEP § 2111.01) as meaning “physically contacts”, “electrically contacts”, “indirectly contacts”, or “directly contacts”.
Regarding claim 3, Zhang teaches the semiconductor structure of Claim 1, and FIG. 3A of Zhang further teaches wherein the top surface of the backside semiconductor cap structure (top surface of 102) is in contact with a bottom surface of the bottommost insulating layer within the alternating stack (bottom surface of bottommost 19).
Regarding claim 4, Zhang teaches the semiconductor structure of Claim 1, and FIG. 3A of Zhang further teaches wherein the top surface of the backside semiconductor cap structure (top surface of 102) is in contact with a planar horizontal surface of the vertical semiconductor channel (e.g. bottom surface of 1). The Examiner notes the term “contact” has been interpreted under broadest reasonable interpretation (BRI, MPEP § 2111.01) as meaning “physically contacts”, “electrically contacts”, “indirectly contacts”, or “directly contacts”.
Regarding claim 5, Zhang teaches the semiconductor structure of Claim 1, and FIG. 3A of Zhang further teaches further comprising a logic die (driver circuits of 100 ¶ [0033] “substrate 100 may include… driver circuits for a memory device”) bonded to a memory die (memory die comprising 120, 150) containing the alternating stack (120).
Regarding claim 13, Zhang teaches the semiconductor structure of Claim 1, and FIG. 3A of Zhang further teaches wherein: the vertical semiconductor channel (1) has a doping of a first conductivity type (e.g. p-type ¶ [0029]); and the backside semiconductor cap structure (102) has a doping of a second conductivity type that is an opposite of the first conductivity type (e.g. n-type ¶ [0029]).
Regarding claim 14, Zhang teaches the semiconductor structure of Claim 1, and FIG. 3A of Zhang further teaches wherein an entirety of an interface between the memory opening fill structure (155) and the backside semiconductor cap structure (102) is located within the horizontal plane (horizontal plane shared by bottom surface of bottommost 19 and top surface of 102).
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pachamuthu et al. (US 20160111434 A1; hereinafter Pachamuthu).
Regarding claim 1, FIG. 5L of Pachamuthu teaches a semiconductor structure (e.g. FIG. 5L), comprising: an alternating stack (120) of insulating layers (19) and electrically conductive layers (3 ¶ [0025]); a memory opening (81) vertically extending through the alternating stack (120 ¶ [0031]); a memory opening fill structure (1, 2, 7, 9, 11) located in the memory opening (81) and comprising a memory film (9) and a vertical semiconductor channel (1 ¶ [0027]-[0028]); and a backside semiconductor cap structure (511 ¶ [0039]) having a top surface (top surface of 511) that is in contact with a bottom surface of the vertical semiconductor channel (bottom surface of 1), wherein an entirety of the top surface of the backside semiconductor cap structure (top surface of 511) is located within a horizontal plane including a bottom surface of a bottommost insulating layer within the alternating stack (horizontal plane including bottom surface of bottommost insulating layer 19).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Baraskar et al. (US 20210375908 A1; hereinafter Baraskar).
Regarding claim 8, Zhang teaches the semiconductor structure of Claim 1.
Zhang does not teach further comprising a metal-semiconductor alloy structure contacting a bottom surface of the backside semiconductor cap structure.
FIG. 32B of Baraskar teaches a semiconductor structure (e.g. FIG. 32B), comprising: an alternating stack (132, 146, 232, 246) of insulating layers (132, 232 ¶ [0171], [0195]) and electrically conductive layers (146, 246 ¶ [0244], [0246]-[0247]); a memory opening (49) vertically extending through the alternating stack (132, 146, 232, 246 ¶ [0207]); a memory opening fill structure (55) located in the memory opening (49) and comprising a memory film (54) and a vertical semiconductor channel (60 ¶ [0209]); and a backside semiconductor cap structure (14) in contact with the vertical semiconductor channel (60 ¶ [0252]); and a metal-semiconductor alloy structure (18 ¶ [0239]-[0240]) contacting the backside semiconductor cap structure (14), wherein the backside semiconductor cap structure (14) is located between the vertical semiconductor channel (60) and the metal-semiconductor alloy structure (18).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure taught by Zhang with the source contact structure taught by Baraskar for the purpose of providing a higher quality semiconductor material (¶ [0275]), thus increasing the reliability of the device, and providing a highly conductive current path for the source select region.
Regarding claim 11, Zhang as modified teaches the semiconductor structure of Claim 8, and FIG. 32B of Baraskar further teaches further comprising a backside conductive layer (112) comprising at least one metallic material (¶ [0247]) and contacting a bottom surface of the metal-semiconductor alloy structure (e.g. surface of 18 facing 112).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Pachamuthu in view of Zhang.
Regarding claim 12, Pachamuthu teaches the semiconductor structure of Claim 1, and FIG. 5L of Pachamuthu further teaches wherein: the vertical semiconductor channel (1) comprises undoped or doped polycrystalline silicon (¶ [0023]); and the backside semiconductor cap structure (511) comprises undoped or doped polycrystalline silicon (¶ [0039]).
Pachamuthu does not explicitly teach wherein: the vertical semiconductor channel has a doping of a first conductivity type; and the backside semiconductor cap structure has a doping of the first conductivity type.
FIG. 3A of Zhang teaches a semiconductor structure (e.g. FIG. 3A) including a vertical semiconductor channel (1 ¶ [0029]); wherein the vertical semiconductor channel (1) has a doping of a first conductivity type (e.g. p-type ¶ [0029]).
Thus, Pachamuthu in view of Zhang teaches wherein: the vertical semiconductor channel (1 of Pachamuthu) has a doping of a first conductivity type (p-type as taught by Zhang); and the backside semiconductor cap structure (511 of Pachamuthu) has a doping of the first conductivity type (p-type as taught by Zhang since 511 of Pachamuthu is a channel extension).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure taught by Pachamuthu with the p-type channel taught by Zhang for the purpose of providing a channel with faster switching and lower on-state resistance.
Allowable Subject Matter
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 recites the semiconductor structure of Claim 1, wherein: the backside semiconductor cap structure comprises a contoured bottom surface; and each point on the contoured bottom surface is equidistant from a respective most proximal point on a bottom surface of the vertical semiconductor channel.
Zhang teaches the semiconductor structure of claim 1.
FIG. 4 of Yamabe (US 20220068949 A1; hereinafter Yamabe) teaches a semiconductor structure (e.g. FIG. 4) comprising a backside semiconductor cap structure (150 ¶ [0055], [0065]), wherein the backside semiconductor cap structure (150) comprises a contoured bottom surface.
However, the prior art fails to teach or reasonably suggest “each point on the contoured bottom surface is equidistant from a respective most proximal point on a bottom surface of the vertical semiconductor channel” together with all the limitations of claims 1 and 6 as claimed. Claim 7 contains allowable subject matter insofar as it depends upon and requires all the limitations of claims 1 and 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891