DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on February 02, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 6-15, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2015/0380335 A1 to Takematsu et al. (“Takematsu”) in view of JP 2004-172211 A to Hayashi et al. (“Hayashi”), and U.S. Patent Application Publication No. 2010/0096166 A1 to Fjelstad (“Fjelstad”)/U.S. Patent Application Publication No. 2017/0331371 A1 to Parto (“Parto”). As to claim 1, although Takematsu discloses a semiconductor package comprising: a substrate (4) forming a first surface and a second surface that opposes the first surface; a set of terminals (10) of the semiconductor package attached to the first surface of the substrate (4) and protruding from the first surface of the substrate (4); a gallium nitride die (6) attached to the first surface of the substrate (4); a substrate layer (9) physically contacting the gallium nitride die (6), the substrate layer (9) including at least one circuit layer disposed on an insulating substrate layer; and mold compound (11) covering portions of the substrate (4), the set of terminals (10), the gallium nitride die (6), and the substrate layer (9) (See Fig. 1, ¶ 0003, ¶ 0005, ¶ 0026, ¶ 0039, ¶ 0041, ¶ 0048) (Notes: the thin circuit board has a certain flexibility and Fjelstad discloses a flexible circuit (2016) to provide flexibility amongst other circuitry and device elements, where the at least one circuit layer (2028) disposed on an insulating substrate layer (2032) provide connections on surfaces thereof (See Fig. 20, Fig. 28, ¶ 0115-¶ 0124, ¶ 0133). Lastly, Parto discloses the gallium nitride die is known as a high performance die that is capable of high switch speed (See ¶ 0005, ¶ 0137)), Takematsu does not further disclose the set of terminals of the semiconductor package attached to the first surface of the substrate via a conductive adhesive; and a control die attached to a second surface of the substrate layer opposite the gallium nitride die. However, Hayashi does disclose the set of terminals (7) of the semiconductor package attached to the first surface of the substrate (4) via a conductive adhesive (9); and a control die (3) attached to a second surface of the substrate layer (10) opposite the die (1) (See Fig. 1, Fig. 2, Fig. 3, Abstract, ¶ 0002, ¶ 0006, ¶ 0007, ¶ 0008). In view of the teaching of Hayashi, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Takematsu to have the set of terminals of the semiconductor package attached to the first surface of the substrate via a conductive adhesive; and a control die attached to a second surface of the substrate layer opposite the gallium nitride die because the conductive adhesive provides electrical bonding and secures connection between the terminals and the substrate, where the control die provided on the second surface of the substrate with the opposite the gallium nitride die form an integrated power module having a short and compact connection to reduce inductance and the size of the power module (See ¶ 0006, ¶ 0007, ¶ 0008). As to claim 10, although Takematsu discloses a semiconductor package comprising: a substrate (4) forming a first surface and a second surface that opposes the first surface; a set of terminals (10) of the semiconductor package attached to the first surface of the substrate (4) and protruding from the first surface of the substrate (4); a first gallium nitride die (6) and a second gallium nitride die (6) attached to the first surface of the substrate (4); a substrate layer (9) on the first gallium nitride die (6) and the second gallium nitride die (6), the substrate layer (9) including at least one circuit layer disposed on a flexible insulating substrate layer; and mold compound (11) covering portions of the substrate (4), the set of terminals (10), the first gallium nitride die (6), the second gallium nitride die (6), and the substrate layer (9) (See Fig. 1, ¶ 0003, ¶ 0005, ¶ 0026, ¶ 0039, ¶ 0041, ¶ 0048) (Notes: the thin circuit board has a certain flexibility and Fjelstad discloses a flexible circuit (2016) to provide flexibility amongst other circuitry and device elements, where the at least one circuit layer (2028) disposed on an insulating substrate layer (2032) provide connections on surfaces thereof (See Fig. 20, Fig. 28, ¶ 0115-¶ 0124, ¶ 0133). Lastly, Parto discloses the gallium nitride die is known as a high performance die that is capable of high switch speed (See ¶ 0005, ¶ 0137)), Takematsu does not further disclose the set of terminals of the semiconductor package attached to the first surface of the substrate via a conductive adhesive; wherein a top surface of the substrate layer includes two sections at different planes in a cross-sectional view of the semiconductor package; and a control die attached to a second surface of the substrate layer. However, Hayashi does disclose the set of terminals (7) of the semiconductor package attached to the first surface of the substrate (4) via a conductive adhesive (9); and a control die (3) attached to a second surface of the substrate layer (10) (See Fig. 1, Fig. 2, Fig. 3, Abstract, ¶ 0002, ¶ 0006, ¶ 0007, ¶ 0008). Further, Fjelstad does disclose wherein a top surface of the substrate layer (2016) includes two sections at different planes in a cross-sectional view of the semiconductor package (See Fig. 20, Fig. 28, ¶ 0115-¶ 0124, ¶ 0133). In view of the teachings of Hayashi and Fjelstad, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Takematsu to have the set of terminals of the semiconductor package attached to the first surface of the substrate via a conductive adhesive; wherein a top surface of the substrate layer includes two sections at different planes in a cross-sectional view of the semiconductor package; and a control die attached to a second surface of the substrate layer because the conductive adhesive provides electrical bonding and secures connection between the terminals and the substrate, where the control die provided on the second surface of the substrate with the opposite the gallium nitride die form an integrated power module having a short and compact connection to reduce inductance and the size of the power module (See Hayashi ¶ 0006, ¶ 0007, ¶ 0008). Further, the substrate layer with two sections at different planes provides flexibility amongst other circuitry and device elements as desired (See Fjelstad ¶ 0133). As to claim 17, although Takematsu discloses a semiconductor package comprising: a substrate (4) forming a first surface and a second surface that opposes the first surface; a set of terminals (10) of the semiconductor package attached to the first surface of the substrate (4) and protruding from the first surface of the substrate (4); a gallium nitride die (6) attached to the first surface of the substrate (4); a substrate layer (9) physically contacting the gallium nitride die (6), the substrate layer (9) including at least one circuit layer disposed on an insulating substrate layer, wherein the at least one circuit layer electrically connects the gallium nitride die (6) to another gallium nitride die (6) in the semicontuor package; and mold compound (11) covering portions of the substrate (4), the set of terminals (10), the gallium nitride die (6), and the substrate layer (9) (See Fig. 1, ¶ 0003, ¶ 0005, ¶ 0026, ¶ 0039, ¶ 0041, ¶ 0048) (Notes: the thin circuit board has a certain flexibility and Fjelstad discloses a flexible circuit (2016) to provide flexibility amongst other circuitry and device elements, where the at least one circuit layer (2028) disposed on an insulating substrate layer (2032) provide connections on surfaces thereof (See Fig. 20, Fig. 28, ¶ 0115-¶ 0124, ¶ 0133). Lastly, Parto discloses the first and second gallium nitride dies are known as high performance dies that are electrically connected and capable of high switch speed (See ¶ 0005, ¶ 0074, ¶ 0137)), Takematsu does not further disclose the set of terminals of the semiconductor package attached to the first surface of the substrate via a conductive adhesive; and a control die attached to a second surface of the substrate layer opposite the gallium nitride die. However, Hayashi does disclose the set of terminals (7) of the semiconductor package attached to the first surface of the substrate (4) via a conductive adhesive (9); and a control die (3) attached to a second surface of the substrate layer (10) opposite the die (1) (See Fig. 1, Fig. 2, Fig. 3, Abstract, ¶ 0002, ¶ 0006, ¶ 0007, ¶ 0008). In view of the teaching of Hayashi, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Takematsu to have the set of terminals of the semiconductor package attached to the first surface of the substrate via a conductive adhesive; and a control die attached to a second surface of the substrate layer opposite the gallium nitride die because the conductive adhesive provides electrical bonding and secures connection between the terminals and the substrate, where the control die provided on the second surface of the substrate with the opposite the gallium nitride die form an integrated power module having a short and compact connection to reduce inductance and the size of the power module (See ¶ 0006, ¶ 0007, ¶ 0008). As to claims 2 and 11, Takematsu in view of Hayashi discloses further comprising one or more passive components (2) of a sensing circuit mounted on the second surface of the substrate layer (9/10) and electrically connected to the control die (3) (See Hayashi Fig. 1, Fig. 2, Fig. 3, ¶ 0002, ¶ 0006, ¶ 0007, ¶ 0008) (Notes: the sensing circuit includes active/passive elements integrated as a control signal. Essential elements forming the power module are integrated on the substrate layer known in prior art). As to claims 3 and 12, Takematsu in view of Hayashi further discloses wherein the substrate layer (9/10) includes alignment features (15) engaged with the set of terminals (10/7) protruding from the substrate (4) (See Takematsu Fig. 1 and Hayashi Fig. 3, ¶ 0008). As to claims 4 and 13, Takematsu in view of Hayashi further discloses wherein the set of terminals (10) protruding through the substrate layer (9/10) and the mold compound (11) to an external portion of the semiconductor package (See Takematsu Fig. 1 and Hayashi Fig .3). As to claims 6 and 15, Takematsu in view of Hayashi further discloses wherein the substrate (4) is a direct bonded copper substrate (4) including a ceramic base (1/4) and a copper layer (2, 3) on the ceramic base (1/4), the (first/second) gallium nitride die (6/1) attached to the copper layer (2, 3) (See Takematsu Fig. 1, ¶ 0026 and Hayashi Fig. 1, ¶ 0006). As to claim 7, Takematsu in view of Hayashi discloses further comprising a thermal interface material (5/9) between the gallium nitride die (6/1) and the first surface of the substrate (4) (See Takematsu Fig. 1, ¶ 0026 and Hayashi Fig. 1, ¶ 0006). As to claim 8, Takematsu in view of Hayashi discloses further comprising: a first set of solder bumps (8/12) forming electrical connections between the gallium nitride die (6/1) and the substrate layer (9/10) such that the gallium nitride die (6/1) is mounted on the first surface of the substrate layer (9/10) in a first flipchip arrangement (See Takematsu Fig. 1, ¶ 0026 and Hayashi Fig. 1, ¶ 0006). As to claim 9 and 14, Takematsu discloses further comprising a heat sink (cooling member) physically and thermally coupled to the second surface of the substrate (4), the second surface of the substrate opposing the first surface of the substrate (See Fig. 1, ¶ 0039). As to claim 19, Takematsu further discloses wherein a backside of the gallium nitride die (6) is attached to the first surface of the substrate (4) (See Fig. 1). As to claim 20, Takematsu in view of Hayashi further discloses wherein the backside of the gallium nitride die (6) is attached to the first surface of the substrate (4) via a thermal interface material (5/9) (See Takematsu Fig. 1, ¶ 0026 and Hayashi Fig. 1, ¶ 0006).
Claim(s) 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2015/0380335 A1 to Takematsu et al. (“Takematsu”), JP 2004-172211 A to Hayashi et al. (“Hayashi”), and U.S. Patent Application Publication No. 2010/0096166 A1 to Fjelstad (“Fjelstad”) as applied to claims 1 and 10 above, and further in view of U.S. Patent Application Publication No. 2005/0280138 A1 to Shrivastava et al. (“Shrivastava”). The teachings of Takematsu, Hayashi, and Fjelstad have been discussed above. As to claims 5 and 16, although Takematsu and Fjelstad disclose the substrate layer (9/2016) (See Takematsu and Fjelstad), Takematsu, Hayashi, and Fjelstad do not further disclose wherein the substrate layer is a flexible circuit layer/flexible insulating substrate layer which includes a bend radius under 25 millimeters. However, Shrivastava does disclose wherein the substrate layer is a flexible circuit layer/flexible insulating substrate layer (30) includes a bend radius under 25 millimeters (See Fig. 2, ¶ 0020). In view of the teaching of Shrivastava, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Takematsu and Fjelstad to have wherein the substrate layer is a flexible circuit layer/flexible insulating substrate layer which includes a bend radius under 25 millimeters as the bend radius is determined by the physical dimensions forming the substrate layer and may be adjusted and optimized in view of design requirements and constraints (See ¶ 0020).
Response to Arguments
Applicant's arguments filed on February 02, 2026 have been fully considered but they are not persuasive. Applicants argue “the result will be a bigger substrate to accommodate the direct connection (please see the bigger gap of the substrate 4 for the right-side terminal 10 of Fig.3). Such a modification would increase the size of the power module instead of reducing as the Examiner alleges…Second, having a longer external connection terminal 10…increases the inductance since inductance is a function of length and inductance generally increases with length instead of reducing it as the Examiner alleges...Third, modifying the terminal 10 to contact the substrate 4 would leave the device of Takematsu inoperable for its intended purposes…Modifying the terminals 10 to contact to the substrate 4 would leave no path for terminal 10 to be electrically connected to the semiconductor element 6 rending the device of Takematsu inoperable for its intended purposes…Fourth…when the sole focus of Takematsu is to handle heat from the device with an innovative resin.” This is not found persuasive because the modification is merely incorporating/adding the missing conductive adhesive from Hayashi. It is noted that the limitation “attached to the first surface of the substrate” does not require any direct contact/attachment in view of the recited “via a conductive adhesive”, where the conductive adhesive provides electrical bonding and secures connection. There is no modification to the terminal 10 or the substrate such that the size of the power module and the inductance would not be increased as argued. It is further noted that the annotated Fig. 3 of Takematsu in REMARKS filed on February 02, 2026 is not the combined teachings of Takematsu and Hayashi in the rejection above. As already stated, there is no modification to the terminal or the substrate. The combination is to incorporate the missing conductive adhesive from Hayashi into Takematsu such that the conductive adhesive is placed/inserted under the terminal 10 of Takamatsu rather than having a newly formed longer terminal by extending the substrate as annotated. Further, the limitation does not recite the terminal 10 to contact/physical touch the substrate 4. As discussed above, the limitation is directed to the attachment to the substrate via the conductive adhesive. Thus, having the conductive adhesive inserted under the terminal 10 meets the recited attachment. It is also noted that the opposite terminal 10 is attached to the substrate 4 and penetrating the printed circuit board 9. Lastly, as stated above, the sensing circuit includes active/passive elements is integrated as a control signal. Essential elements forming the power module are integrated on the substrate layer and known in prior art. The power module of Parto also comprises several essential passive components. Also, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815