DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 12, 2026 has been entered.
Response to Amendment
The amendment filed February 12, 2026 has been entered. Claims 1-6 and 9-19 remain pending in this application. Claims 7-8 drawn to non-elected invention have been withdrawn. Claims 1, 6, 9-11, 15, and 18-19 have been amended. No claims have been added. No new matter has been added.
Applicant’s amendments to the Specification, Drawings, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Final Office Action mailed November 14, 2025.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 6 objected to because of the following informalities:
Claim 6 improperly marked (Previously Presented) when it has been amended.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 6, 9, 13-16, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0099254 A1 to Chan Park, et al. (hereafter Park) in view of US 5,592,001 to Masamichi Asano (hereafter Asano) and further in view of US 2020/0303382 A1 to Akira Takashima, et al. (hereafter Takashima) and US 4,984,199 to Masahiro Yoneda, et al. (hereafter Yoneda).
Regarding Independent Claim 1, Park discloses a semiconductor memory device, comprising:
a plurality of first holes
arranged in a first direction to be spaced apart from each other by a first distance (A plurality of first holes, arranged in first direction and separated from each other by a distance: Park, Figure 14A),
wherein each of the plurality of first holes includes first and second memory cell strings (Disclosing two sets of cell strings within a single hole: Park, ¶[0079]), and
wherein each of the plurality of first memory cell strings include a plurality of first memory cells (Disclosing cell architecture, wherein a string of memory cells include a plurality of memory cells: Park, ¶[0073]), and
wherein each of the plurality of second memory cell strings include a plurality of second memory cells (Disclosing cell architecture, wherein a string of memory cells include a plurality of memory cells: Park, ¶[0073]);
a first drain select line
coupled to the plurality of first memory cell strings (Disclosing drain and/or select transistors, optionally at either end of the memory string: Park, ¶[0073]),
among the plurality of first and second memory cell strings,
the first memory cell string separated from the second memory cell string in each of the plurality of first holes; and a second drain select line coupled to the plurality of second memory cell strings (Teaching the drain select transistor may be shared between memory strings, as in Park, Figure 10A, or be individually provided for separate strings: Park, ¶[0074]).
wherein the first and second memory cell strings are connected to a common bitline (Teaching bit line contacts may be offset so that channels of memory holes connect to different bit lines, suggesting bit line contacts may not be so offset and therefore connect to common bit lines: Park, ¶[0078]).
Park implies memory strings sharing memory holes may be connected to a common bit line. The designation of first and second bit lines as even or odd in inherent. Other prior art, however, explicitly teaches multiple strings of memory cells sharing a memory hole where the multiple strings are connected to a common bit line (For instance, showing paired memory strings in a common sharing a common bit line: Takashima, Figure 1 and ¶[0049]; See also, pairs of memory cell strings sharing a memory hold and common bit line: Yoneda, Figure 8 and col.2:34-37). Yoneda teaches this configuration halves the number of contact holes required for a particular number of storage bits (Yoneda, col.2:6-13). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the common bit line of Takashima and Yoneda with the paired memory strings of Park, with a reasonable expectation of success. Both inventions are well known in the field of multiple memory strings per memory hole architecture and the combination of known inventions with predictable results is obvious and not patentable.
Park does not disclose identical data being stored in the first and second memory cells coupled to a selected word line, among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings. Asano, however, discloses a memory array wherein:
identical data is stored in the first and second memory cells (Storing identical data in paired memory cells: Asano, col.4:14-17)
coupled to a selected word line (First and second memory cells sharing a single word line: Asano, Figure 10), among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings (Illustrating the paired memory cells being located on separate strings: Asano, Figure 10).
Asano teaches this configuration improves the reliability of data storage (Asano, col.4:14-17). Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the paired programming operation of Asano with the divided memory strings of Park, with a reasonable expectation of success. Both inventions are well known methods of increasing reliable storage of memory cells in NAND architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 4, Park discloses the semiconductor memory device according to claim 1, wherein
each of the first and second memory cells is implemented as a single-level cell (SLC) in which one bit of data is stored (Disclosing either MLC or SLC storage in memory cells: Park, ¶[0069]).
Regarding Amended Independent Claim 6, Park discloses a semiconductor memory device, comprising:
a plurality of memory blocks (Disclosing multiple blocks of memory: Park, ¶[0003]),
each including a plurality of first holes
arranged in a first direction to be spaced apart from each other by a first distance (A plurality of first holes, arranged in first direction and separated from each other by a distance: Park, Figure 14A),
wherein each of the plurality of first holes includes a first and a second memory cell strings (Disclosing two sets of cell strings within a single hole: Park, ¶[0079]), and
wherein each of the plurality of first memory cell strings include a plurality of first memory cells
wherein each of the plurality of second memory cell strings include a plurality of second memory cells (Disclosing cell architecture, wherein a string of memory cells include a plurality of memory cells: Park, ¶[0073]);
a peripheral circuit
configured to perform a program operation or a read operation on a memory block selected from among the plurality of memory blocks (Disclosing a peripheral controller 100: Park, Figure 1); and
a control logic
configured to control an operation of the peripheral circuit, wherein
the first memory cell strings are coupled to a first drain select line (Disclosing drain and/or select transistors, optionally at either end of the memory string: Park, ¶[0073]),
among the plurality of first and second memory cell strings,
the first memory cell string separated from the second memory cell string in each of the plurality of first holes (Disclosing separate memory strings configured within the same hole: Park, ¶[0079]),
wherein the second memory cell strings are coupled to a second drain select line (Disclosing drain and/or select transistors, optionally at either end of the memory string: Park, ¶[0073]; Further, teaching the drain select transistor may be shared between memory strings, as in Park, Figure 10A, or be individually provided for separate strings: Park, ¶[0074]),
wherein the first and second memory cell strings are connected to a common bit line (Teaching bit line contacts may be offset so that channels of memory holes connect to different bit lines, suggesting bit line contacts may not be so offset and therefore connect to common bit lines: Park, ¶[0078]).
Park implies memory strings sharing memory holes may be connected to a common bit line. The designation of first and second bit lines as even or odd in inherent. Other prior art, however, explicitly teaches multiple strings of memory cells sharing a memory hole where the multiple strings are connected to a common bit line (For instance, showing paired memory strings in a common sharing a common bit line: Takashima, Figure 1 and ¶[0049]; See also, pairs of memory cell strings sharing a memory hold and common bit line: Yoneda, Figure 8 and col.2:34-37). Yoneda teaches this configuration halves the number of contact holes required for a particular number of storage bits (Yoneda, col.2:6-13). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the common bit line of Takashima and Yoneda with the paired memory strings of Park, with a reasonable expectation of success. Both inventions are well known in the field of multiple memory strings per memory hole architecture and the combination of known inventions with predictable results is obvious and not patentable.
Park does not disclose identical data being stored in the first and second memory cells coupled to a selected word line, among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings. Asano, however, discloses a memory array wherein:
identical data is stored in the first and second memory cells (Storing identical data in paired memory cells: Asano, col.4:14-17)
coupled to a selected word line (First and second memory cells sharing a single word line: Asano, Figure 10), among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings (Illustrating the paired memory cells being located on separate strings: Asano, Figure 10).
Asano teaches this configuration improves the reliability of data storage (Asano, col.4:14-17). Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the paired programming operation of Asano with the divided memory strings of Park, with a reasonable expectation of success. Both inventions are well known methods of increasing reliable storage of memory cells in NAND architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Independent Claim 9, Park discloses a semiconductor memory device, comprising:
a plurality of first holes
arranged in a first direction to be spaced apart from each other by a first distance (A plurality of first holes, arranged in first direction and separated from each other by a distance: Park, Figure 14A); and
a plurality of second holes arranged in the first direction to be spaced apart from each other by the first distance (A plurality of first holes, arranged in first direction and separated from each other by a distance: Park, Figure 14A), wherein
the plurality of second holes are arranged to be spaced apart from the plurality of first holes in a second direction that is perpendicular to the first direction (The second holes to be spaced apart from the first holes perpendicularly to the first direction: Park, Figure 14A) and
are arranged to be offset from the plurality of first holes in the first direction by a third distance (The second set of holes offset from the first holes: Park, Figure 14A),
wherein
each of the plurality of first holes is separated into first and second memory cell strings (Disclosing a first set of holes separated into first and second memory strings: Park, Figure 24B and Figure 25),
the first memory cell strings are coupled to a first drain select line,
the second memory cell strings are coupled to a second drain select line (The first and second memory strings controlled independently by select transistors: Park, ¶[0094]), and
wherein
each of the plurality of second holes is separated into third and fourth memory cell strings (Disclosing a first set of holes separated into first and second memory strings: Park, Figure 24B and Figure 25),
the third memory cell strings are coupled to the second drain select line (The memory string word and select lines shown as located between the trenches, i.e. connecting second and third memory strings: Park, Figure 22B; See annotated image below),
the fourth memory cell strings are coupled to a third drain select line (The memory strings controlled independently by select transistors: Park, ¶[0094]), and
wherein,
during an operation performed on the first and second memory cell strings,
the first drain select line, the second drain select line, and the odd-numbered bit lines are activated (Disclosing selecting memory strings through selective activation of bitlines and select transistors: Park, ¶[0094]), and
wherein,
during an operation performed on the third and fourth memory cell strings,
the second drain select line, the third drain select line, and the even-numbered bit lines are activated (Disclosing selecting memory strings through selective activation of bitlines and select transistors: Park, ¶[0094]).
wherein the first and second memory cell strings are connected to a first bit line (Teaching bit line contacts may be offset so that channels of memory holes connect to different bit lines, suggesting bit line contacts may not be so offset and therefore connect to common bit lines: Park, ¶[0078]),
wherein the third and fourth memory cell strings are connected to a second bit line (Teaching bit line contacts may be offset so that channels of memory holes connect to different bit lines, suggesting bit line contacts may not be so offset and therefore connect to common bit lines: Park, ¶[0078]).
Park implies memory strings sharing memory holes may be connected to a common bit line. The designation of first and second bit lines as even or odd in inherent. Other prior art, however, explicitly teaches multiple strings of memory cells sharing a memory hole where the multiple strings are connected to a common bit line (For instance, showing paired memory strings in a common sharing a common bit line: Takashima, Figure 1 and ¶[0049]; See also, pairs of memory cell strings sharing a memory hold and common bit line: Yoneda, Figure 8 and col.2:34-37). Yoneda teaches this configuration halves the number of contact holes required for a particular number of storage bits (Yoneda, col.2:6-13). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the common bit line of Takashima and Yoneda with the paired memory strings of Park, with a reasonable expectation of success. Both inventions are well known in the field of multiple memory strings per memory hole architecture and the combination of known inventions with predictable results is obvious and not patentable.
Park does not disclose identical data being stored in the first and second memory cells coupled to a selected word line, among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings. Asano, however, discloses a memory array wherein:
identical data is stored in the first and second memory cells (Storing identical data in paired memory cells: Asano, col.4:14-17)
coupled to a selected word line (First and second memory cells sharing a single word line: Asano, Figure 10), among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings (Illustrating the paired memory cells being located on separate strings: Asano, Figure 10).
Asano teaches this configuration improves the reliability of data storage (Asano, col.4:14-17). Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the paired programming operation of Asano with the divided memory strings of Park, with a reasonable expectation of success. Both inventions are well known methods of increasing reliable storage of memory cells in NAND architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 13, Park discloses the semiconductor memory device according to claim 9, wherein: as the first drain select line and the second drain select line are activated, the first, second, and third memory cell strings are activated, and as the odd-numbered bit lines are activated, the operation is performed on the first and second memory cell strings, among the first, second, and third memory cell strings. (Selecting particular memory cell lines through activation of a combination of bit lines and select drain lines is a common operation in three-dimensional memory cell arrays: Park, Figure 5; See Also, Yoneda, Figure 7)
Functionally, the limitations of this claim amount to selecting a specific memory string by isolating it via a combination of bit line and drain line activation. The only departure from common practice in this instance being that two memory strings share a single memory hole instead of separate memory holes. The use of a single memory hole to enclose two memory strings is disclosed in Park (Disclosing a first set of holes separated into first and second memory strings: Park, Figure 24B and Figure 25). It would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the paired memory string architecture of Park with the well-known string isolation structure of Park and Yoneda, with a reasonable expectation of success. Both inventions are well known in the field of three-dimensional memory architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 14, Park discloses the semiconductor memory device according to claim 9, wherein:
as the second drain select line and the third drain select line are activated, the second, third, and fourth memory cell strings are activated, and as the even-numbered bit lines are activated, the operation is performed on the third and fourth memory cell strings, among the second, third, and fourth memory cell strings. (Selecting particular memory cell lines through activation of a combination of bit lines and select drain lines is a common operation in three-dimensional memory cell arrays: Park, Figure 5; See Also, Yoneda, Figure 7).
Functionally, the limitations of this claim amount to selecting a specific memory string by isolating it via a combination of bit line and drain line activation. The only departure from common practice in this instance being that two memory strings share a single memory hole instead of separate memory holes. The use of a single memory hole to enclose two memory strings is disclosed in Park (Disclosing a first set of holes separated into first and second memory strings: Park, Figure 24B and Figure 25). It would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the paired memory string architecture of Park with the well-known string isolation structure of Park and Yoneda, with a reasonable expectation of success. Both inventions are well known in the field of three-dimensional memory architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Independent Claim 15, Park discloses a semiconductor memory device, comprising:
a plurality of first holes
arranged in a first direction to be spaced apart from each other by a first distance (A plurality of first holes, arranged in first direction and separated from each other by a distance: Park, Figure 14A),
wherein each of the plurality of first holes includes first and second memory cell strings (Disclosing two sets of cell strings within a single hole: Park, ¶[0079]); and
a plurality of second holes
that are offset in relation to the plurality of first holes (The second set of holes offset from the first holes: Park, Figure 14A),
wherein each of the plurality of second holes includes third and fourth memory cell strings (Showing a series of paired memory cell strings: Park, Figure 25),
wherein an operation is performed on different memory cell strings based on which drain select lines and bit lines are activated (Selecting individual memory cell strings based on a combination of drain select lines and bit lines: Park, ¶[0094]).
Wherein the two memory cell strings separated from a single hole are connected to a common bit line (Teaching bit line contacts may be offset so that channels of memory holes connect to different bit lines, suggesting bit line contacts may not be so offset and therefore connect to common bit lines: Park, ¶[0078]).
Park implies memory strings sharing memory holes may be connected to a common bit line. The designation of first and second bit lines as even or odd in inherent. Other prior art, however, explicitly teaches multiple strings of memory cells sharing a memory hole where the multiple strings are connected to a common bit line (For instance, showing paired memory strings in a common sharing a common bit line: Takashima, Figure 1 and ¶[0049]; See also, pairs of memory cell strings sharing a memory hold and common bit line: Yoneda, Figure 8 and col.2:34-37). Yoneda teaches this configuration halves the number of contact holes required for a particular number of storage bits (Yoneda, col.2:6-13). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the common bit line of Takashima and Yoneda with the paired memory strings of Park, with a reasonable expectation of success. Both inventions are well known in the field of multiple memory strings per memory hole architecture and the combination of known inventions with predictable results is obvious and not patentable.
Park does not disclose identical data being stored in the first and second memory cells coupled to a selected word line, among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings. Asano, however, discloses a memory array wherein:
identical data is stored in the first and second memory cells (Storing identical data in paired memory cells: Asano, col.4:14-17)
coupled to a selected word line (First and second memory cells sharing a single word line: Asano, Figure 10), among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings (Illustrating the paired memory cells being located on separate strings: Asano, Figure 10).
Asano teaches this configuration improves the reliability of data storage (Asano, col.4:14-17). Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the paired programming operation of Asano with the divided memory strings of Park, with a reasonable expectation of success. Both inventions are well known methods of increasing reliable storage of memory cells in NAND architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 16, Park discloses the semiconductor memory device according to claim 15, wherein
the first memory cell strings are coupled to a first drain select line,
the second memory cell strings are coupled to a second drain select line (The first and second memory strings controlled independently by select transistors: Park, ¶[0094]), and
the first and second memory cell strings
are coupled to odd-numbered bit lines (The two strings of cells connected to a same bit line: Park, Figure 26A and ¶[0094]),
wherein the third memory cell strings are coupled to the second drain select line (The memory string word and select lines shown as located between the trenches, i.e. connecting second and third memory strings: Park, Figure 22B; See annotated image above),
the fourth memory cell strings are coupled to a third drain select line (The memory strings controlled independently by select transistors: Park, ¶[0094]), and
wherein,
during an operation performed on the first and second memory cell strings,
the first drain select line, the second drain select line, and the odd-numbered bit lines are activated (Disclosing selecting memory strings through selective activation of bitlines and select transistors: Park, ¶[0094]), and
wherein,
during an operation on the third and fourth memory cell strings,
the second drain select line, the third drain select line, and the even-numbered bit lines are activated (Disclosing selecting memory strings through selective activation of bitlines and select transistors: Park, ¶[0094]).
Park implies memory strings sharing memory holes may be connected to a common bit line. The designation of first and second bit lines as even or odd in inherent. Other prior art, however, explicitly teaches multiple strings of memory cells sharing a memory hole where the multiple strings are connected to a common bit line (For instance, showing paired memory strings in a common sharing a common bitline: Takashima, Figure 1 and ¶[0049]; See also, pairs of memory cell strings sharing a memory hold and common bit line: Yoneda, Figure 8 and col.2:34-37). Yoneda teaches this configuration halves the number of contact holes required for a particular number of storage bits (Yoneda, col.2:6-13). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the common bit line of Takashima and Yoneda with the paired memory strings of Park, with a reasonable expectation of success. Both inventions are well known in the field of multiple memory strings per memory hole architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 18, Park discloses the semiconductor memory device according to claim 16, wherein:
as the first drain select line and the second drain select line are activated,
the first, second, and third memory cell strings are activated (Disclosing selecting memory strings through selective activation of bitlines and select transistors: Park, ¶[0094]), and
as the odd-numbered bit lines are activated,
the operation is performed on the first and second memory cell strings,
among the first, second, and third memory cell strings (The two strings of cells connected to a same bit line: Park, Figure 26A and ¶[0094]; See annotated figure above).
Regarding Claim 19, Park discloses the semiconductor memory device according to claim 16, wherein:
as the second drain select line and the third drain select line are activated,
the second, third, and fourth memory cell strings are activated (Disclosing selecting memory strings through selective activation of bitlines and select transistors: Park, ¶[0094]), and
as the even-numbered bit lines are activated,
the operation is performed on the third and fourth memory cell strings,
among the second, third, and fourth memory cell strings (The two strings of cells connected to a same bit line: Park, Figure 26A and ¶[0094]; The designation of a first bit line as odd and second bit line as even is inherent in sequential alternating bit lines connecting a first row of holes and a second row of holes; See annotated figure above).
Park implies memory strings sharing memory holes may be connected to a common bit line. The designation of first and second bit lines as even or odd in inherent. Other prior art, however, explicitly teaches multiple strings of memory cells sharing a memory hole where the multiple strings are connected to a common bit line (For instance, showing paired memory strings in a common sharing a common bitline: Takashima, Figure 1 and ¶[0049]; See also, pairs of memory cell strings sharing a memory hold and common bit line: Yoneda, Figure 8 and col.2:34-37). Yoneda teaches this configuration halves the number of contact holes required for a particular number of storage bits (Yoneda, col.2:6-13). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the common bit line of Takashima and Yoneda with the paired memory strings of Park, with a reasonable expectation of success. Both inventions are well known in the field of multiple memory strings per memory hole architecture and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0099254 A1 to Chan Park, et al. (hereafter Park), US 5,592,001 to Masamichi Asano (hereafter Asano), US 2020/0303382 A1 to Akira Takashima, et al. (hereafter Takashima), and US 4,984,199 to Masahiro Yoneda, et al. (hereafter Yoneda) in view of US 2020/0183618 A1 to Sung-Min Joe (hereafter Joe).
Regarding Claim 2, Park discloses the semiconductor memory device according to Claim 1, but fails to disclose the further limitations of Claim 2. Joe, however, discloses a memory array as in Claim 1, wherein,
during a program operation (Disclosing a simultaneous programming operation: Joe, ¶[0072])
performed on the first and second memory cells (Programming on first and second memory cells: Joe, ¶¶[0073-0074]),
identical data is stored in the first and second memory cells (Storing identical data: Joe, ¶[0077])
by simultaneously activating the first and second drain select lines (Simultaneously activating the string select transistor during the programming operation: Joe, ¶[0075]).
Joe teaches this method of simultaneous programming creates a dispersion of voltage thresholds having a wider interval between data (Joe, ¶¶[0071-0072]).
Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the simultaneous programming operation of Joe with the divided memory strings of Park with a reasonable expectation of success. Both inventions are known techniques for ensuring reliable programming of paired memory cells and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 3, Park discloses the semiconductor memory device according to Claim 1, but fails to disclose the further limitations of Claim 3. Joe, however, discloses a memory device as in Claim 1, wherein,
during a read operation
performed on the first and second memory cells, (Performing a read operation on memory cells: Joe, ¶[0043])
identical data is read from the first and second memory cells (Disclosing programming identical data into multiple cells simultaneously: Joe, ¶[0072])
by simultaneously activating the first and second drain select lines (Multiple cells may be read simultaneously through activation of appropriate select lines: Joe, ¶[0043]; See Also, Joe, Figure 7).
Joe teaches this arrangement allows multiple data from a plurality of memory strings to be provided to the page buffer simultaneously (Joe, ¶[0044]).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the simultaneous read operation of Joe with the divided memory string of Park, with a reasonable expectation of success. Both inventions are known techniques for ensuring reliable data reads of memory cells in an array and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 5, 10-12, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0099254 A1 to Chan Park, et al. (hereafter Park), US 5,592,001 to Masamichi Asano (hereafter Asano), US 2020/0303382 A1 to Akira Takashima, et al. (hereafter Takashima), and US 4,984,199 to Masahiro Yoneda, et al. (hereafter Yoneda) in view of US 7,692,970 to Ki-Tae Park, et al. (hereafter Ki-Tae Park).
Regarding Amended Claim 5 and the substantially similar limitations of Claim 12, Park discloses the semiconductor memory device wherein different pieces of data are stored in the first and second memory cells (Programming different bits of data in adjacent memory cells: Park, ¶[0064]), and Asano discloses the semiconductor memory device wherein identical data is stored in the first and second memory cells (Simultaneously programming identical data in different memory cells: Asano, col.4:14-17). Neither Park nor Asano disclose modifying these operations when the number of program-erase operations performed on the semiconductor memory device is more or less than a preset reference value.
Ki-Tae Park, however, discloses a semiconductor memory device according to claim 1, wherein, when the number of program-erase operations performed on the semiconductor memory device is less than a preset reference value (Adjusting the programming operation depending on the number of program-erase cycles: Ki-Tae Park, col.4:29-33), the device programs memory cells in a first operation and when the number of program-erase operations is equal to or greater than the preset reference value (Adjusting the programming operation depending on the number of program-erase cycles: Ki-Tae Park, col.4:29-33), it programs memory cells in a second operation. Ki-Tae Park teaches the varying the programming operation allows the memory device to compensate for the detrapping based changes in the threshold voltage (Ki-Tae Park, col.4:36-40).
Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of the application, to combine the program-erase cycle tracking logic of Ki-Tae Park to the divided memory cell management system of Park and Asano, with a reasonable expectation of success. All inventions are known variations on increasing the reliability of programming data in memory cell arrays, and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 10 and the substantially similar limitations of Claim 11, Park discloses the semiconductor memory device according to claim 9, wherein a programming operation is performed among memory cells included in the first and second memory cell strings coupled to a selected word line (First and second cells on separate strings connected to a selected word line: Park, Figure 25). Park fails to disclose that this programming operation comprises programming identical data in the first and second memory cells.
Asano, on the other hand, discloses a memory array wherein identical data is stored in the first and second memory cells coupled to a selected word line (Storing identical data in paired memory cells: Asano, col.4:14-17), among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings (Illustrating the paired memory cells being located on separate strings: Asano, Figure 10).
Neither Park nor Asano expressly discloses that the determination to program identical data into the first and second memory cells should be based on the quality of those cells. Ki-Tae Park, however, discloses a programming operation based on a quality of the first and second memory cells (Adjusting the programming operation depending on the number of program-erase cycles: Ki-Tae Park, col.4:29-33; See Also, Teaching the quality of the memory cells is mostly determined by the number of program-erase cycles the memory block has undergone: Ki-Tae Park, col.2:1-7). Ki-Tae Park teaches the varying the programming operation allows the memory device to compensate for the detrapping based changes in the threshold voltage (Ki-Tae Park, col.4:36-40).
Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of the application, to combine the program-erase cycle tracking logic of Ki-Tae Park to the divided memory cell management system of Park and Asano, with a reasonable expectation of success. All inventions are known variations on increasing the reliability of programming data in memory cell arrays, and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 17, Park and Asano disclose the semiconductor memory device according to claim 16, wherein a programming operation is performed among memory cells included in the first and second memory cells coupled to a selected word line (First and second cells on separate strings connected to a selected word line: Park, Figure 25). Park further discloses programming third and fourth memory cells coupled to a selected word line (Third and fourth cells on separate strings connected to a selected word line: Park, Figure 25). Park fails to disclose that this programming operation comprises programming identical data in pairs of memory cells.
Neither Park nor Asano expressly discloses that the determination to program identical data into the first and second memory cells should be based on the quality of those cells. Ki-Tae Park, however, discloses a programming operation based on a quality of the first and second memory cells (Adjusting the programming operation depending on the number of program-erase cycles: Ki-Tae Park, col.4:29-33; See Also, Teaching the quality of the memory cells is mostly determined by the number of program-erase cycles the memory block has undergone: Ki-Tae Park, col.2:1-7). Ki-Tae Park teaches the varying the programming operation allows the memory device to compensate for the detrapping based changes in the threshold voltage (Ki-Tae Park, col.4:36-40).
Therefore, it would have been obvious to one having ordinary skill in the art, prior to the effective filing date of the application, to combine the program-erase cycle tracking logic of Ki-Tae Park to the divided memory cell management system of Park and Asano, with a reasonable expectation of success. All inventions are known variations on increasing the reliability of programming data in memory cell arrays, and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,950,627 to Tatsuya Hinoue, et al.: Teaching a pair of memory strings formed in a single hole be removing material during production, where select transistors lay between holes.
US 10,811,105 to Takuya Futatsuyama, et al.: Teaching a memory cell with multiple word lines connected to the cell.
US 2020/0303382 to Akira Takashima, et al.: Teaching a divided hole comprising two memory strings, where select transistors lay between holes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 03/06/2026