DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US Pub. 2024/0099015 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In re claim 1, Lee et al. shows (fig. 3) a semiconductor memory device, comprising: a stack disposed on a substrate, wherein the stack comprises electrodes (121) and cell insulating layers (110) that are alternately stacked on top of each other; and vertical structures (130) that penetrate the stack, wherein each of the vertical structures comprises: a vertical channel pattern (134) that penetrates the stack; and a data storage structure (120) disposed between the electrodes and the vertical channel pattern, wherein the data storage structure comprises first ferroelectric patterns (123) that are respectively disposed on side surfaces of the electrodes, and first conductive patterns (122) that are disposed between the first ferroelectric patterns and the vertical channel pattern, and the first ferroelectric patterns (123) and the first conductive patterns (122) are spaced apart from each other in a direction perpendicular to a top surface of the substrate with the cell insulating layers (110) interposed therebetween.
In re claim 7, Lee et al. shows (fig. 3) the first ferroelectric patterns (123) are in contact with the side surfaces of the electrodes.
In re claim 8, Lee et al. shows (fig. 3) wherein a thickness of each of the first ferroelectric patterns (123) in a direction parallel to the top surface of the substrate is less than a thickness of the vertical channel pattern (134).
In re claim 9, Lee et al. shows (fig. 3) wherein the electrodes (123) are recessed from side surfaces of the cell insulating layers (110) and the vertical channel pattern (134), and recess regions are defined (at S1, S2) by side surfaces of the cell insulating layers and the vertical channel pattern, wherein the first ferroelectric patterns (123) and the first conductive patterns (122) are disposed in the recess regions.
In re claim 10, Lee et al. shows (fig. 3) wherein each of the first conductive patterns (122) is in an electrically-floated state (since the first conductive patterns are not connected electrically to any other components).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being obvious over Lee et al. (US Pub. 2024/0099015 A1) in view of Yoon et al. (US Pub. 2024/0040794 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
In re claim 19, Lee et al. shows (figs. 3, 18) an electronic system, comprising:
a main substrate (1; fig.18); a semiconductor memory device (2; fig.18) disposed on the main substrate; and the cell insulating layers (110) interposed therebetween. Lee shows all of the elements of the claims except a controller disposed on the main substrate and electrically connected to the semiconductor memory device. A controller is well-known in the art for use in a computer memory system to operate the device. However, Yoon et al. shows (figs. 1-2) a system comprising a semiconductor memory device (Memory Cell Array 110) electrically connected to a controller (160; [0035]) to transmit commands or data to the memory. This configuration helps to operate the memory device. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the device of Lee by using a controller as taught by Yoon to transmit commands and/or data ultimately operating the device.
Allowable Subject Matter
Claims 2-6 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-18 are allowed.
The following is an examiner’s statement of reasons for allowance:
In re claim 11, the prior art references, alone or in combination, do not show a semiconductor memory device, comprising: a stack disposed on a substrate, wherein the stack comprises electrodes and cell insulating layers that are alternately stacked on top of each other; a vertical channel pattern that penetrates the stack; and a data storage structure disposed between the electrodes and the vertical channel pattern, wherein the data storage structure comprises: first ferroelectric patterns disposed on side surfaces of the electrodes; first conductive patterns disposed between the first ferroelectric patterns and the vertical channel pattern; second ferroelectric patterns disposed between the first conductive patterns and the vertical channel pattern; second conductive patterns disposed between the second ferroelectric patterns and the vertical channel pattern; and a third ferroelectric pattern disposed between the second conductive patterns and the vertical channel pattern, wherein the third ferroelectric pattern extends along a side surface of the vertical semiconductor layer and is connected in common to the second conductive patterns.
The closest prior references include Lee (US Pub. 2024/0099015 A1), Yoon (US Pub. 2024/0040794 A1), Fujimura (US Pub. 2023/0345727 A1), Bae (US Pub. 2023/0180481 A1), Heo (KR-20240004061-A), Lee (KR-20190123163-A), and (KR-102817641-B1). The references disclose various elements of claims including the electrodes, cell insulating patterns, vertical channel patterns, and parts of the data storage structures. However, none of the references disclose second ferroelectric patterns disposed between the first conductive patterns and the vertical channel pattern; second conductive patterns disposed between the second ferroelectric patterns and the vertical channel pattern; and a third ferroelectric pattern disposed between the second conductive patterns and the vertical channel pattern, wherein the third ferroelectric pattern extends along a side surface of the vertical semiconductor layer and is connected in common to the second conductive patterns.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fujimura (US Pub. 2023/0345727 A1), Bae (US Pub. 2023/0180481 A1), Heo (KR-20240004061-A), Lee (KR-20190123163-A), and (KR-102817641-B1) also disclose various elements of the claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2815