Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to Applicant’s claim to priority and benefit of U.S. Provisional Patent Application No. 63/459,597 filed on April 14, 2023.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed January 21, 2026. Claims 1-2, 5-6, 9, 13-14, 16, and 18-20 are amended. The Examiner notes that claims 1-20 are examined.
Specification
The substitute specification filed January 21, 2026 is acceptable and has been entered. All objections to the specification have been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie-712 (US 2023/0040712 A1) in view of Frougier (US 10,192,867 B1).
With respect to claim 1, Xie-712 teaches:
A method comprising:
growing a first epitaxy layer (Fig. 7, source/drain region 710) at a first side (left) and a second side (right) of a stack of a gate and a channel (see annotated Fig. 7 below of channel and gate stack at stage before gate stack has dummy gates replaced with gates of the finished construction) formed over a surface and a substrate (top surface of substrate 110), the surface of the substrate being parallel to a plane;
applying a sacrificial layer (sacrificial spacer layer 801) on the first epitaxy layer (710) (Fig. 8);
growing a second epitaxy layer (upper device S/D regions 910) on the sacrificial layer (810) (Fig. 9);
removing the sacrificial layer (para. 68 “FIG. 10 illustrates device 10 following selective removal of sacrificial material 810 from between upper and lower S/D regions 910, 710, and from around lower S/D regions 710.”);
and depositing a metal layer (wrap-around metal S/D contact 1610) on the first epitaxy layer (710) and the second epitaxy layer (910) at the first side (left side) of the stack of the gate and the channel (see Fig. 16),
Xie-712 fails to teach:
wherein the metal layer, the first epitaxy layer, and the stack of the gate and the channel are aligned along a direction parallel to the plane.
Frougier teaches in Fig. 17:
wherein the metal layer (conductive metal 1810), the first epitaxy layer (first doped material 510), and the stack of the gate (HKMG 1310) and the channel (Si layer 312a) are aligned along a direction parallel to the plane (see Fig. 17, stack, epitaxial layer, and metal contact are arranged horizontally in direction parallel to top surface of the substrate).
Xie-712 discloses the claimed invention except for the stack, epitaxy layer, and metal contact arranged in a direction parallel to a surface of the substrate. Frougier teaches that it is known to arrange the contact to the side of the epitaxial layer on the opposite side of the gate/channel stack. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Xie-712 with vertically integrated wraparound contacts to the side of the epitaxial layer, as taught by Frougier in order to enable vertical integration of the device See MPEP 2144 and/or because it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to put the contact to the side of the epitaxial layer, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70
PNG
media_image1.png
581
804
media_image1.png
Greyscale
With respect to claim 2, Xie-712 further teaches:
wherein the depositing of the metal layer (1610) on the first epitaxy layer (710) and the second epitaxy layer (910) comprises depositing the metal layer between the first epitaxy layer and the second epitaxy layer (see Fig. 16).
With respect to claim 3, Xie-712 further teaches:
wherein the first epitaxy layer comprises silicon germanium (para. 63 “FIG. 7 illustrates device 100 following epitaxial growth of source/drain regions for the lower FET device of the CFET. In an embodiment, boron doped SiGe (SiGe:B) is epitaxially grown from exposed semiconductor surfaces”) having a first concentration ratio of silicon to germanium, and the second epitaxy layer comprises silicon (FIG. 9 illustrates device 100 following epitaxial growth, patterning and selective removal of upper device S/D regions 910. In an embodiment, epitaxial growth of phosphorous doped Si (Si:P) provides S/D regions for nFET devices of the CFET.)
With respect to claim 7, Xie-712 further teaches:
wherein the first epitaxy layer is an n-type material and the second epitaxy layer is a p-type material (para. 67 “In an embodiment, the CFET includes an upper pFET and a lower nFET. In this embodiment, the appropriate doping of the upper and lower S/D regions results in the desired pattern of nFET and pFET for the CFET device.”).
With respect to claim 8, Xie-712 further teaches:
wherein the first epitaxy layer is a p-type material (SiGe:B, para. 63) and the second epitaxy layer is an n-type material (Si:P, para. 66) (para. 66 “The disclosed example provides for the fabrication of a CFET device having an upper nFET and a lower pFET.).
With respect to claim 9, Xie-712 teaches in Fig. 21:
A semiconductor device comprising:
a first stack of a gate and a channel (see annotated Fig. 21 below) between a first side of a first epitaxy layer (left portion of S/D region 710, labeled in Fig. 7) and a second side of the first epitaxy layer formed over a surface and a substrate (top surface of substrate 110), the surface of the substrate being parallel to a plane; (right portion of 710)
a second stack of a gate and a channel on the first stack of gates and channels (see annotated Fig. 21 below),
and located between a first side of a second epitaxy layer (left portion of S/D region 910, labeled in Fig. 9) and a second side of the second epitaxy layer (right portion of 910),
the first side and the second side of the second epitaxy layer being on the first side and the second side, respectively, of the first epitaxy layer (See Fig. 21, the left portion of 910 is on the left portion of 710 and the right portion of 910 is on the right portion of 710);
and a metal layer (wrap-around metal S/D contact 1610) on the first side of the first epitaxy layer and the first side of the second epitaxy layer (1610 is on the epitaxy layers on the left side, see X and Y1 of Fig. 21.
Xie-712 fails to teach:
wherein the metal layer, the first epitaxy layer, and the stack of the gate and the channel are aligned along a direction parallel to the plane.
Frougier teaches in Fig. 17:
wherein the metal layer (conductive metal 1810), the first epitaxy layer (first doped material 510), and the stack of the gate (HKMG 1310) and the channel (Si layer 312a) are aligned along a direction parallel to the plane (see Fig. 17, stack, epitaxial layer, and metal contact are arranged horizontally in direction parallel to top surface of the substrate).
Xie-712 discloses the claimed invention except for the stack, epitaxy layer, and metal contact arranged in a direction parallel to a surface of the substrate. Frougier teaches that it is known to arrange the contact to the side of the epitaxial layer on the opposite side of the gate/channel stack. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Xie-712 with vertically integrated wraparound contacts to the side of the epitaxial layer, as taught by Frougier in order to enable vertical integration of the device See MPEP 2144 and/or because it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to put the contact to the side of the epitaxial layer, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70
PNG
media_image2.png
571
812
media_image2.png
Greyscale
With respect to claim 10, Xie-712 further teaches:
wherein the metal layer (1610) is on:
a top surface of the first side of the first epitaxy layer (see Y1 cut of Fig. 21, 1610 is on the top surface of the left portion of 710);
a top surface and a bottom surface of the first side of the second epitaxy layer (see Y1 cut of Fig. 21, 1610 is completely surrounds the left portion of 910);
and a side surface of the first epitaxy layer and the second epitaxy layer (see Y1 cut of Fig. 21, 1610 is on the side surfaces of 710 and 910);
With respect to claim 11, Xie-712 further teaches:
wherein the metal layer (1610) forms an Ohmic contact with the first side of the first epitaxy layer (left portion of 710) and the first side of the second epitaxy layer (right portion of 910).
The Examiner determines that although Xie-712 does not use the term “ohmic contact,” an ohmic contact between the metal layers and epitaxy layers is implicit because an ohmic contact is necessary for the source/drain contact to function.
With respect to claim 12, Xie-712 further teaches: wherein the first side and the second side of the first epitaxy layer comprise silicon germanium having a first concentration ration of silicon to germanium (para. 63 “FIG. 7 illustrates device 100 following epitaxial growth of source/drain regions for the lower FET device of the CFET. In an embodiment, boron doped SiGe (SiGe:B) is epitaxially grown from exposed semiconductor surfaces”),
and the first side and the second side of the second epitaxy layer comprises silicon (FIG. 9 illustrates device 100 following epitaxial growth, patterning and selective removal of upper device S/D regions 910. In an embodiment, epitaxial growth of phosphorous doped Si (Si:P) provides S/D regions for nFET devices of the CFET.).
With respect to claim 13, Xie-712 further teaches:
wherein the first side and the second side of the first epitaxy layer (710) comprise an n-type material, and the first side and the second side of the second epitaxy layer (910) comprise a p-type material. (para. 67 “In an embodiment, the CFET includes an upper pFET and a lower nFET. In this embodiment, the appropriate doping of the upper and lower S/D regions results in the desired pattern of nFET and pFET for the CFET device.”).
Wirth respect to claim 14, Xie-712 further teaches:
wherein the first side and the second side of the first epitaxy layer and the first stack of the gate and the channel form a first metal-oxide semiconductor (MOS) (710, channels, gate metal, and gate dielectric form a MOSFET, para. 44 teaches that the motivation for Xie-712, reciting “optimizing source/drain contact resistance remains a critical aspect to successful technology scaling. In the instance of complementary metal-oxide-semiconductor (CMOS) technology”)
and the first side and the second side of the second epitaxy layer and the second stack of the gate and the channel form a second MOS. (910, channels, gate metal, and gate dielectric form a MOSFET)
With respect to claim 16, Xie-712 further teaches:
wherein the first stack of the gate and the channel is configured to receive a gate voltage (para. 67 teaches that the device of Xie-712 includes upper and lower FETs. FETs definitionally require a gate voltage to function properly, therefore the limitation of claim 16 is implicit to labelling the device as a FET.)
With respect to claim 17, Xie-712 further teaches:
wherein the second side (right) of the second epitaxy layer (910) is configured to receive a source voltage (connected to one of the independent S/D contacts 2110, see cut Y2 of Fig. 21) and the second side (right) of the first epitaxy layer (710) is configured to receive a drain voltage (connected to another of the independent S/D contacts 2110, see cut Y2 of Fig. 21).
With respect to claim 18, Xie-712 further teaches:
A method for manufacturing the semiconductor device of claim 9,
the method comprising: growing the first side of the first epitaxy layer (left portion of 710) at the first side (left side) of the first stack of the gate and the channel (see annotated Fig. 21 above),
and growing the second side of the first epitaxy layer (right portion of 710) at the second side (right) of the first stack of the gate and the channel (see annotated Fig. 21 above);
the first stack of the gate and the channel formed over a surface of a substrate (top surface of substrate 110), the surface of the substrate being parallel to a plane
applying a sacrificial layer on the first side and the second side of the first epitaxy layer (sacrificial spacer layer 810, see Fig. 9);
growing the first side and the second side of the second epitaxy layer on the sacrificial layer (left and right portion of 910, see Fig. 9);
removing the sacrificial layer (see Fig. 10);
and depositing the metal layer (wrap around S/D metal 1610) on the first side of the first epitaxy layer and the first side of the second epitaxy layer. (see Fig. 16)
Frougier further teaches:
wherein the metal layer (conductive metal 1810), the first epitaxy layer (first doped material 510), and the stack of the gate (HKMG 1310) and the channel (Si layer 312a) are aligned along a direction parallel to the plane (see Fig. 17, stack, epitaxial layer, and metal contact are arranged horizontally in direction parallel to top surface of the substrate).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Xie-712 in view of Frougier as explained above.
With respect to claim 19, Xie-712 teaches:
A method for manufacturing a common output stack transistor, the method comprising
forming a first stack of a gate and a channel (see annotated Fig. 21 above) on a surface of a substrate (substrate 110), the surface of the substrate being parallel to a plane;
forming a second stack of a gate and a channel on the first stack of the gate and the channel (see annotated Fig. 21 above);
growing a first epitaxy layer (S/D regions 710, labeled in Fig. 7) on the substrate (110) and adjacent to a first side and a second side of the first stack of the gate and the channel (see annotated Fig. 21 above);
applying a sacrificial layer on the first epitaxy layer (semiconductor layer 1110);
removing the sacrificial layer (Fig. 15);
growing a second epitaxy layer (S/D region 910) on the sacrificial layer (1110) (Fig. 11, the Examiner notes that the preceding limitations do not have an implied order and the second epitaxy has been grown so that it is on the sacrificial layer 1110 at some point in the manufacture process) and adjacent to a first side and a second side of the second stack of the gate and the channel (see annotated Fig. 21 above);
and depositing a metal layer (wrap around metal S/D contact 1610) on the first epitaxy layer and the second epitaxy layer (see Fig. 16).
Xie-712 fails to teach:
wherein the metal layer, the first epitaxy layer, and the stack of the gate and the channel are aligned along a direction parallel to the plane.
Frougier teaches in Fig. 17:
wherein the metal layer (conductive metal 1810), the first epitaxy layer (first doped material 510), and the stack of the gate (HKMG 1310) and the channel (Si layer 312a) are aligned along a direction parallel to the plane (see Fig. 17, stack, epitaxial layer, and metal contact are arranged horizontally in direction parallel to top surface of the substrate).
Xie-712 discloses the claimed invention except for the stack, epitaxy layer, and metal contact arranged in a direction parallel to a surface of the substrate. Frougier teaches that it is known to arrange the contact to the side of the epitaxial layer on the opposite side of the gate/channel stack. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Xie-712 with vertically integrated wraparound contacts to the side of the epitaxial layer, as taught by Frougier in order to enable vertical integration of the device See MPEP 2144 and/or because it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to put the contact to the side of the epitaxial layer, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70
With respect to claim 20, Xie-712/Frougier teaches all limitations of claim 19 upon which claim 20 depends. Xie-712 further teaches:
and wherein the sacrificial layer comprises silicon germanium having a concentration ratio of silicon to germanium,
which is different from a concentration ratio of silicon to germanium in the first epitaxy layer. (para. 69 “FIG. 11 illustrates device 100 following a merger of upper and lower S/D regions 910, 710 through the epitaxial growth of a semiconductor layer 1110. In an embodiment, conformal epitaxial growth of SiGe.sub.65 merges the S/D regions. In an embodiment having lower S/D regions with high Ge concentrations, merging the S/D regions comprises growth of a thin layer of Si followed by growth of SiGe, such as SiGe.sub.35.”).
Xie-712 does not teach:
wherein the depositing of the metal layer is performed by an atomic layer deposition process,
However, Xie-712 teaches that metal gates can be made by atomic layer deposition (para. 71). Therefore, it would be obvious to also make the metal layer from atomic layer deposition to teach:
wherein the depositing of the metal layer is performed by an atomic layer deposition process,
It would have been obvious to one of ordinary skill in the art at the time of the invention to make the metal layer through an atomic layer deposition process because the known technique of atomic layer deposition of metal was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Xie-712 (US 2023/0040712 A1) and Frougier (US 10,192,867 B1) as applied to claim 3 above and further in view of Xie-184 (US 2021/0296184 A1).
With respect to claim 4, Xie-712/Frougier teaches all limitations of claim 3 upon which claim 4 depends.
Xie-712 differs from claim 4 in that Xie-712 teaches an initial sacrificial layer that the second epitaxial layer is grown on that is not SiGe. However, Xie-712 teaches the use of SiGe as a sacrificial layer with a different composition as the first epitaxial layer is deposited between the first and second epitaxial layers (para. 69 “FIG. 11 illustrates device 100 following a merger of upper and lower S/D regions 910, 710 through the epitaxial growth of a semiconductor layer 1110. In an embodiment, conformal epitaxial growth of SiGe.sub.65 merges the S/D regions. In an embodiment having lower S/D regions with high Ge concentrations, merging the S/D regions comprises growth of a thin layer of Si followed by growth of SiGe, such as SiGe.sub.35.”) Xie-712 also teaches in the process of making the channel and gate stack that SiGe with a large Ge content can be used as a sacrificial material in order to provide a material with a different etch rate as the other layers (para. 51-52).
Xie-184 teaches in para. 53 that “Generally, epitaxial growth, deposition, formation, etc. means the growth of a semiconductor material on a deposition or seed surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface.” Xie-184 further teaches that layer 54 is an “nFET epi” layer that is formed over sacrificial material 52, which can be a semiconductor layer such as amorphous silicon or polycrystalline silicon according para. 55.
Xie-712/Frougier modified by Xie-184 so that a sacrificial seed semiconductor layer is deposited prior to the growth of the second epitaxial layer, and further modifying with the additional teaching of Xie-712 of using a SiGe layer with a different Ge concentration of the first epitaxial layer for etch selectivity teaches:
wherein the sacrificial layer comprises silicon germanium (second sacrificial layer of Xie-712 modified to be deposited before the growth of the second epitaxial in order to act as the sacrificial seed layer taught by Xie-184) having a second concentration ratio of silicon to germanium, which is different from the first concentration ratio of silicon to germanium for the first epitaxy layer (para. 69 “FIG. 11 illustrates device 100 following a merger of upper and lower S/D regions 910, 710 through the epitaxial growth of a semiconductor layer 1110. In an embodiment, conformal epitaxial growth of SiGe.sub.65 merges the S/D regions. In an embodiment having lower S/D regions with high Ge concentrations, merging the S/D regions comprises growth of a thin layer of Si followed by growth of SiGe, such as SiGe.sub.35.”).
Xie-712/Frougier discloses the claimed invention except for the material of the sacrificial layer. Xie-184 teaches that it is known to use a sacrificial semiconductor as a seed layer and Xie-172 further teaches the use of a SiGe sacrificial layer to combine the epitaxial layers and that SiGe can be used as a sacrificial layer in a semiconductor epitaxial stack because of etch selectivity. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Xie-712/Frougier with the teachings of Xie-184 and further teachings of Xie-712 in order to use a sacrificial seed layer with good etch selectivity. See MPEP 2144.
With respect to claim 5, Xie-184 further teaches:
wherein the sacrificial layer (52) comprises a seeding layer for a growth of the second epitaxy layer (para. 53 “Generally, epitaxial growth, deposition, formation, etc. means the growth of a semiconductor material on a deposition or seed surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Xie-712/Frougier in view of Xie-184 as explained above.
With respect to claim 6, Xie-712/Frougier/Xie-184 is silent to the kind of etch used for the removal of the sacrificial layer of SiGe. Therefore, Xie-712/Frougier/Xie-184 does not teach:
wherein the removing the sacrificial layer further comprises dry etching to selectively remove material having the second concentration ratio of silicon to germanium.
However, Xie-712 teaches:
“There are generally two categories of etching, (i) wet etch and (ii) dry etch… Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive-ion etching (RIE) operates under conditions intermediate between sputter and plasma etching.” (para. 61)
It would have been obvious to one of ordinary skill in the art at the time of the invention to use dry etching to selectively remove the sacrificial layer having the second concentration ratio of silicon to germanium because the known technique of dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Xie-712 (US 2023/0040712 A1) and Frougier (US 10,192,867 B1) as applied to claim 10 above and further in view of Xie-684 (US 11,069,684 B1).
With respect to claim 15, Xie-712/Frougier teaches all limitations of claim 10 upon which claim 15 depends. Xie-712 fails to teach:
wherein the metal layer is a metal selected from the group consisting of nickel and platinum.
Xie-684 teaches in col. 9, ln. 61 – col. 10, ln. 6:
wherein the metal layer is a metal selected from the group consisting of nickel and platinum (“A conductive material is then deposited within the via. The conductive material for top source/drain contact 138, bottom source/drain contact 140, and metal gate contact can be of the same or different material. The conductive material can include any suitable conductive material such as, for example, polycrystalline or amorphous silicon, germanium, silicon germanium, a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold))”
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Xie-712 to make the metal layers that are used as source/drain contacts from platinum as taught by Xie-684, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Response to Arguments
Applicant’s arguments, see pages 8-9, filed January 21, 2026, with respect to the specification objection and drawing objection have been fully considered and are persuasive. The objection to the specification and drawing objections have been withdrawn.
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897