Prosecution Insights
Last updated: April 19, 2026
Application No. 18/363,841

POSITION DETERMINING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Aug 02, 2023
Examiner
PETERSON, ERIK T
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kioxia Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
89%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
271 granted / 353 resolved
+8.8% vs TC avg
Moderate +12% lift
Without
With
+12.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
40 currently pending
Career history
393
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
39.3%
-0.7% vs TC avg
§102
24.7%
-15.3% vs TC avg
§112
29.7%
-10.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 353 resolved cases

Office Action

§103
DETAILED ACTION This action is responsive to the application No. 18/363,841 filed on August 2, 2023. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I, corresponding to claims 1-7, in the reply filed on October 23, 2025, is acknowledged. Claims 8-15 are withdrawn from consideration. Information Disclosure Statement Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al. (JP2002198415, citations from machine translation) in view of Harris et al. (US 2007/0275541), Van Der Stam et al. (US 2018/0311762), and Ohkubo et al. (US 2020/0335370). (Re Claims 1 and 6) Kurakowa teaches (see Fig. 4 and lines 168-178, 248-263, 419-443) a position determining method of a wafer (W) which has a plurality of singulated chips (22) and which is pasted on a tape (Fig. 3 and lines 150-161), the position determining method comprising: irradiating, with light (72), the wafer which has a first cut mark provided between the chips (23) and a second cut mark (e) with a width that differs from a width of the first cut mark (lines 176-178, 419-443); determining a position of the wafer based on a width of received light (lines 248-263, 419-443). Kurakowa is silent regarding receiving irradiated light at a position opposing an irradiation position of light across the wafer; and received light having passed through the wafer since Kurakowa uses reflected light for imaging the cut marks (e.g. note locations of 71 and 72 in Fig. 7). A PHOSITA desiring to make, use, and improve upon Kurakowa’s methods would be motivated to look to related art to teach process alternatives and improvements. Related art from Watanabe teaches imaging marks or grooves on a wafer using either reflected light (e.g. Fig. 1) like Kurakowa, or transmitted light (Figs. 4-8) showing the two different techniques are art recognized alternatives. Related art from Van Der Stam teaches imaging widths of cuts using transmitted IR from 7 through the wafer to IR camera 10 (Fig. 1A, ¶¶56-63). Related art from Harris also teaches using transmitted IR from 432 through the wafer to IR camera 436 to image grooves/streets 424, and also teaches scanning the imager to image the entire wafer (¶¶30, 38-42). Ohkubo shows conventional 2D imaging of a trench (e.g. see Figs. 5-6) wherein the transmitted light detected by the imager corresponds to the trench geometry (e.g. width, length, shape, etc.) and is represented by white pixels in the image. Thus when using a conventional 2D imager/camera to recognize a trench or groove as shown by Ohkubo, the pixels of the image simultaneously account for both a width and a length of light from the trench in the 2D image (RE claim 6: wherein a position is determined based on a width and a length), also considering if an image only showed a column of pixels in a single row, e.g. a feature having a width but practically no length, then one would obviously not consider this to be the expected trench or groove and would be excluded or filtered. In view of the prior art, a PHOSITA would find it obvious to use transmitted light instead of reflected light for the groove imaging as taught by Van Der Stam, Harris, and Ohkubo, and therefore arrange the camera/imager on one side of the wafer and opposite to a light source on the opposite side of the wafer. Transmitted light imaging tends to produce a high contrast silhouette of the groove/edges, which makes thresholding and edge detection for positioning and alignment more robust and repeatable. Because the camera is not relying on specular surface reflections, it is typically less sensitive to surface roughness/uniformity, glare/hot spots, and lighting nonuniformities that can result in noise, aberrations, false edges, and other artifacts in reflected-light setups. (Re Claim 7) wherein the second cut mark (e) is provided in an outer circumferential portion of the wafer (see Fig. 4: e in outer circumference), and the position determining method further comprises: irradiating the outer circumferential portion of the wafer with light (as claimed, this includes the wafer simply having incident light from whatever lights are on in the room, e.g. ceiling lights, and it is obvious for manufacturing facilities to have lights on for the workers to see what they are doing, for safety, etc.). Kurakawa, as modified above to employ transmitted light imaging according to Van Der Stam, Harris, and Ohkubo, will also irradiate the outer circumferential portion of the wafer with light, in addition to any ambient light. If implementing the light source of Van Der Stam (Fig. 1A) or Ohkubo (Fig. 2), the entire surface may be illuminated, including the outer circumference. Alternatively, Harris shows the light source and imager are aligned and arranged in a 1:1 manner, thus when imaging Kurakawa’s groove (e) near the perimeter of the wafer, one would position the light source at a corresponding position above the imager. Allowable Subject Matter Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 2 recites the allowable subject matter “…detecting a notch based on the second cut mark”, as set forth in the claimed combination. None of the prior art known to the Examiner detects a notch based on a cut mark, e.g. a trench or groove. Claims 3-5 depend from claim 2 and are allowable based on dependency. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art discloses related wafers with grooves and notches, methods for imaging grooves and detecting notches, and positioning wafers. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Aug 02, 2023
Application Filed
Feb 26, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
89%
With Interview (+12.0%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 353 resolved cases by this examiner. Grant probability derived from career allow rate.

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