DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II drawn to claims 1-15 in the reply filed on 01/23/2026 is acknowledged. Claims 16-20 are directed to the non-elected group are thereby withdrawn. Currently claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/02/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claim 1-5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over (US 20220278196 A1) “Kuang et al.” in view of SERIZAWA, Haruhiko (US 20230053433 A1) “SERIZAWA et al.”.
Regarding Independent Claim 1, Kuang et al. Figs. 3-17C discloses a method for forming a semiconductor device (“a semiconductor device” ¶ [0008]), the method comprising:
forming a first nanosheet structure (“A nanosheet stack 18” ¶ [0016]) in a designated NFET region (“A nanosheet stack 18 is formed over the n-well 12” ¶ [0016]; “fin structures 24n, 24p are formed from the nanosheet stacks 17, 18,” ¶ [0030]) of a semiconductor substrate (“formed over a substrate 10” ¶ [0009]) and a second nanosheet structure (“A nanosheet stack 17” ¶ [0012]) in a designated PFET region (“A nanosheet stack 17 is formed over the p-well 11.” ¶ [0012]; “fin structures 24n, 24p are formed from the nanosheet stacks 17, 18,” ¶ [0030]) of the semiconductor substrate 10,
the designated PFET region separated from the designated NFET region by a distance defining a NFET-to-PFET region (N-to-P region) (Fig. 3 shows n-well 12 and p-well 11 are separated);
forming, in the N-to-P region, a dielectric bar (“high-k dielectric features 36 are formed over the hybrid fins 30”; “hybrid fin 30 is a bi-layer structure including a dielectric liner layer 32 and a dielectric filling layer 34” ¶ [0033]) that separates the first nanosheet structure from the second nanosheet structure (“hybrid fins 30 are formed in the trenches between the neighboring fin structures 24n, 24p” ¶ [0033]);
forming a first backside contact (“a transitional epitaxial layer 60a” ¶ [0058]) in the NFET region and forming a first backside contact extension (“backside contact alignment features 62” ¶ [0055]) extending from the first backside contact 60a to a first side of the dielectric bar (36, 30);
forming a second backside contact (“a transitional epitaxial layer 56a” ¶ [0052]) in the PFET region and forming a second backside contact extension (“backside contact alignment features 58 are selectively formed under the source/drain 56” ¶ [0050]) extending from the second backside contact to an opposing second side of the dielectric bar; and
a first backside power rail (“backside contact alignment features 58 are selectively formed under the source/drain 56 where the source/drain features 56 are to be connected to a backside power rail.” ¶ [0050]).
However, Kuang et al. does not disclose, forming a first backside power rail against at least the first backside contact extension and forming a second backside power rail against at least the second backside contact extension.
In the similar field of endeavor of a nanosheet multi-channel device SERIZAWA et al. Figs. 1-48 discloses forming a first backside power rail against at least the first backside contact extension (“The local wiring 162 is connected to the power supply line 910 through a conductor in the contact hole 311.” ¶ [0038]; “power supply lines 910 and 920 having such structures may be referred to as buried power rails (BPR)” ¶ [0027]) and forming a second backside power rail against at least the second backside contact extension (“The local wiring 262 is connected to the power supply line 920 through a conductor in the contact hole 321” ¶ [0039]; “power supply lines 910 and 920 having such structures may be referred to as buried power rails (BPR)” ¶ [0027]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the contact extension and formation of power rails of SERIZAWA et al. so that a VDD wiring to which a power supply potential VDD is applied, and a VSS wiring to which a power supply potential VSS is applied (“SERIZAWA et al.” ¶ [0025]).
Regarding Claim 2, Kuang et al. as modified by SERIZAWA et al. discloses the limitations of claim 1. However, Kuang et al. does not disclose wherein the dielectric bar is disposed between the first backside power rail and the second backside power rail.
In the similar field of endeavor of a nanosheet multi-channel device SERIZAWA et al. Figs. 1-48 discloses, wherein the dielectric bar (“An insulating wall 50” ¶ [0040]) is disposed between the first backside power rail 910 and the second backside power rail 920 (Fig. 1 shows 50 is between 910 and 920).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the contact extension and formation of power rails of SERIZAWA et al. so that a VDD wiring to which a power supply potential VDD is applied, and a VSS wiring to which a power supply potential VSS is applied (“SERIZAWA et al.” ¶ [0025]).
Regarding Claim 3, Kuang et al. as modified by SERIZAWA et al. discloses the limitations of claim 2. However, Kuang et al. does not disclose, wherein forming the dielectric bar comprises:
forming, in the semiconductor substrate, a deep trench defines the N-to-P region separating the first nanosheet structure from the second nanosheet structure;
depositing a dielectric liner that conforms to sidewalls and an upper surface of the first and second nanosheet structures, and conforms to sidewalls and a base of the deep trench; and
removing a first portion of the dielectric liner that conforms to the sidewalls and the upper surface of the first and second nanosheet structures, while maintaining a second portion of the dielectric liner in the deep trench so as to form the dielectric bar.
In the similar field of endeavor of a nanosheet multi-channel device SERIZAWA et al. Figs. 25-29 discloses, wherein forming the dielectric bar comprises:
forming, in the semiconductor substrate (“a substrate 101” ¶ [0027]), a deep trench defines (“trenches 105” ¶ [0059]) the N-to-P region separating the first nanosheet structure from the second nanosheet structure (“trenches 105 for the isolation films 102 are formed on the surface of the substrate 101 on the sides of the fins 91 and 92” ¶ [0059]);
depositing a dielectric liner that conforms to sidewalls and an upper surface of the first and second nanosheet structures, and conforms to sidewalls and a base of the deep trench (“FIG. 28, an insulating film 106 is formed to cover the top and side surfaces of the fins 91 and 92 and the top surface of the isolation films 102. The insulating film 106 is formed to fill the gap between the fins 91 and 92.” ¶ [0061]); and
removing a first portion of the dielectric liner that conforms to the sidewalls and the upper surface of the first and second nanosheet structures, while maintaining a second portion of the dielectric liner in the deep trench so as to form the dielectric bar (“as depicted in FIGS. 11 and 29, the insulating film 106 is etched in such a manner as to remain in the gap between the fins 91 and 92, thereby forming the insulating wall 50.” ¶ [0062]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the formation steps of insulating walls of SERIZAWA et al. in order to function to separate gate structures formed over the fin structures (Kuang et al. ¶ [0035]).
Regarding Claim 4, Kuang et al. as modified by SERIZAWA et al. discloses the limitations of claim 3. Kuang et al. further discloses, a first metal material that defines the first and second backside contacts (“The transitional epitaxial layer 56a may include one or more layers of Si, SiP, SiC and SiCP. The transitional epitaxial layer 56a also include n-type dopants, such as phosphorus (P), arsenic (As), etc.” ¶ [0052]) and a second metal material that defines the first and second backside contact extensions (“the backside contact alignment feature 58 may include other materials such as Si, Ge, a compound semiconductor such as SiC, GeAs, GaP, InP, InAs, and/or InSb, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof.” ¶ [0051]; “The backside contacts alignment features 62 may be similar to the backside contact alignment features 58 described above” ¶ [0055]).
However, Kuang et al. does not disclose, wherein forming the first backside contact and the first backside contact extension, and the second backside contact and the second backside contact extension comprises:
depositing an interlayer dielectric (ILD) on the semiconductor substrate to encapsulate the dielectric bar;
replacing a first portion of the ILD with a first metal material that defines the first and second backside contacts; and
replacing a second portion of the ILD with a second metal material that defines the first and second backside contact extensions.
In the similar field of endeavor of FET semiconductor devices, SERIZAWA et al. Figs 2-4 discloses, wherein forming the first backside contact and the first backside contact extension, and the second backside contact and the second backside contact extension comprises:
depositing an interlayer dielectric (ILD) 64 on the semiconductor substrate 101 to encapsulate the dielectric bar 50 (“An insulating film 64 is formed on the wall 50” ¶ [0042);
replacing a first portion of the ILD with a first metal material that defines the first and second backside contacts (“local wirings 164 and 264, ….is formed on the insulating film 64.” ¶ [0042]); and
replacing a second portion of the ILD with a second metal material that defines the first and second backside contact extensions (“Signal lines 411 and 421 are formed in the insulating film 64. The signal line 411 is connected to the local wiring 162 through a conductor in the contact hole 313. The signal line 421 is connected to the local wiring 262 through a conductor in the contact hole 323.” ¶ [0044]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the forming steps of contact and contact extensions wirings of SERIZAWA et al. in order to be connected to the power supply line (SERIZAWA et al. ¶ [0038]).
Regarding Claim 5, Kuang et al. as modified by SERIZAWA et al. discloses the limitations of claim 4. Kuang et al. further discloses, wherein the dielectric bar comprises a first dielectric material (“the hybrid fins 30 include a high-k metal oxide, such as HfO.sub.2, ZrO.sub.2, HfAlOx, HfSiOx, Al.sub.2O.sub.3, and the like, a low-k material such as SiONC, SiCN, SiOC, or other dielectric material. In the example of FIG. 4, the hybrid fin 30 is a bi-layer structure including a dielectric liner layer 32 and a dielectric filling layer 34. In some embodiments, the dielectric liner layer 32 may include a low-k material, such as SiONC, SiCN, SiOC, or other dielectric material, that provide etch resistance during replacement gate processes. The dielectric filling layer 34 may be a dielectric material, such as silicon oxide.” ¶ [0033]) and the ILD comprises a second dielectric material different form the first dielectric material (“The materials for the ILD layer 68 include compounds comprising Si, O, C, and/or H, such as silicon oxide, SiCOH and SiOC.” ¶ [0061]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over (US 20220278196 A1) “Kuang et al.” in view of SERIZAWA, Haruhiko (US 20230053433 A1) “SERIZAWA et al.” further in view of LAI, Jui-Yao (US 20170207166 A1) “LAI et al.”.
Regarding Claim 6, Kuang et al. as modified by SERIZAWA et al. discloses the limitations of claim 5. However, Kuang et al. does not disclose, wherein forming the first backside contact and the first backside contact extension, and the second backside contact and the second backside contact extension further comprises:
performing a first etching process selective to the second dielectric material so as to form contact trenches;
filling the contact trenches with the first metal material;
performing a second etching process selective to the second dielectric material so as to form contact extension trenches without etching the dielectric bar; and
filling the contact extension trenches with the second metal material.
In the similar field of endeavor of FET semiconductor devices, LAI et al. Figs 10-12 discloses, wherein forming the first backside contact and the first backside contact extension, and the second backside contact and the second backside contact extension further comprises:
performing a first etching process selective to the second dielectric material so as to form contact trenches (“an opening 65 is formed in the insulating layer 60” ¶ [0028]);
filling the contact trenches with the first metal material (“In the opening 65, a conductive material is filled to form a local interconnect 90” ¶ [0031]);
performing a second etching process selective to the second dielectric material so as to form contact extension trenches without etching the dielectric bar (“a patterning operation is performed to form via holes” ¶ [0036]); and
filling the contact extension trenches with the second metal material (“the via holes are filed with one or more conductive materials so as to form a first via plug V1” ¶ [0036]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the forming steps of contact and contact extensions wirings of LAI et al. in order to offer several advantages. For example, in the present disclosure, since a local interconnect (and a local metal layer) is formed in a self-aligned manner, short circuits caused by process variation (e.g., alignment errors in a lithography operation) can be avoided. Further, design flexibility in designing standard cells can be enhanced (LAI et al. ¶ [0039]).
Regarding Claim 8, Kuang et al. Figs. 3-17C discloses, method for forming a semiconductor device, the method comprising:
forming a first fin trench in a semiconductor substrate to define a first plurality of nanosheet fins in a designated NFET region of the semiconductor substrate (“The fin structure 24n may be formed by patterning and etching the hard mask layer 22, the top spacing layer 20, and the nanosheet stacks 17, 18 by one or more etching processes. In FIG. 3, the fin structures 24n, 24p are formed along the X direction.” ¶ [0030]);
forming a second fin trench in the semiconductor substrate to define a second plurality of nanosheet fins in a designated PFET region of the semiconductor substrate (“fin structures 24n, 24p are formed from the nanosheet stacks 17, 18, the top spacing layer 20, and the hard mask layer 22,” ¶ [0030]);
forming, in the N-to-P region, a dielectric bar (“high-k dielectric features 36 are formed over the hybrid fins 30”; “hybrid fin 30 is a bi-layer structure including a dielectric liner layer 32 and a dielectric filling layer 34” ¶ [0033]) that separates the first nanosheet structure from the second nanosheet structure (“hybrid fins 30 are formed in the trenches between the neighboring fin structures 24n, 24p” ¶ [0033]);
forming a first backside contact (“a transitional epitaxial layer 60a” ¶ [0058]) in the NFET region and forming a first backside contact extension (“backside contact alignment features 62” ¶ [0055]) extending from the first backside contact 60a to a first side of the dielectric bar (36, 30);
forming a second backside contact (“a transitional epitaxial layer 56a” ¶ [0052]) in the PFET region and forming a second backside contact extension (“backside contact alignment features 58 are selectively formed under the source/drain 56” ¶ [0050]) extending from the second backside contact to an opposing second side of the dielectric bar; and
a first backside power rail (“backside contact alignment features 58 are selectively formed under the source/drain 56 where the source/drain features 56 are to be connected to a backside power rail.” ¶ [0050]).
However, Kuang et al. does not disclose, forming, in the semiconductor substrate, a deep trench between a first nanosheet fin included in the first plurality of nanosheet fins and a second nanosheet fin included in the second plurality of nanosheet fins to define a NFET-to-PFET region (N-to-P region);
forming a first backside power rail against at least the first backside contact extension and forming a second backside power rail against at least the second backside contact extension.
In the similar field of endeavor of a nanosheet multi-channel device SERIZAWA et al. Figs. 1-48 discloses, forming, in the semiconductor substrate (“a substrate 101” ¶ [0027]), a deep trench (“trenches 105” ¶ [0059]) between a first nanosheet fin included in the first plurality of nanosheet fins and a second nanosheet fin included in the second plurality of nanosheet fins to define a NFET-to-PFET region (N-to-P region) (“trenches 105 for the isolation films 102 are formed on the surface of the substrate 101 on the sides of the fins 91 and 92” ¶ [0059]);
forming a first backside power rail against at least the first backside contact extension (“The local wiring 162 is connected to the power supply line 910 through a conductor in the contact hole 311.” ¶ [0038]; “power supply lines 910 and 920 having such structures may be referred to as buried power rails (BPR)” ¶ [0027]) and forming a second backside power rail against at least the second backside contact extension (“The local wiring 262 is connected to the power supply line 920 through a conductor in the contact hole 321” ¶ [0039]; “power supply lines 910 and 920 having such structures may be referred to as buried power rails (BPR)” ¶ [0027]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the contact extension and formation of power rails of SERIZAWA et al. so that a VDD wiring to which a power supply potential VDD is applied, and a VSS wiring to which a power supply potential VSS is applied (“SERIZAWA et al.” ¶ [0025]).
Claim 7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over (US 20220278196 A1) “Kuang et al.” in view of SERIZAWA, Haruhiko (US 20230053433 A1) “SERIZAWA et al.” further in view of Chu, Feng-Ching (US 20210391421 A1) “Chu et al.”.
Regarding Claim 7, Kuang et al. as modified by SERIZAWA et al. discloses the limitations of claim 1. However, Kuang et al. does not disclose, further comprising forming a backside power distribution network (BSPDN) against one or both of the first backside power rail and the second backside power rail.
In the similar field of endeavor of FET semiconductor devices, Chu et al. Figs 21A-21B discloses, further comprising forming a backside power distribution network (BSPDN) (“a backside interconnect 286” ¶ [0052]) against one or both of the first backside power rail and the second backside power rail (“backside power rails 284” ¶ [0052]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the backside interconnect structure with the power rails in order to increase the number of metal tracks available in the device for directly connecting to source/drain contacts and vias. It also increases the gate density for greater device integration than other structures without the backside power rails. The backside power rails may have wider dimension than the first level metal (MO) tracks on the frontside of the device, which beneficially reduces the backside power rail resistance (Chu et al. ¶ [0052]).
Regarding Claim 9, Kuang et al. as modified by SERIZAWA et al. discloses the limitations of claim 8. However, Kuang et al. does not disclose, forming a first backside power rail having a first surface against the first backside contact extension;
forming a second backside power rail having a first surface against the second backside contact extension; and
forming a backside power distribution network (BSPDN) against an opposing second surface of the first backside power rail and against an opposing second surface of the second backside power rail.
In the similar field of endeavor of a nanosheet multi-channel device SERIZAWA et al. Figs. 1-48 discloses forming a first backside power rail against at least the first backside contact extension (“The local wiring 162 is connected to the power supply line 910 through a conductor in the contact hole 311.” ¶ [0038]; “power supply lines 910 and 920 having such structures may be referred to as buried power rails (BPR)” ¶ [0027]) and forming a second backside power rail against at least the second backside contact extension (“The local wiring 262 is connected to the power supply line 920 through a conductor in the contact hole 321” ¶ [0039]; “power supply lines 910 and 920 having such structures may be referred to as buried power rails (BPR)” ¶ [0027]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the contact extension and formation of power rails of SERIZAWA et al. so that a VDD wiring to which a power supply potential VDD is applied, and a VSS wiring to which a power supply potential VSS is applied (“SERIZAWA et al.” ¶ [0025]).
However, SERIZAWA et al. does not disclose, forming a backside power distribution network (BSPDN) against an opposing second surface of the first backside power rail and against an opposing second surface of the second backside power rail.
In the similar field of endeavor of FET semiconductor devices, Chu et al. Figs 21A-21B discloses, further comprising forming a backside power distribution network (BSPDN) (“a backside interconnect 286” ¶ [0052]) against an opposing second surface of the second backside power rail (“backside power rails 284” ¶ [0052]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the backside interconnect structure with the power rails in order to increase the number of metal tracks available in the device for directly connecting to source/drain contacts and vias. It also increases the gate density for greater device integration than other structures without the backside power rails. The backside power rails may have wider dimension than the first level metal (MO) tracks on the frontside of the device, which beneficially reduces the backside power rail resistance (Chu et al. ¶ [0052]).
Regarding Claim 10, Kuang et al. as modified by SERIZAWA et al. and Chu et al. discloses the limitations of claim 9. However, Kuang et al. does not disclose, wherein the dielectric bar is disposed between the first backside power rail and the second backside power rail.
In the similar field of endeavor of a nanosheet multi-channel device SERIZAWA et al. Figs. 1-48 discloses, wherein the dielectric bar (“An insulating wall 50” ¶ [0040]) is disposed between the first backside power rail 910 and the second backside power rail 920 (Fig. 1 shows 50 is between 910 and 920).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the contact extension and formation of power rails of SERIZAWA et al. so that a VDD wiring to which a power supply potential VDD is applied, and a VSS wiring to which a power supply potential VSS is applied (“SERIZAWA et al.” ¶ [0025]).
Claim 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over (US 20220278196 A1) “Kuang et al.” in view of SERIZAWA, Haruhiko (US 20230053433 A1) “SERIZAWA et al.” further in view of Chu, Feng-Ching (US 20210391421 A1) “Chu et al.” further in view of LIAW, Jhon-Jhy (US 20200051980 A1) “LIAW et al.”.
Regarding Claim 11, Kuang et al. as modified by SERIZAWA et al. and Chu et al. discloses the limitations of claim 10. However, Kuang et al. does not disclose, further comprising forming a first gate cut isolation region in the first fin trench and a second gate cut isolation region in the second fin trench.
In the similar field of endeavor of FET devices LIAW et al. Figs. 9-23 discloses further comprising forming a first gate cut isolation region 1028 in the first fin trench and a second gate cut isolation region 1032 (“at least one of the dielectric fins 1024, 1028, 1032, 1036 is between a pair of the adjacent recess-shaped end portions of the gate electrodes 952A-952C” ¶ [0135]) in the second fin trench (“physical elements or layers can be formed by using the gate electrode or the gate contact illustrated in FIG. 22 as patterns.” ¶ [0131]).
Regarding Claim 12, Kuang et al. as modified by SERIZAWA et al. and Chu et al. discloses the limitations of claim 11. However, Kuang et al. does not disclose, wherein forming the dielectric bar, the first gate cut isolation region, and the second gate cut isolation region comprises:
depositing a dielectric liner that conforms to sidewalls and an upper surface of the first plurality of nanosheet structures along with sidewalls and a base of the first fin trench, conforms to sidewalls and an upper surface of the second plurality of nanosheet structure along with sidewalls and a base of the second fin trench, and conforms to sidewalls and a base of the deep trench; and
removing a first portion of the dielectric liner from the sidewalls and the upper surface of the first plurality of nanosheet structures and second plurality of nanosheet structures, while maintaining a second portion of the dielectric liner in the first and second fin trenches so as to define the first and second gate cut isolation regions, and in the deep trench so as to form the dielectric bar.
In the similar field of endeavor of FET devices LIAW et al. Figs. 9-23 discloses, wherein forming the dielectric bar, the first gate cut isolation region, and the second gate cut isolation region comprises:
depositing a dielectric liner that conforms to sidewalls and an upper surface of the first plurality of nanosheet structures along with sidewalls and a base of the first fin trench, conforms to sidewalls and an upper surface of the second plurality of nanosheet structure along with sidewalls and a base of the second fin trench, and conforms to sidewalls and a base of the deep trench (“A capping layer 212 is formed to cover the gate electrodes 152A-152C and the isolation structure 106. The capping layer 212 can be formed by suitable deposition techniques, such as a chemical vapor deposition (CVD) process. In some embodiments, the formation of the capping layer 212 includes filling first and second trenches T1, T2 with a dielectric material.” ¶ [0089]); and
removing a first portion of the dielectric liner from the sidewalls and the upper surface of the first plurality of nanosheet structures and second plurality of nanosheet structures, while maintaining a second portion of the dielectric liner in the first and second fin trenches so as to define the first and second gate cut isolation regions, and in the deep trench so as to form the dielectric bar (“the dielectric fins 650, 652, 654, 656 can be formed by a single dielectric material or by multiple dielectric materials in a combination. Example materials of the dielectric fins 650, 652, 654, 656 include, but are not limited to, a high-k dielectric layer, an interfacial layer, and/or combinations thereof. For example, the dielectric fins 650, 652, 654, 656 may include a nitride-based dielectric, a metal oxide dielectric, hafnium oxide (HfO.sub.2), tantalum oxide (Ta.sub.2O.sub.5), titanium oxide (TiO.sub.2), zirconium oxide (ZrO.sub.2), aluminium oxide (Al.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), or combinations thereof.” ¶ [0110]).
Regarding Claim 13, Kuang et al. as modified by SERIZAWA et al., Chu et al. and LIAW et al. discloses the limitations of claim 12. Kuang et al. further discloses, a first metal material that defines the first and second backside contacts (“The transitional epitaxial layer 56a may include one or more layers of Si, SiP, SiC and SiCP. The transitional epitaxial layer 56a also include n-type dopants, such as phosphorus (P), arsenic (As), etc.” ¶ [0052]) and a second metal material that defines the first and second backside contact extensions (“the backside contact alignment feature 58 may include other materials such as Si, Ge, a compound semiconductor such as SiC, GeAs, GaP, InP, InAs, and/or InSb, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof.” ¶ [0051]; “The backside contacts alignment features 62 may be similar to the backside contact alignment features 58 described above” ¶ [0055]).
However, Kuang et al. does not disclose, wherein forming the first backside contact and the first backside contact extension, and the second backside contact and the second backside contact extension comprises:
depositing an interlayer dielectric (ILD) on the semiconductor substrate to encapsulate the dielectric bar;
replacing a first portion of the ILD with a first metal material that defines the first and second backside contacts; and
replacing a second portion of the ILD with a second metal material that defines the first and second backside contact extensions.
In the similar field of endeavor of FET semiconductor devices, SERIZAWA et al. Figs 2-4 discloses, wherein forming the first backside contact and the first backside contact extension, and the second backside contact and the second backside contact extension comprises:
depositing an interlayer dielectric (ILD) 64 on the semiconductor substrate 101 to encapsulate the dielectric bar 50 (“An insulating film 64 is formed on the wall 50” ¶ [0042);
replacing a first portion of the ILD with a first metal material that defines the first and second backside contacts (“local wirings 164 and 264, ….is formed on the insulating film 64.” ¶ [0042]); and
replacing a second portion of the ILD with a second metal material that defines the first and second backside contact extensions (“Signal lines 411 and 421 are formed in the insulating film 64. The signal line 411 is connected to the local wiring 162 through a conductor in the contact hole 313. The signal line 421 is connected to the local wiring 262 through a conductor in the contact hole 323.” ¶ [0044]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the forming steps of contact and contact extensions wirings of SERIZAWA et al. in order to be connected to the power supply line (SERIZAWA et al. ¶ [0038]).
Regarding Claim 14, Kuang et al. as modified by SERIZAWA et al. discloses the limitations of claim 13. Kuang et al. further discloses, wherein the dielectric bar comprises a first dielectric material (“the hybrid fins 30 include a high-k metal oxide, such as HfO.sub.2, ZrO.sub.2, HfAlOx, HfSiOx, Al.sub.2O.sub.3, and the like, a low-k material such as SiONC, SiCN, SiOC, or other dielectric material. In the example of FIG. 4, the hybrid fin 30 is a bi-layer structure including a dielectric liner layer 32 and a dielectric filling layer 34. In some embodiments, the dielectric liner layer 32 may include a low-k material, such as SiONC, SiCN, SiOC, or other dielectric material, that provide etch resistance during replacement gate processes. The dielectric filling layer 34 may be a dielectric material, such as silicon oxide.” ¶ [0033]) and the ILD comprises a second dielectric material different form the first dielectric material (“The materials for the ILD layer 68 include compounds comprising Si, O, C, and/or H, such as silicon oxide, SiCOH and SiOC.” ¶ [0061]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over (US 20220278196 A1) “Kuang et al.” in view of SERIZAWA, Haruhiko (US 20230053433 A1) “SERIZAWA et al.” further in view of Chu, Feng-Ching (US 20210391421 A1) “Chu et al.”, further in view of LIAW, Jhon-Jhy (US 20200051980 A1) “LIAW et al.” further in view of LAI, Jui-Yao (US 20170207166 A1) “LAI et al.”.
Regarding Claim 15, Kuang et al. as modified by SERIZAWA et al. discloses the limitations of claim 14. However, Kuang et al. does not disclose, wherein forming the first backside contact and the first backside contact extension, and the second backside contact and the second backside contact extension further comprises:
performing a first etching process selective to the second dielectric material so as to form contact trenches;
filling the contact trenches with the first metal material;
performing a second etching process selective to the second dielectric material so as to form contact extension trenches without etching the dielectric bar; and
filling the contact extension trenches with the second metal material.
In the similar field of endeavor of FET semiconductor devices, LAI et al. Figs 10-12 discloses, wherein forming the first backside contact and the first backside contact extension, and the second backside contact and the second backside contact extension further comprises:
performing a first etching process selective to the second dielectric material so as to form contact trenches (“an opening 65 is formed in the insulating layer 60” ¶ [0028]);
filling the contact trenches with the first metal material (“In the opening 65, a conductive material is filled to form a local interconnect 90” ¶ [0031]);
performing a second etching process selective to the second dielectric material so as to form contact extension trenches without etching the dielectric bar (“a patterning operation is performed to form via holes” ¶ [0036]); and
filling the contact extension trenches with the second metal material (“the via holes are filed with one or more conductive materials so as to form a first via plug V1” ¶ [0036]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify nFET and pFET structures of Kuang et al. including the forming steps of contact and contact extensions wirings of LAI et al. in order to offer several advantages. For example, in the present disclosure, since a local interconnect (and a local metal layer) is formed in a self-aligned manner, short circuits caused by process variation (e.g., alignment errors in a lithography operation) can be avoided. Further, design flexibility in designing standard cells can be enhanced (LAI et al. ¶ [0039]).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893