Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/2/2023 and 1/31/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Barthelmess et al. US 2005/0258448 in view of Vobecky et al. US 2024/0038880 (WO 2022/112169).
Re claim 1, Barthelmes teaches a semiconductor device (fig 1) comprising:
a semiconductor body (100, fig1, [23]) having a first surface (101, fig1, [23]), a second surface (102, fig1, [23]) opposite the first surface in a vertical direction, a gate region (42, fig1, [24]), and an active region (region around 52, fig1, [23]) arranged adjacent to the gate region in a horizontal direction;
a first emitter of a first conductivity type (20 p-type, fig1, [23]), a first base of a second conductivity type (30 n type, fig1, [23]), and a second base of the first conductivity type (40 p-type, fig1, [23]) which are arranged consecutively between the second surface (102, fig1, [23]) and the first surface (101, fig1, [23]) in the vertical direction;
a front-facing emitter of the second conductivity type (50 n+, fig1, [23]) arranged in the active region and extending from the first surface (101, fig1, [23]) to the second base (40, fig1, [23]) in the vertical direction; and
a plurality of short-circuit regions (p-type region under 52 between 50 in top surface 101, fig1) of the first conductivity type extending from the first surface (101, fig1, [23]) through the front-facing emitter (50 n+, fig1, [23]) to the second base (40, fig1, [23]),
wherein the active region has a first edge region (left region around 52 facing 42, fig1, [23]) adjacent to the gate region in the horizontal direction,
a failure region (region under 52 around center part of 52, fig1, [23]) adjacent to the first edge region in the horizontal direction, and
a second edge region (right region around 52 facing 103, fig1, [23]) adjacent to the failure region in the horizontal direction.
Barthelmes does not explicitly show wherein an average density of the short-circuit regions arranged in the failure region is lower than an average density of the short-circuit regions arranged in each of the first edge region and the second edge region.
Vobecky teaches a failure region (center part with low density 71, fig1C, [71]) adjacent to the first edge region (high density 71 region facing gate 410, fig1C, [53, 71]) in the horizontal direction, and a second edge region (high density 71 region facing away gate 410, fig1C, [53, 71]) adjacent to the failure region in the horizontal direction, wherein an average density of the short-circuit regions (71, fig1C, [71]) arranged in the failure region is lower than an average density of the short-circuit regions arranged in each of the first edge region and the second edge region (fig1C).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Barthelmes and Vobecky to adjust the layout of the short region pattern. The motivation to do so is to enhance di/dt for fast turn-on (Vobecky, [18]).
Re claim 2, Barthelmes modified above teaches the semiconductor device of claim 1, wherein a cross-sectional area of the failure region in the horizontal plane is between 10% and 50% of a total surface area of the semiconductor body (Vobecky, 71, fig1C, [71]).
Re claim 3, Barthelmes modified above teaches the semiconductor device of claim 1, wherein each of the short-circuit regions is columnar shaped and has a round, oval or polygonal cross-section in the horizontal direction (Vobecky, 71, fig1C and 1H, [71]).
Re claim 4, Barthelmes modified above teaches the semiconductor device of claim 3, wherein an extension of each of the short- circuit regions in the horizontal direction is a maximum of 200µm (Vobecky, 71 E1 between 50-250 µm, fig1C and 1H and 1E, [71, 76]).
Re claim 5, Barthelmes modified above teaches the semiconductor device of claim 3, wherein in the first edge region and the second edge region, the distance between two directly adjacent short-circuit regions is between 200 µm and 800 µm (Vobecky, 71 D1 between 300-500 µm, fig1C and 1H and 1E, [71, 77]), and wherein in the failure region, the distance between two directly adjacent short-circuit regions is at least 1000µm (Vobecky, distance between 71 in center wider than edge region, fig1C, [71, 76, 77]).
Re claim 6, Barthelmes modified above teaches the semiconductor device of claim 3, wherein each of the short-circuit regions has an identical cross-sectional area in the horizontal plane (Vobecky, 71, fig1C and 1H, [71]).
Re claim 7, Barthelmes modified above teaches the semiconductor device of claim 1, wherein each of the short-circuit regions has an annular shape (Vobecky, 71, fig1C, [71]), such that the front-facing emitter (Vobecky, 310, fig1C and 1H, [69]) is divided by the short-circuit regions into individual, concentric rings.
Re claim 8, Barthelmes modified above teaches the semiconductor device of claim 7, wherein a width of each of the short-circuit regions in the horizontal direction is a maximum of 500µm (Vobecky, 71 E1 between 50-250 µm, fig1C and 1H and 1E, [71, 76]).
Re claim 9, Barthelmes modified above teaches the semiconductor device of claim 7, wherein in the first edge region and the second edge region, the distance between two directly adjacent short-circuit regions is between 200µm and 800µm (Vobecky, 71 D1 between 300-500 µm, fig1C and 1H and 1E, [71, 77]), and wherein in the failure region, the distance between two directly adjacent short-circuit regions is at least 1000µm (Vobecky, distance between 71 in center wider than edge region, fig1C, [71, 76, 77]).
Re claim 10, Barthelmes modified above teaches the semiconductor device of claim 1, wherein at least one of the short-circuit regions has an annular shape (Vobecky, 71, fig1C, [71]), and wherein at least one of the short-circuit regions is columnar shaped and has a round (Vobecky, 71, fig1C and 1H, [71]), oval or polygonal cross-section in the horizontal direction.
Re claim 11, Barthelmes modified above teaches the semiconductor device of claim 10, wherein at least one of the short-circuit regions arranged in the second edge region has an annular shape (Vobecky, 71, fig1C, [71]).
Re claim 12, Barthelmes modified above teaches the semiconductor device of claim 1, further comprising: a gate electrode (Barthelmes, 42, fig1, [24]) arranged in the gate region on the first surface (Barthelmes, 101, fig1, [23]) and electrically connected to the second base (Barthelmes, 40 p-type, fig1, [23]); a cathode electrode (Barthelmes, 52, fig1, [23]) arranged in the active region on the first surface (Barthelmes, 101, fig1, [23]) and electrically connected to the front-facing emitter (Barthelmes, 50 n+, fig1, [23]); and an anode electrode (Barthelmes, 22, fig1, [23]) arranged on the second surface (Barthelmes, 102, fig1, [23]) and electrically connected to the first emitter (Barthelmes, 20 p-type, fig1, [23]).
Re claim 13, Barthelmes modified above teaches the semiconductor device of claim 12, wherein the cathode electrode has at least one annular discontinuity within the failure region (Barthelmes, 52 adjusted according to Vobecky 310 in fig1c, fig1, [23]).
Claim(s) 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Barthelmess et al. US 2005/0258448 in view of Vobecky et al. US 2024/0038880 (WO 2022/112169) and Schenk et al. US 2021/0036136.
Re claim 14, Barthelmes teaches the semiconductor device of claim 12, wherein the cathode (Vobecky, 310, fig1F) has a notch (Vobecky, 4110, fig1C, 1E and 1F) within the failure region (Vobeck, region around 410 with low density of 71, fig1C), such that the cathode electrode in the failure region is at least partially discontinuous (Vobecky, fig1C, 1E).
Barthelmes does not explicitly show a housing with a housing lid, wherein the housing lid contacts the cathode electrode, wherein the housing lid has a notch within the failure region, such that the contact between the housing lid and the cathode electrode in the failure region is at least partially discontinuous.
Schenk teaches a housing with a housing lid (18 and 19, fig4, [115, 177]), wherein the housing lid contacts the cathode electrode (10, fig4, [177]), wherein the housing lid has a same width corresponding the cathode electrode (fig4, [115]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Barthelmes, Vobecky and Schenk to use a copper alloy disk contact with the same shape as the cathode/anode electrode. The motivation to do so is to effectively conduct current away from the cathode region (Schenk, [115]).
Re claim 15, Barthelmes does not explicitly show the semiconductor device of claim 12, further comprising: a first contact disk in electrical contact with the cathode electrode; and a second contact disk in electrical contact with the anode electrode.
Schenk teaches a first contact disk (18, fig4, [115, 177]) in electrical contact with the cathode electrode (10, fig2, [177]); and a second contact disk (19, fig4, [115, 177]) in electrical contact with the anode electrode (11, fig4, [115, 177]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Barthelmes, Vobecky and Schenk to use a copper alloy disk contact. The motivation to do so is to effectively conduct current away from the cathode region (Schenk, [115]).
Re claim 16, Barthelmes modified above teaches the semiconductor device of claim 15, wherein the first contact disk and/or the second contact disk each have or comprise a copper alloy (Schenk, [115, 177]), an aluminum alloy, or carbon.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812