DETAILED ACTION
The instant application having Application No. 18/364,181 filed on 08/02/2023 is presented for examination by the examiner.
Claim 1-20 is/are pending in the application.
Claims 1, 10 and 18 is/are independent claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Information Disclosure Statement
As required by M.P.E.P. 609, the applicant’s submissions of the Information Disclosure Statement dated 08/12/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter as being software, per se.
Regarding claim 1, the claim calls for a system; however, there is no hardware element found within the claimed system. As recited in the body of the claim, the claimed system contains “one or more higher-performance compute nodes”, “a communication backbone”, and “lower-performance compute nodes”. The specification does not explicitly define how the “one or more higher-performance compute nodes”, “a communication backbone”, and “lower-performance compute nodes” are implemented. One of ordinary skill in the art would understand that “one or more higher-performance compute nodes”, “a communication backbone”, and “lower-performance compute nodes” could be implemented in software, which is non-statutory subject matter. It’s noted that the claim recites ‘a vehicle' Said “vehicle” may not be a part of the claimed system. The nominal recitation of the machine/device in the preamble with an absence of a hardware element in the body of the claim fails to make the claim statutory under 35 USC 101. See Am. Med. Sys., Inc v. Biolitec, Inc., 618 F.3d 1354, 1358 (Fed. Cir. 2010). See also Ex parte Cohen et al., (Appeal No. 2009-011366) for details. It is suggested that the claim be further amended to positively recite at least one hardware embodiment in the body of the claim to make the claim statutory under 35. U.S.C. 101.
Claims 2-9 are rejected under 35 U.S.C. 101 as directed to non-statutory subject matter for at least the reason stated above. Claims 2-9 are depended on claim 1, however, they do not add any feature or subject matter that would solve any of the non-statutory deficiencies of claim 1.
Claims 10-17 are rejected under 35 U.S.C. 101 because the claims are/is directed to an abstract idea without being integrated into a practical application nor being significantly more.
Per claims 10 and 18, the claims are within at least one of the four categories of patent eligible subject matter as it is directing to a method/apparatus claim under Step 1.
However, per claim 10, the limitations “identifying first processes for execution on one or more higher-performance compute nodes of the asymmetric distributed compute nodes”, and “identifying second processes for execution on one or more lower-performance compute nodes of the asymmetric distributed compute nodes”, as drafted, recite functions that, under its broadest reasonable interpretation, covers functions that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components. That is, the limitation “identifying first processes for execution on one or more higher-performance compute nodes of the asymmetric distributed compute nodes”, and “identifying second processes for execution on one or more lower-performance compute nodes of the asymmetric distributed compute nodes” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the functions through observation, evaluation, judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and fall within the “Mental Processes” grouping of abstract ideas under Prong 1 Step 2A.
Under Prong 2 Step 2A, this judicial exception is not integrated into a practical application. The claim recites the following additional elements “compute nodes in a vehicle”, “directing the one or more higher-performance compute nodes to execute the first processes to perform a first portion of the software-defined vehicle functions for the vehicle”, and “directing the one or more lower-performance compute nodes to execute the second processes to perform a second portion of the software-defined vehicle functions for the vehicle.” The “compute nodes in a vehicle” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception.
The addition element “directing the one or more higher-performance compute nodes to execute the first processes to perform a first portion of the software-defined vehicle functions for the vehicle”, and “directing the one or more lower-performance compute nodes to execute the second processes to perform a second portion of the software-defined vehicle functions for the vehicle.” fails to meaningfully limit the claim because it does not require any particular application of the recited “directing” and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements are “compute nodes in a vehicle”, “directing the one or more higher-performance compute nodes to execute the first processes to perform a first portion of the software-defined vehicle functions for the vehicle”, and “directing the one or more lower-performance compute nodes to execute the second processes to perform a second portion of the software-defined vehicle functions for the vehicle.” the mere use of generic computer to implement the abstract idea, as discussed above, which does not amount to significantly more, thus, not an inventive concept, and the courts have identified gathering data, storing data, and outputting the result is well-understood, routine and conventional activity (Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018)), thus, cannot amount to an inventive concept.. Accordingly, the claim does not appear to be patent eligible under 35 USC 101. See MPEP 2106.05(d).
Regarding claim 11, under prong 2, the “wherein the software-defined vehicle functions interact with vehicle components connected to the one or more higher-performance compute nodes and the one or more lower-performance compute nodes” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 12, the limitation “determining the second processes execute properly at a performance level of the one or more lower-performance compute nodes” is an additional metal process under prong 1.
Regarding claim 13, under prong 2, the “load balancing the second processes between the one or more lower-performance compute nodes” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 15, under prong 2, the “assigning” and “activating” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 16, the limitation “determining at least a portion of the first processes necessitate a performance level of the one or more higher-performance compute nodes” is an additional metal process under prong 1.
Regarding claim 17, the limitation “determining that a compute node of the one or more lower-performance compute nodes can no longer handle a process of the second processes” is an additional metal process under prong 1. Under prong 2, the “reassigning the process to a different compute node of the asymmetric distributed compute nodes” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Allowable Subject Matter
Claim 15 would be allowable if rewritten to overcome the rejection(s) under 101, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The prior art of record does not disclose and/or fairly suggest at least claimed limitations recited in such manners in dependent claim 15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10-12, 14, 16 and 18-20 are rejected under 35 U.S.C. 102(a1) as being anticipated by US 2019/0391846 to Kobayashi et al. (hereafter “Kobayashi”)
As per claim 10, Kobayashi discloses a method for providing software-defined vehicle functions via asymmetric distributed compute nodes (FIG. 1 and 5; paragraphs 0027, and 0049-0050: “As shown in FIG. 1, the semiconductor integrated circuit 100 is configured as an asymmetric multiple processor in which a plurality of CPUs having different data processing performances are mounted.” [Wingdings font/0xE0] big CPU and little CPU (asymmetric multiple processors) in a vehicle (FIG. 1; paragraphs 0027, 0066 and 0092: “the semiconductor integrated circuit 100 constitutes an in-vehicle information system.”), the method comprising:
identifying first processes (FIG. 1 and 3; paragraphs 0044-0045: “The governor 1 and the scheduler 4 may be executed in either the first CPU group 8 (big CPU) or the second CPU group 9 (Little CPU). Depending on the loading conditions of these CPUs, it may be decided whether to execute the governor 1 or the scheduler 4 in the big CPU or the Little CPU.”) for execution on one or more higher-performance compute nodes of the asymmetric distributed compute nodes (FIGs. 1-5; paragraphs 0029 and 0045: “Each of CPUs 8A, 8B, 8C, and 8D is a high-performance CPU.”);
identifying second processes for execution on one or more lower-performance compute nodes of the asymmetric distributed compute nodes (FIGs. 1-5; paragraphs 0029 and 0045: “Each of CPUs 8A, 8B, 8C, and 8D is a high-performance CPU.”) [Wingdings font/0xE0] LITTLE CPU).”);
directing the one or more higher-performance compute nodes to execute the first processes (FIG. 1 and 3; paragraphs 0044-0045: “The governor 1 and the scheduler 4 may be executed in either the first CPU group 8 (big CPU) or the second CPU group 9 (Little CPU). Depending on the loading conditions of these CPUs, it may be decided whether to execute the governor 1 or the scheduler 4 in the big CPU or the Little CPU.”) to perform a first portion of the software-defined vehicle functions for the vehicle (FIG. 1-5; paragraphs 0029, 0045, 0061 and 0065-0066: “These functional blocks are those that require high-performance CPUs (high processing performances). On the other hand, the SD host controller and the I 2 C controller are associated with the LITTLE CPU. These functional blocks are blocks that do not necessarily require high-performance CPUs (the performance of the entire system is less affected by the operation of tasks in the LITTLE CPU).”); and
directing the one or more lower-performance compute nodes to execute the second processes (FIG. 1 and 3; paragraphs 0044-0045: “The governor 1 and the scheduler 4 may be executed in either the first CPU group 8 (big CPU) or the second CPU group 9 (Little CPU). Depending on the loading conditions of these CPUs, it may be decided whether to execute the governor 1 or the scheduler 4 in the big CPU or the Little CPU.”) to perform a second portion of the software-defined vehicle functions for the vehicle (FIG. 1-5; paragraphs 0029, 0045, 0061 and 0065-0066: “These functional blocks are those that require high-performance CPUs (high processing performances). On the other hand, the SD host controller and the I 2 C controller are associated with the LITTLE CPU. These functional blocks are blocks that do not necessarily require high-performance CPUs (the performance of the entire system is less affected by the operation of tasks in the LITTLE CPU).”).
As per claim 11, Kobayashi discloses wherein the software-defined vehicle functions (FIG. 1; paragraphs 0027, 0066 and 0092: “the semiconductor integrated circuit 100 constitutes an in-vehicle information system.”) interact with vehicle components connected to the one or more higher-performance compute nodes and the one or more lower-performance compute nodes (FIG. 1-5; paragraphs 0029, 0045, 0061 and 0065-0066).
As per claim 12, Kobayashi discloses determining the second processes (FIG. 1 and 3; paragraphs 0044-0045: “The governor 1 and the scheduler 4 may be executed in either the first CPU group 8 (big CPU) or the second CPU group 9 (Little CPU). Depending on the loading conditions of these CPUs, it may be decided whether to execute the governor 1 or the scheduler 4 in the big CPU or the Little CPU.”) execute properly at a performance level of the one or more lower-performance compute nodes (FIG. 3; paragraphs 0045 and 0047: “On the other hand, the SD host controller and the I 2 C controller are associated with the LITTLE CPU. These functional blocks are blocks that do not necessarily require high-performance CPUs (the performance of the entire system is less affected by the operation of tasks in the LITTLE CPU).”).
As per claim 14, Kobayashi discloses wherein directing the one or more lower-performance compute nodes to execute the second processes comprises: assigning a process of the second processes (FIG. 1 and 3; paragraphs 0044-0045: “The governor 1 and the scheduler 4 may be executed in either the first CPU group 8 (big CPU) or the second CPU group 9 (Little CPU). Depending on the loading conditions of these CPUs, it may be decided whether to execute the governor 1 or the scheduler 4 in the big CPU or the Little CPU.”) to a compute node of the one or more lower-performance compute nodes connected to a vehicle component with which the process interacts (FIGs. 3-5; paragraphs 0044-0045 and 0047).
As per claim 16, Kobayashi discloses determining at least a portion of the first processes necessitate a performance level of the one or more higher-performance compute nodes (FIG. 3-5; paragraphs 0029, 0045, 0061 and 0065-0066: VCP, USB controller or GPU requires big CPU)
As per claim 18, Kobayashi discloses an apparatus to provide asymmetric distributed compute nodes (FIG. 1 and 5; paragraphs 0027, and 0049-0050: “As shown in FIG. 1, the semiconductor integrated circuit 100 is configured as an asymmetric multiple processor in which a plurality of CPUs having different data processing performances are mounted.” [Wingdings font/0xE0] big CPU and little CPU (asymmetric multiple processors) in a vehicle for software-defined vehicle functions (FIG. 1; paragraphs 0027, 0066 and 0092: “the semiconductor integrated circuit 100 constitutes an in-vehicle information system.”), the apparatus comprising:
one or more microprocessors, wherein the one or more microprocessors execute first processes (FIG. 1 and 3; paragraphs 0044-0045: “The governor 1 and the scheduler 4 may be executed in either the first CPU group 8 (big CPU) or the second CPU group 9 (Little CPU). Depending on the loading conditions of these CPUs, it may be decided whether to execute the governor 1 or the scheduler 4 in the big CPU or the Little CPU.”) for performing a first portion of the software-defined vehicle functions for the vehicle (FIG. 1-5; paragraphs 0029, 0045, 0061 and 0065-0066: “These functional blocks are those that require high-performance CPUs (high processing performances). On the other hand, the SD host controller and the I 2 C controller are associated with the LITTLE CPU. These functional blocks are blocks that do not necessarily require high-performance CPUs (the performance of the entire system is less affected by the operation of tasks in the LITTLE CPU).”);
input and output interfaces connected to vehicle components of the vehicle (FIG. 1; paragraphs 0027, 0066 and 0092); and
a network interface connected to a communication backbone to communicate with other compute nodes of the asymmetric distributed compute nodes (FIG. 1; paragraphs 0027, 0066 and 0092);
wherein the other compute nodes execute second processes (FIG. 1 and 3; paragraphs 0044-0045: “The governor 1 and the scheduler 4 may be executed in either the first CPU group 8 (big CPU) or the second CPU group 9 (Little CPU). Depending on the loading conditions of these CPUs, it may be decided whether to execute the governor 1 or the scheduler 4 in the big CPU or the Little CPU.”)” for performing a second portion of the software-defined vehicle functions for the vehicle (FIG. 1-5; paragraphs 0029, 0044-0045, 0061 and 0065-0066: “These functional blocks are those that require high-performance CPUs (high processing performances). On the other hand, the SD host controller and the I 2 C controller are associated with the LITTLE CPU. These functional blocks are blocks that do not necessarily require high-performance CPUs (the performance of the entire system is less affected by the operation of tasks in the LITTLE CPU).”).
As per claim 19, Kobayashi discloses wherein the one or more microprocessors have a lower level of performance than microprocessors of at least one of the other compute nodes (FIG. 1 and 5; paragraphs 0027, and 0049-0050: “As shown in FIG. 1, the semiconductor integrated circuit 100 is configured as an asymmetric multiple processor in which a plurality of CPUs having different data processing performances are mounted.” [Wingdings font/0xE0] big CPU (high performance cpu) and little CPU (low performance cpu))
As per claim 20, Kobayashi discloses wherein a process of the first processes directs the one or more microprocessors (FIG. 1 and 3; paragraphs 0044-0045: “The governor 1 and the scheduler 4 may be executed in either the first CPU group 8 (big CPU) or the second CPU group 9 (Little CPU). Depending on the loading conditions of these CPUs, it may be decided whether to execute the governor 1 or the scheduler 4 in the big CPU or the Little CPU.”) to interact with a vehicle component of the vehicle components (FIG. 1 and 3; paragraphs 0044-0045: VCP, USP controller or GPU).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0391846 to Kobayashi et al. (hereafter “Kobayashi”) in further view of US 2018/0373078 to Mizuno.
As per claim 1, Kobayashi discloses a system to provide asymmetric distributed compute nodes (FIG. 1 and 5; paragraphs 0027, and 0049-0050: “As shown in FIG. 1, the semiconductor integrated circuit 100 is configured as an asymmetric multiple processor in which a plurality of CPUs having different data processing performances are mounted.” [Wingdings font/0xE0] big CPU and little CPU (asymmetric multiple processors) in a vehicle for software-defined vehicle functions (FIG. 1; paragraphs 0027, 0066 and 0092: “the semiconductor integrated circuit 100 constitutes an in-vehicle information system.”), the system comprising:
one or more higher-performance compute nodes of the asymmetric distributed compute nodes (FIGs. 1-5; paragraphs 0029 and 0045: “Each of CPUs 8A, 8B, 8C, and 8D is a high-performance CPU.”);
one or more lower-performance compute nodes of the asymmetric distributed compute nodes (FIG. 1-5; paragraphs 0029 and 0045: “The second CPU group 9 includes CPUs 9A, 9B, 9C, and 9D denoted by “CPU0”, “CPU1”, “CPU2”, and “CPU3”, respectively. Each of CPUs 9A, 9B, 9C, and 9D is a low-performance CPU.”); and
wherein the one or more higher-performance compute nodes execute first processes (FIG. 1 and 3; paragraphs 0044-0045: “The governor 1 and the scheduler 4 may be executed in either the first CPU group 8 (big CPU) or the second CPU group 9 (Little CPU). Depending on the loading conditions of these CPUs, it may be decided whether to execute the governor 1 or the scheduler 4 in the big CPU or the Little CPU.”) for performing a first portion of the software-defined vehicle functions for the vehicle (FIG. 1-5; paragraphs 0029, 0045, 0061 and 0065-0066: “These functional blocks are those that require high-performance CPUs (high processing performances). On the other hand, the SD host controller and the I 2 C controller are associated with the LITTLE CPU. These functional blocks are blocks that do not necessarily require high-performance CPUs (the performance of the entire system is less affected by the operation of tasks in the LITTLE CPU).”);
wherein the one or more lower-performance compute nodes execute second processes (FIG. 1 and 3; paragraphs 0044-0045: “The governor 1 and the scheduler 4 may be executed in either the first CPU group 8 (big CPU) or the second CPU group 9 (Little CPU). Depending on the loading conditions of these CPUs, it may be decided whether to execute the governor 1 or the scheduler 4 in the big CPU or the Little CPU.”) for performing a second portion of the software-defined vehicle functions for the vehicle (FIG. 1-5; paragraphs 0029, 0045, 0061 and 0065-0066: “These functional blocks are those that require high-performance CPUs (high processing performances). On the other hand, the SD host controller and the I 2 C controller are associated with the LITTLE CPU. These functional blocks are blocks that do not necessarily require high-performance CPUs (the performance of the entire system is less affected by the operation of tasks in the LITTLE CPU).”).
Kobayashi does not explicitly disclose a communication backbone over which the higher-performance compute nodes and the lower-performance compute nodes communicate.
Mizuno further discloses a communication backbone over which the higher-performance compute nodes and the lower-performance compute nodes communicate (FIG. 1; paragraph 0058: “the processor 100 and the processor 200 may include a communication interface section (hereinafter abbreviated as “communication I/F section”) which transmits and receives various data and signals by a predetermined communication scheme using a wire or wirelessly between the electronic device where the display device 10 is mounted and a device provided outside (hereinafter referred to as an “external device”)” [Wingdings font/0xE0] high performance processor 100 connecting low processor 200).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Mizuno into Kobayashi’s teaching because it would provide for the purpose of the processor 200 includes a cooperative communication section 250 having a structure equivalent to that of the cooperative communication section 150 provided to the above-described processor 100, and transmits and receives a predetermined cooperative signal to and from the processor 100 described above, thereby controlling at least a display status of the display section 300 in cooperation and synchronization with the processor 100 (Mizuno, paragraph 0035).
As per claim 2, Kobayashi discloses wherein the one or more higher-performance compute nodes and the one or more lower-performance compute nodes include input and output interfaces for interacting with vehicle components (FIG. 1; paragraphs 0030-0031: “The CPUs 8A to 8D of the first CPU group 8 and the CPUs 9A to 9D of the second CPU group 9 are connected to a memory 11, an input/output (I/O) circuit 12, and a functional block group 13 via a bus 10.”).
As per claim 3, Kobayashi discloses a zonal gateway connected to the communication backbone, wherein a vehicle component is connected to the zonal gateway (in view of paragraph 0043 of the instant specification, zonal gate way is lower-performance nodes Kobayashi FIG. 1-5; paragraphs 0030-0031 teaches little CPU as zonal gate connecting to other components in the vehicle through connections buses 10, 14 and 15);
wherein one of the first or second processes controls the vehicle component over the communication backbone via the zonal gateway (FIG. 1-5; paragraphs 0030-0031).
As per claim 4, Kobayashi discloses wherein the first processes and the second processes are configured to execute on a processing architecture shared by the one or more higher-performance compute nodes and the one or more lower-performance compute nodes (FIG. 1; “The semiconductor integrated circuit 100 includes a first CPU group (big CPU) 8 having high data processing performance and high-power consumption, and a second CPU group (LITTLE CPU) 9 having low data processing performance and low-power consumption.”).
As per claim 6, Kobayashi does not explicitly disclose wherein the one or more lower-performance compute nodes are located remotely in the vehicle from the one or more higher-performance compute nodes.
Mizuno further discloses wherein the one or more lower-performance compute nodes are located remotely in the vehicle from the one or more higher-performance compute nodes (FIG. 1; paragraphs 0036 and 0057-0058: “Note that although the processor 100 and the processor 200 are depicted as separate structures in the present embodiment as depicted in FIG. 1” [Wingdings font/0xE0] since processor 100 is separated from the processor 200, they are connected remotely).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Mizuno into Kobayashi’s teaching because it would provide for the purpose of the processor 200 includes a cooperative communication section 250 having a structure equivalent to that of the cooperative communication section 150 provided to the above-described processor 100, and transmits and receives a predetermined cooperative signal to and from the processor 100 described above, thereby controlling at least a display status of the display section 300 in cooperation and synchronization with the processor 100 (Mizuno, paragraph 0035).
As per claim 9, Kobayashi discloses wherein a first compute node of the one or more lower-performance compute nodes controls a vehicle component (FIGs. 1 and 3; paragraphs 0045 and 0059: “On the other hand, the SD host controller and the I 2 C controller are associated with the LITTLE CPU.”) connected thereto in response to an instruction received over the communication backbone (FIGs. 1; paragraphs 0028-0030).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in further view of Mizuno, as applied to claim 1, and further in view of US 2010/0011085 to Taguchi et al. (hereafter “Taguchi”)
As per claim 5, Kobayashi in view of Mizuno does not explicitly disclose wherein the first processes and the second processes are load balanced across the one or more higher-performance compute nodes and the one or more lower-performance compute nodes.
Taguchi further discloses wherein the first processes and the second processes are load balanced across the one or more higher-performance compute nodes and the one or more lower-performance compute nodes (paragraph 0160: “Then, the balance between the performance and the load is improved by coupling the light-load volume 4 to the low-performance data archiving server 300B and coupling the heavy-load volume 3 to the high-performance data archiving server 300C.”)
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Taguchi into Kobayashi’s teaching and Mizuno’s teaching because it would provide for the purpose of the configuration of a data archiving system can be managed in a manner that improves the balance between the performance of computers and the load on storage subsystems (Taguchi, paragraph 0015).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in further view of Mizuno, as applied to claim 6, and further in view of US 2006/0094350 to Ishimura et al. (hereafter “Ishimura”)
As per claim 7, Kobayashi discloses a plurality of computing nodes are lower-performance nodes (FIGs. 1-5; paragraphs 0029 and 0045: “Each of CPUs 8A, 8B, 8C, and 8D is a high-performance CPU.”), however, Kobayashi does not explicitly disclose wherein a first compute node of the one or more compute nodes is physically located closer to vehicle components connected thereto than a second compute node of the one or more compute nodes.
Ishimura further discloses wherein a first compute node of the one or more compute nodes is physically located closer to vehicle components connected thereto than a second compute node of the one or more compute nodes (FIG. 1 and 6; paragraph 0078).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Ishimura into Kobayashi’s teaching and Mizuno’s teaching because it would provide for the purpose of a communication device which can communicate with a partner communication device, the partner communication device having a plurality of distance-calculation communication devices that each transmits a distance-calculation signal to calculate distance (Ihsimura, paragraph 0021).
As per claim 8, Kobayashi discloses wherein a process of the second processes is executing on the first compute node to interact with one or more of the vehicle components (FIG. 1-5; paragraphs 0029, 0045, 0061 and 0065-0066).
Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi further in view of US 2021/0144517 to Guim Bernat et al. (hereafter “Guim”)
As per claim 13, Kobayashi does not explicitly disclose wherein directing the one or more lower-performance compute nodes to execute the second processes comprises: load balancing the second processes between the one or more lower-performance compute nodes.
Guim further discloses wherein directing the one or more lower-performance compute nodes to execute the second processes comprises: load balancing the second processes between the one or more lower-performance compute nodes (paragraph 0947: “Thus, if the power budget configuration specifies a low-performance requirement with a low power budget, the load balancer will prefer a low-power compute element over a high-power compute element.”)
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Guim into Kobayashi’s teaching because it would provide for the purpose of load balance to the low performance element to meet a low power budget (Guim, paragraph 0947).
Claims 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi further in view of US 2024/0027996 to Yang.
As per claim 17, Kobayashi does not explicitly disclose determining that a compute node of the one or more lower-performance compute nodes can no longer handle a process of the second processes; and reassigning the process to a different compute node of the asymmetric distributed compute nodes.
Yang further discloses determining that a compute node of the one or more lower-performance compute nodes can no longer handle a process of the second processes (paragraphs 0256-0257); and
reassigning the process to a different compute node of the asymmetric distributed compute nodes (paragraphs 0256-0257).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Yang into Kobayashi’s teaching because it would provide for the purpose of tracking a worker yield percentage of the worker, wherein the worker yield percentage is calculated based on an amount of failed jobs and an amount of completed jobs assigned to the worker (Yang, paragraph 0017).
Conclusion
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Prior arts:
US 2009/0193243 to Ely
For further supporting the cooperation of the operating system of both sub-systems, at least one communication link 190 (IP link) interconnects the high-performance subsystem HP with the low-performance subsystem LP. This communication link 190 can provide a connection from the low-performance subsystem LP to the high-performance HP subsystem.
US 2005/0223574 to Fillatreau
the processor module selected the PL.sub.2 location rather than the PL.sub.1 location because the PL.sub.2 location is closer to the reference point R.sub.1B.sub.3 of the B.sub.3 magnetic field data point (i.e. the previous reference point).
US 2004/0243709 to Kalyanavarathan
these additional requests are sent to the selected node 110A-H if the selected node is active. If the selected node is inactive, a lower-level load balancer 400B-D may assign the additional requests to another node in the same cluster 120A-C as the selected node.
US 2004/0066745 to Joe
if a node becomes an inactive node, the embodiments may automatically redistribute the work accordingly. Once the inactive node becomes an active node again, the embodiments may automatically redistribute the work to include the new active node. In addition, the embodiments move the load balancing work to layer 2 of the protocol stack. This not only provides increased flexibility and efficiency for distributing work among multiple nodes, but also provides additional processing cycles by moving this functionality from higher layers. These additional processing cycles may be dedicated to other tasks, e.g., processing packets in accordance with their primary function.
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/TUAN C DAO/ Primary Examiner, Art Unit 2198