Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18364240 filed on 08/02/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of claims 1-9 in the reply filed on 12/09/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Polishchuck et al. (US 2020/0013863) in view of Pillarisetty et al. (US 2015/0091067).
Regarding independent claim 1, Polishchuck et al. teach a synapse device (this is an intended use recitation that does not structurally distinguish over prior art) comprising:
a channel member (Fig. 3, element 312, paragraph 0051);
a tunnel insulating layer (Fig. 3, element 316, paragraph 0051) disposed on the channel member;
a charge trap layer (Fig. 3, elements 318A & 318B, paragraph 0051) disposed on the tunnel insulating layer;
a blocking insulating layer (Fig. 3, element 320, paragraph 0051) disposed on the charge trap layer;
a gate electrode (Fig. 3, element 308, paragraph 0051) disposed on the blocking insulating layer;
a first terminal (Fig. 3, element 314, paragraph 0051) and a second terminal (Fig. 3, element 314, paragraph 0051) respectively connected to first and second regions of the channel member; and
wherein the charge trap layer has a multilayer structure including a first trap layer (Fig. 3, element 318B, paragraph 0051) disposed adjacent to the channel member and a second trap layer (Fig. 3, element 318A, paragraph 0051) disposed adjacent to the gate electrode, and wherein the first trap layer has a trap of a shallower level than that of the second trap layer (paragraph 0051 discloses 318B substantially trap free).
Polishchuck et al. do not explicitly disclose first and second conductors respectively bonded to the first and second terminals.
Pillarisetty et al. teach a semiconductor device comprising first and second conductors (Fig. 6, elements 115 & 109, paragraph 0060) respectively bonded to the first and second terminals (Fig. 6, source and drain regions 105 & 106, paragraph 0060).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Polishchuck et al. according to the teachings of Pillarisetty et al. with the motivation to provide interconnection.
Regarding claim 2, Polishchuck et al. teach wherein the first trap layer is a first silicon nitride layer, and the second trap layer is a second silicon nitride layer different from the first silicon nitride layer (paragraph 0051, 0034, 0035).
Regarding claim 7, Polishchuck et al. teach wherein the first trap layer has a smaller energy bandgap than that of the second trap layer (paragraph 0035 discloses that the bandgap can be adjusted by the gas flow process to improve data retention. Accordingly, the band gap is an art recognized optimizable parameter. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, and arrive at the claimed bandgap. Furthermore, the applicant has not presented persuasive evidence that the claimed bandgap is for a particular purpose that is critical to the overall claimed invention.
Regarding claim 8, Polishchuck et al. modified by Pillarisetty et al. teach wherein the first terminal is a source and the second terminal is a drain (paragraph 0051 of Polishchuck discloses semiconductor source and drain region), and wherein the source and the first conductor form a Schottky junction, and the drain and the second conductor form a Schottky junction (paragraph 0060 of Pillarisetty discloses the conductors are formed of metal, accordingly the metal/semiconductor interface would be a Schottky junction).
Regarding claim 9, Polishchuck et al. modified by Pillarisetty et al. teach wherein each of the source and the drain has a doping concentration of 1×10.sup.16 to 2×10.sup.18 atoms/cm.sup.3 (paragraph 0036 of Pillarisetty et al. discloses a range of doping concentration for the source and drain region and additionally discloses “In an embodiment, the doping concentration and profile of the source and drain regions can vary in to obtain a particular electrical characteristic”. Accordingly, the doping concentration is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the arrive at the claimed doping concentration).
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Polishchuck et al. (US 2020/0013863) in view of Pillarisetty et al. (US 2015/0091067) and further in view of Jin et al. (CN 108899273 A).
Regarding claim 3, Polishchuck et al. modified by Pillarisetty et al. teach all the limitations as discussed above.
Polishchuck et al. teach the first and second charge trapping layer comprising silicon nitride (paragraph 0051).
Polishchuck et al. do not explicitly disclose wherein the first silicon nitride layer is a silicon (Si)-rich silicon nitride layer, and the second silicon nitride layer is a silicon nitride layer having a higher nitrogen (N) content than the first silicon nitride layer.
Jin et al. teach a semiconductor device comprising a multilayer charge trapping element 124 wherein “In another embodiment shown in FIG. 3C, charge-trapping layer 124 comprises a lower layer, a middle layer and an upper layer. In an embodiment, lower layer 124A 'is oxygen-rich, middle layer 124C' is silicon-rich, and the upper layer 124B is silicon-rich and/or rich nitrogen”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Polishchuck et al. and Pillarisetty et al. according to the teachings of Jin et al. with the motivation to form a “grid electrode dielectric layer”.
Regarding claim 4, Polishchuck et al. modified by Pillarisetty et al. and Jin et al. teach wherein the second silicon nitride layer includes silicon nitride having a stoichiometric composition, or N-rich silicon nitride, or both (Jin et al. teach “In another embodiment shown in FIG. 3C, charge-trapping layer 124 comprises a lower layer, a middle layer and an upper layer. In an embodiment, lower layer 124A 'is oxygen-rich, middle layer 124C' is silicon-rich, and the upper layer 124B is silicon-rich and/or rich nitrogen. In an embodiment, lower layer 124A includes silicon oxynitride middle layer 124C ' comprises oxynitride, and the upper layer 124B comprises silicon oxynitride or Si3N4. In an embodiment, lower layer 124A ' according to atom percentage comprises 30% +/ - 5%, 20% +/ - 10% of nitrogen, and 50% + 10%. In an embodiment, the middle layer 124C ' according to atom percentage comprises 5% +/ - 2%, 40% +/ - 10% of nitrogen, and 55% +/-10 % of silicon. In an embodiment, the upper layer 124B ' comprises 0-7 % oxygen, 30-57 % nitrogen, and 43-65 % of silicon by atom percentage”).
Regarding claim 5, Polishchuck et al. modified by Pillarisetty et al. and Jin et al. teach wherein the first silicon nitride layer has a silicon (Si) content in a range from about 43 at % to about 86 at % (Jin et al. teach “In another embodiment shown in FIG. 3C, charge-trapping layer 124 comprises a lower layer, a middle layer and an upper layer. In an embodiment, lower layer 124A 'is oxygen-rich, middle layer 124C' is silicon-rich, and the upper layer 124B is silicon-rich and/or rich nitrogen. In an embodiment, lower layer 124A includes silicon oxynitride middle layer 124C ' comprises oxynitride, and the upper layer 124B comprises silicon oxynitride or Si3N4. In an embodiment, lower layer 124A ' according to atom percentage comprises 30% +/ - 5%, 20% +/ - 10% of nitrogen, and 50% + 10%. In an embodiment, the middle layer 124C ' according to atom percentage comprises 5% +/ - 2%, 40% +/ - 10% of nitrogen, and 55% +/-10 % of silicon. In an embodiment, the upper layer 124B ' comprises 0-7 % oxygen, 30-57 % nitrogen, and 43-65 % of silicon by atom percentage”. Accordingly, it would be obvious to one of ordinary skill in the art before the effective filling date of the invention to choose silicon (Si) content in a range from about 43 at % to about 86 at % as shown by Jin. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05).
Regarding claim 6, Polishchuck et al. modified by Pillarisetty et al. and Jin et al. teach wherein the second silicon nitride layer has a silicon (Si) content in a range from about 14 at % to about 43 at % (Jin et al. teach “In another embodiment shown in FIG. 3C, charge-trapping layer 124 comprises a lower layer, a middle layer and an upper layer. In an embodiment, lower layer 124A 'is oxygen-rich, middle layer 124C' is silicon-rich, and the upper layer 124B is silicon-rich and/or rich nitrogen. In an embodiment, lower layer 124A includes silicon oxynitride middle layer 124C ' comprises oxynitride, and the upper layer 124B comprises silicon oxynitride or Si3N4. In an embodiment, lower layer 124A ' according to atom percentage comprises 30% +/ - 5%, 20% +/ - 10% of nitrogen, and 50% + 10%. In an embodiment, the middle layer 124C ' according to atom percentage comprises 5% +/ - 2%, 40% +/ - 10% of nitrogen, and 55% +/-10 % of silicon. In an embodiment, the upper layer 124B ' comprises 0-7 % oxygen, 30-57 % nitrogen, and 43-65 % of silicon by atom percentage”. Accordingly, it would be obvious to one of ordinary skill in the art before the effective filling date of the invention to choose silicon (Si) content in a range from about 14 at % to about 43 at % as shown by Jin. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05).
Conclusion
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813