Prosecution Insights
Last updated: May 29, 2026
Application No. 18/364,262

CHIP PACKAGE STRUCTURE AND FABRICATION

Non-Final OA §102§103
Filed
Aug 02, 2023
Priority
May 05, 2023 — CN 2023104987647
Examiner
PARVEZ, AZM A
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co. Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
507 granted / 647 resolved
+10.4% vs TC avg
Strong +27% interview lift
Without
With
+27.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
14 currently pending
Career history
658
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
68.4%
+28.4% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
14.4%
-25.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 647 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 1-13 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/05/2025. Applicant’s election without traverse of Claims 14-20 in the reply filed on 12/05/2025 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Engelhardt, US 2014/0153193. Regarding claim 14, Engelhardt discloses; a chip package structure, comprising: a substrate (Fig. 1-2 and [0009]; PCB 12); a chip (Fig. 1-2 and [0009]; heat producing components 14, shown as microprocessors) on a side of the substrate; an energy storage material layer (Fig. 1-2 and [0015]; phase change material 36) on a side of the chip opposite the substrate; and a package layer comprising a first portion (Fig. 1-2 and [0010]; thermal planes 24 & attached Fig. 1 below) covering the chip and a second portion (Fig. 1-2 and [0010]; thermal planes 24 & attached Fig. 1 below) covering the energy storage material layer. PNG media_image1.png 667 945 media_image1.png Greyscale Regarding claim 15, Engelhardt discloses; a material of the first portion covering the chip is the same as a material of the second portion covering the energy storage material layer (Fig. 1-2 and [0010]; thermal planes 24 are illustrated as aluminum & attached Fig. 1 above). Regarding claim 16, Engelhardt discloses; the chip package structure further comprises a first heat conduction support frame (Fig. 1-2 and [0010]; thermal pads 22) connected between the chip and the energy storage material layer. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Engelhardt, US 2014/0153193 as applied to claims 14-16 above, and further in view of Uppal, US 2020/0219790. Regarding claim 17 and 19, Engelhardt substantially discloses the invention that material of the first portion covering the chip and the material of the second portion covering the energy storage material layer is illustrated as aluminum, alternately, may comprise any material able to efficiently conduct or dissipate heat (Fig. 1-2 and [0010]; attached Fig. 1 above) but specifically silent about a material of the first portion covering the chip is different from a material of the second portion covering the energy storage material layer in claim 17 and the material of the first portion covering the chip comprises epoxy resin in claim 19. However, Uppal teaches that a mold material 180 may be formed over the first integrated circuit device 120 as the phase change material layer 170 may be disposed on the first surface 182 of the mold material 180 (Fig. 4-6 and [0047]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Engelhardt by providing a material of the first portion covering the chip is different from a material of the second portion covering the energy storage material layer in claim 17 and the material of the first portion covering the chip comprises epoxy resin in claim 19, so that the phase change material layer may increase the thermal capacitance (thermal energy storage) of the integrated circuit assembly, which may allow for thermal performance regardless of high power densities and turbo boosting ([0050]). Regarding claim 18, Engelhardt discloses; the first portion covering the chip comprises a groove (Fig. 1-2 and [0016]; attached Fig.1 above; chambers 35) that is located on a side of the first portion covering the chip opposite the substrate, and the energy storage material layer (Fig. 1-2; [0015] and attached Fig.1 above; phase change material 36 is filled within the groove) is filled within the groove; wherein the second portion covering the energy storage material layer comprises a second heat conduction support frame that comprises a support sub-portion (Fig. 1-2; [0015] and attached Fig.1 above; the frame 34 is illustrated as a grid of interconnected walls) and a cover plate sub-portion (Fig. 1-2; [0015] and attached Fig.1), wherein the support sub-portion extends (Fig. 1-2; [0015] and attached Fig.1 above; the frame 34 extends into phase change material 36) into the energy storage material layer, and the cover plate sub-portion is connected to an end of the support sub-portion opposite the chip and covers at least part of the energy storage material layer (Fig. 1-2; [0015] and attached Fig.1 above; the frame 34 connected to second portion, covering the phase change material 36). Regarding claim 20, Engelhardt discloses; the chip package structure further comprises a sealant (Fig. 1-2; [0015] and attached Fig.1 above; the inner wall 32 is exemplified as an elastomer material for retaining the phase change material 36) filled between the cover plate sub-portion and a sidewall of the groove. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW RICHARDS can be reached at (571)272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AZM PARVEZ/ Examiner Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Aug 02, 2023
Application Filed
May 06, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+27.0%)
3y 1m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 647 resolved cases by this examiner. Grant probability derived from career allowance rate.

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