DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/24/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 10-11, 13-14, 16, 19-20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0104091 to Tanaka in view of Joh et al. (US Patent No. 9,882,041, hereinafter Joh).
With respect to claim 1, Tanaka discloses a nitride semiconductor device (e.g., high electron mobility transistor (HEMT)) (Tanaka, Fig. 11, ¶0002, ¶0011-¶0025, ¶0048-¶0064, ¶0160-¶0168), comprising:
an electron transit layer (e.g., 4) (Tanaka, Fig. 11, ¶0053, ¶0055) composed of a nitride semiconductor (e.g., GaN);
an electron supply layer (e.g., 5/6) (Tanaka, Fig. 11, ¶0054-¶0056) formed on the electron transit layer (4), the electron supply layer (5/6) being composed of a nitride semiconductor (e.g., AlGaN) having a band gap that is larger than that of the electron transit layer (4);
a gate layer (7) (Tanaka, Fig. 11, ¶0058) formed on the electron supply layer (5/6), the gate layer (7) being composed of a nitride semiconductor including an acceptor impurity (e.g., p-type doped GaN);
a gate electrode (8) (Tanaka, Fig. 11, ¶0059) formed on the gate layer (7);
an insulation layer (14/9) (Tanaka, Fig. 11, ¶0060, ¶0161) covering the electron supply layer (5/6), the gate layer (7), and the gate electrode (8) and including a first opening (e.g., a recess 11a for the source electrode/contact 11) (Tanaka, Fig. 11, ¶0060, ¶0062, ¶0161) and a second opening (e.g., a recess 12a for the drain electrode/contact 12);
a source electrode (11) (Tanaka, Fig. 11, ¶0062, ¶0161) in contact with the electron supply layer (5/6) through the first opening (11a); and
a drain electrode (12) (Tanaka, Fig. 11, ¶0062, ¶0161) in contact with the electron supply layer (5/6) through the second opening (12a), wherein
the gate layer (7) is located between the first opening (e.g., 11a) (Tanaka, Fig. 11, ¶0058, ¶0060, ¶0062) and the second opening (e.g., 12a),
the source electrode (11) includes a source field plate (e.g., the source electrode 11 extending over the gate electrode 8 toward the drain electrode 12) (Tanaka, Fig. 11, ¶0062, ¶0073, ¶0161) covering the insulation layer (14/9),
the source field plate (11) includes an end located between the second opening (e.g., 12a) and the gate layer (7) (Tanaka, Fig. 11, ¶0062, ¶0073, ¶0161),
the insulation layer (14/9) includes
a first insulation layer part (e.g., passivation layer 9, SiN) (Tanaka, Fig. 11, ¶0060, ¶0161) that is disposed on the electron supply layer (5/6) in contact with the drain electrode (e.g., 12) and has a first thickness (e.g., a thickness of the passivation layer 9 is about 100 nm) (Tanaka, Fig. 11, ¶0060, ¶0161), and
a second insulation layer part (e.g., a dielectric layer 14, SiO2 and a portion of the SiN layer 9 over the gate electrode 8) (Tanaka, Fig. 11, ¶0161) that is disposed on the gate electrode (8) in contact with the source field plate (11) and has a second thickness (e.g., including a thickness of the SiN layer 9 and a thickness of the SiO2 dielectric layer 14 above the gate electrode 8),
the end of the source field plate (11) is disposed on the first insulation layer part (e.g., 9) (Tanaka, Fig. 11, ¶0161),
the second thickness (e.g., including a thickness of the SiN layer 9 and a thickness of the SiO2 dielectric layer 14 above the gate electrode 8) (Tanaka, Fig. 11, ¶0060, ¶0161) of the second insulation layer part (14/9) is greater than the first thickness of the first insulation layer part (e.g., 9).
Further, Tanaka does not specifically disclose that the source field plate includes an end located between the second opening and the gate layer in a plan view, and the source electrode entirely surrounds the drain electrode in the plan view.
However, Joh teaches forming a high electron mobility transistor (HEMT) (Joh, Figs. 1C, 2, 3B-3D, Col. 1, lines 7-9, lines 37-41; lines 50-61; Col. 3, lines 10-67; Col. 4, lines 15-67; Col. 5, lines 1-23; lines 34-67; Col. 6, lines 1-24) having a drain centered layout where the high voltage drain area is completely enclosed by the gate and the source, to provide leakage current control and device isolation, and thus to improve device robustness and reliability. In Joh, the drain (120) is completely enclosed by both the gate (114) and the source (122), and there is electrical isolation (Joh, Figs. 1C, 2, 3B-3D, Col. 5, lines 3-8) between the metal providing the gate (114) and the source (122), wherein a dielectric layer is provided over the metal of the gate (114), and the metal of the source (122) is on top of the dielectric layer on the gate metal to form field plates, such that the source (122) including field plates has an end located between the drain (120) and the gate (114) in a plan view (e.g., Figs. 2, 3B-3D).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the nitride semiconductor device of Tanaka by forming HEMT transistor having a drain centered layout, and including the source completely enclosing the gate and having field plates as taught by Joh to have the nitride semiconductor device, wherein the source field plate includes an end located between the second opening and the gate layer in a plan view, and the source electrode entirely surrounds the drain electrode in the plan view, in order to provide leakage current control and device isolation, and thus to improve device robustness and reliability (Joh, Col. 1, lines 7-9, lines 37-41; lines 50-61; Col. 5, lines 3-8; Col. 6, lines 20-23).
Regarding claim 4, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 1. Further, Tanaka discloses the nitride semiconductor device, wherein the insulation layer (14/9) includes a spacer layer (e.g., dielectric layer 14 over the gate electrode 8) (Tanaka, Fig. 11, ¶0161) formed on the gate electrode (8), and a passivation layer (e.g., 9) covering the electron supply layer (5/6), the gate layer (7), the gate electrode (8), and the spacer layer (e.g., 14) and including the first opening (11a) (Tanaka, Fig. 11, ¶0060) and the second opening (12a), the first insulation layer part (e.g., 9) is formed of the passivation layer, and the second insulation layer part (14/9) is formed of the spacer layer (e.g., 14) and the passivation layer (e.g., the passivation layer 9 over the gate 8).
Regarding claim 5, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 4. Further, Tanaka discloses the nitride semiconductor device, wherein in the first insulation layer part, the passivation layer (e.g., a thickness of the passivation layer 9 between the gate 8 and the drain 12) (Tanaka, Fig. 11, ¶0060, ¶0161) has the first thickness, in the second insulation layer part (14/9), the spacer layer (e.g., 14) has a third thickness, and the passivation layer (e.g., 9) has a fourth thickness (e.g., a thickness of the passivation layer 9 over the gate electrode 8), and the second thickness (e.g., a thickness of the insulation layer 14/9) is a sum of the third thickness and the fourth thickness.
Regarding claim 6, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 5. Further, Tanaka discloses that the first thickness (e.g., a thickness of the passivation layer 9 between the gate 8 and the drain 12) is substantially equal to the fourth thickness (e.g., a thickness of the passivation layer 9 over the gate electrode 8).
Regarding claim 7, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 4. Further, Tanaka discloses the nitride semiconductor device, wherein the spacer layer (e.g., 14) (Tanaka, Fig. 11, ¶0161) is composed of any one (e.g., SiO2) of SiN, SiO2, SiON, Al2O3, AlN, and AlON.
Regarding claim 10, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 4. Further, Tanaka discloses that the spacer layer (14, SiO2) (Tanaka, Fig. 11, ¶0161) is composed of a material having a lower electric permittivity than a material of the passivation layer (9, SiN) (Tanaka, Fig. 11, ¶0060).
Regarding claim 11, Tanaka n view of Joh discloses the nitride semiconductor device according to claim 4. Further, Tanaka discloses the nitride semiconductor device, wherein the gate electrode (8) (Tanaka, Fig. 11, ¶0161, ¶0059) includes a first surface (e.g., a bottom surface) in contact with the gate layer (7) and a second surface (e.g., a top surface) opposite to the first surface, and the spacer layer (14) is formed on a portion of the second surface (e.g., the top surface) of the gate electrode (8).
Regarding claim 13, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 1. Further, Tanaka discloses the nitride semiconductor device, wherein the insulating layer (14/9) is a passivation layer (e.g., includes passivation layer 9) (Tanaka, Fig. 11, ¶0161, ¶0060), and each of the first insulation layer part (e.g., 9) and the second insulation layer part (14/9) is formed of the passivation layer.
Regarding claim 14, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 4. Further, Tanaka discloses the nitride semiconductor device, wherein the passivation layer (e.g., 9) (Tanaka, Fig. 11, ¶0060) is composed of any one (e.g., SiN) of SiN, SiO2, SiON, Al2O3, AlN, and AlON.
With respect to claim 16, Tanaka discloses a method for manufacturing a nitride semiconductor device (e.g., forming a high electron mobility transistor (HEMT)) (Tanaka, Figs. 2A-2G, 11, ¶0002, ¶0011-¶0025, ¶0048-¶0064, ¶0065-¶0074, ¶0160-¶0168), the method comprising:
forming an electron transit layer (e.g., 4) (Tanaka, Figs. 2A, 11, ¶0053, ¶0055, ¶0066) composed of a nitride semiconductor (e.g., GaN);
forming an electron supply layer (e.g., 5/6) (Tanaka, Figs. 2A, 11, ¶0054-¶0056, ¶0066) on the electron transit layer (4), the electron supply layer (5/6) being composed of a nitride semiconductor (e.g., AlGaN) having a band gap that is larger than that of the electron transit layer (4);
forming a gate layer (7) (Tanaka, Figs. 2A, 11, ¶0058, ¶0066) on the electron supply layer (5/6), the gate layer (7) being composed of a nitride semiconductor including an acceptor impurity (e.g., p-type doped GaN);
forming a gate electrode (8) (Tanaka, Figs. 2B-2C, 11, ¶0059, ¶0067-¶0069) on the gate layer (7);
forming an insulation layer (14/9) (Tanaka, Figs. 2D, 11, ¶0060, ¶0070, ¶0161) that covers the electron supply layer (5/6), the gate layer (7), and the gate electrode (8) and includes a first opening (e.g., a recess 11a for the source electrode/contact 11) (Tanaka, Figs. 2E, 11, ¶0060, ¶0062, ¶0071, ¶0161) and a second opening (e.g., a recess 12a for the drain electrode/contact 12);
forming a source electrode (11) (Tanaka, Figs. 2E, 11, ¶0062, ¶0072, ¶0161) that is in contact with the electron supply layer (5/6) through the first opening (11a); and
forming a drain electrode (12) (Tanaka, Figs. 2E, 11, ¶0062, ¶0072, ¶0161) that is in contact with the electron supply layer (5/6) through the second opening (12a), wherein
the gate layer (7) is located between the first opening (e.g., 11a) (Tanaka, Fig. 11, ¶0058, ¶0060, ¶0062, ¶0071) and the second opening (e.g., 12a),
the source electrode (11) includes a source field plate (e.g., the source electrode 11 extending over the gate electrode 8 toward the drain electrode 12) (Tanaka, Figs. 2F, 11, ¶0062, ¶0072, ¶0161) covering the insulation layer (14/9),
the source field plate (11) includes an end located between the second opening (e.g., 12a) and the gate layer (7) (Tanaka, Figs. 2G, 11, ¶0062, ¶0073, ¶0161),
the insulation layer (14/9) includes
a first insulation layer part (e.g., passivation layer 9, SiN) (Tanaka, Fig. 11, ¶0060, ¶0161) that is disposed on the electron supply layer (5/6) in contact with the drain electrode (e.g., 12) and has a first thickness (e.g., a thickness of the passivation layer 9 is about 100 nm) (Tanaka, Fig. 11, ¶0060, ¶0161), and
a second insulation layer part (e.g., a dielectric layer 14, SiO2 and a portion of the SiN layer 9 over the gate electrode 8) (Tanaka, Fig. 11, ¶0161) that is disposed on the gate electrode (8) in contact with the source field plate (11) and has a second thickness (e.g., including a thickness of the SiN layer 9 and a thickness of the SiO2 dielectric layer 14 above the gate electrode 8),
the end of the source field plate (11) is disposed on the first insulation layer part (e.g., 9) (Tanaka, Fig. 11, ¶0161),
the second thickness (e.g., including a thickness of the SiN layer 9 and a thickness of the SiO2 dielectric layer 14 above the gate electrode 8) (Tanaka, Fig. 11, ¶0060, ¶0161) of the second insulation layer part (14/9) is greater than the first thickness of the first insulation layer part (e.g., 9).
Further, Tanaka does not specifically disclose that the source field plate includes an end located between the second opening and the gate layer in a plan view, and the source electrode entirely surrounds the drain electrode in the plan view.
However, Joh teaches forming a high electron mobility transistor (HEMT) (Joh, Figs. 1C, 2, 3B-3D, Col. 1, lines 7-9, lines 37-41; lines 50-61; Col. 3, lines 10-67; Col. 4, lines 15-67; Col. 5, lines 1-23; lines 34-67; Col. 6, lines 1-24) having a drain centered layout where the high voltage drain area is completely enclosed by the gate and the source, to provide leakage current control and device isolation, and thus to improve device robustness and reliability. In Joh, the drain (120) is completely enclosed by both the gate (114) and the source (122), and there is electrical isolation (Joh, Figs. 1C, 2, 3B-3D, Col. 5, lines 3-8) between the metal providing the gate (114) and the source (122), wherein a dielectric layer is provided over the metal of the gate (114), and the metal of the source (122) is on top of the dielectric layer on the gate metal to form field plates, such that the source (122) including field plates has an end located between the drain (120) and the gate (114) in a plan view (e.g., Figs. 2, 3B-3D).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tanaka by forming HEMT transistor having a drain centered layout, and including the source completely enclosing the gate and having field plates as taught by Joh to have the method, wherein the source field plate includes an end located between the second opening and the gate layer in a plan view, and the source electrode entirely surrounds the drain electrode in the plan view, in order to provide leakage current control and device isolation, and thus to improve device robustness and reliability (Joh, Col. 1, lines 7-9, lines 37-41; lines 50-61; Col. 5, lines 3-8; Col. 6, lines 20-23).
Regarding claim 19, Tanaka in view of Joh discloses the method according to claim 16. Further, Tanaka discloses the method, wherein the forming an insulation layer (14/9) includes forming a spacer layer (e.g., dielectric layer 14 over the gate electrode 8) (Tanaka, Fig. 11, ¶0161) on the gate electrode (8), and forming a passivation layer (e.g., 9) that covers the electron supply layer (5/6), the gate layer (7), the gate electrode (8), and the spacer layer (e.g., 14) and includes the first opening (11a) (Tanaka, Fig. 11, ¶0060) and the second opening (12a), the first insulation layer part (e.g., 9) is formed of the passivation layer, and the second insulation layer part (14/9) is formed of the spacer layer (e.g., 14) and the passivation layer (e.g., the passivation layer 9 over the gate 8).
Regarding claim 20, Tanaka in view of Joh discloses the method according to claim 16. Further, Tanaka discloses the method, wherein the forming an insulation layer (14/9) includes selectively etching the insulation layer (e.g., forming the openings 11a and 12a) (Tanaka, Fig. 2E, ¶0071) so that the first insulation layer part (e.g., 9) differs in thickness from the second insulation layer part (14/9).
Regarding claim 21, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 1. Further, Tanaka discloses the nitride semiconductor device, wherein the first thickness is a thickness of the insulation layer (14/9) where the end of the source field plate (11) is located, and the second thickness (e.g., including a thickness of the SiN layer 9 and a thickness of the SiO2 dielectric layer 14 above the gate electrode 8) (Tanaka, Fig. 11, ¶0060, ¶0161) is a distance between the gate electrode (8) and the source electrode (11) in a region of the gate electrode (8), but does not specifically disclose the end of the source field plate in the plan view, and a region of the gate electrode in the plan view.
However, Joh teaches forming a high electron mobility transistor (HEMT) (Joh, Figs. 1C, 2, 3B-3D, Col. 1, lines 7-9, lines 37-41; lines 50-61; Col. 3, lines 10-67; Col. 4, lines 15-67; Col. 5, lines 1-23; lines 34-67; Col. 6, lines 1-24) having a drain centered layout where the high voltage drain area is completely enclosed by the gate and the source, wherein the drain (120) is completely enclosed by both the gate (114) and the source (122), and there is electrical isolation (Joh, Figs. 1C, 2, 3B-3D, Col. 5, lines 3-8) between the metal of the gate (114) and the source (122) by providing a dielectric layer over the metal of the gate (114), and the metal of the source (122) on top of the dielectric layer on the gate metal forms field plates, such that the source (122) including field plates has an end located between the drain (120) and the gate (114) in a plan view (e.g., Figs. 2, 3B-3D).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the nitride semiconductor device of Tanaka/Joh by forming HEMT transistor having a drain centered layout, and including the source completely enclosing the gate and having field plates as taught by Joh to have the nitride semiconductor device, wherein the end of the source field plate is located in the plan view, and a region of the gate electrode in the plan view, in order to provide leakage current control and device isolation, and thus to improve device robustness and reliability (Joh, Col. 1, lines 7-9, lines 37-41; lines 50-61; Col. 5, lines 3-8; Col. 6, lines 20-23).
Claims 2-3 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0104091 to Tanaka in view of Joh (US Patent No. 9,882,041) as applied to claim 1 (claim 16), and further in view of Chou et al. (US 2021/0151571, hereinafter Chou) and Yoshimochi (US 2019/0296140).
Regarding claims 2 and 3, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 1. Further, Tanaka does not specifically disclose that the second thickness is greater than or equal to 1.2 times the first thickness and less than or equal to 5.0 times the first thickness (as claimed in claim 2); wherein the first thickness is greater than or equal to 50 nm and less than or equal to 200 nm, and the second thickness is greater than or equal to 100 nm and less than or equal to 400 nm (as claimed in claim 3).
However, Chou teaches forming an insulating layer (116/120/124/126) (Chou, Fig. 8, ¶0030, ¶0032, ¶0035, ¶0036) including a first insulating layer (116/120) and a second insulating layer (124/126) over the gate electrode (112) and under the source field plate, and each insulating layer having a thickness (H1/H2/H3/H4) between 100 nm and 200 nm, and a distance between the field plate and the barrier (electron supply layer) is adjusted to improve the breakdown voltage (Chou, Fig. 8, ¶0049).
Thus, Chou recognizes that a distance between the field plate and the barrier (electron supply layer) impacts breakdown voltage of the HEMT device, Thus, a distance between the field plate and the barrier (electron supply layer) are a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a distance between the field plate and the barrier (electron supply layer) as Chou has identified a distance between the field plate and the barrier (electron supply layer) as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific thickness of the dielectric layer under the source field plate and a distance between the field plate and the barrier (electron supply layer), in order to improve the breakdown voltage as taught by Chou (¶0049) (MPEP 2144.05).
Further, Yoshimochi teaches a thickness of the passivation layer (8) (Yoshimochi, Fig. 8, ¶0047, ¶0055-¶0057) under the end of the source field plate (12) of about 100 nm, to protect electron supply layer, and thus to obtain improved a nitride semiconductor device.
Thus, a person of ordinary skill in the art would recognize that with a second thickness between 200 nm and 400 nm (corresponding to at least two insulating layers over the gate electrode and under the source field plate as taught by Chou), and with the first thickness of about 100 nm (as taught by Yoshimochi), the second thickness would be between 2 and 4 times the first thickness.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the nitride semiconductor device of Tanaka/Joh by adjusting a distance between the field plate and the barrier (electron supply), wherein the second thickness of the insulating layer over the gate and under the source field plate is in a range as taught by Chou, and wherein the first thickness corresponds to a thickness of the passivation layer on the barrier (electron supply) layer and under the end of the source field plate as taught by Yoshimochi to have the nitride semiconductor device, wherein the second thickness is greater than or equal to 1.2 times the first thickness and less than or equal to 5.0 times the first thickness (as claimed in claim 2); wherein the first thickness is greater than or equal to 50 nm and less than or equal to 200 nm, and the second thickness is greater than or equal to 100 nm and less than or equal to 400 nm (as claimed in claim 3), in order to improve the breakdown voltage; and to protect electron supply layer (Chou, ¶0049; Yoshimochi, ¶0055-¶0057).
Regarding claims 17 and 18, Tanaka in view of Joh discloses the method according to claim 16. Further, Tanaka does not specifically disclose that the second thickness is greater than or equal to 1.2 times the first thickness and less than or equal to 5.0 times the first thickness (as claimed in claim 2); wherein the first thickness is greater than or equal to 50 nm and less than or equal to 200 nm, and the second thickness is greater than or equal to 100 nm and less than or equal to 400 nm (as claimed in claim 3).
However, Chou teaches forming an insulating layer (116/120/124/126) (Chou, Fig. 8, ¶0030, ¶0032, ¶0035, ¶0036) including a first insulating layer (116/120) and a second insulating layer (124/126) over the gate electrode (112) and under the source field plate, and each insulating layer having a thickness (H1/H2/H3/H4) between 100 nm and 200 nm, and a distance between the field plate and the barrier (electron supply layer) is adjusted to improve the breakdown voltage (Chou, Fig. 8, ¶0049).
Thus, Chou recognizes that a distance between the field plate and the barrier (electron supply layer) impacts breakdown voltage of the HEMT device, Thus, a distance between the field plate and the barrier (electron supply layer) are a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a distance between the field plate and the barrier (electron supply layer) as Chou has identified a distance between the field plate and the barrier (electron supply layer) as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific thickness of the dielectric layer under the source field plate and a distance between the field plate and the barrier (electron supply layer), in order to improve the breakdown voltage as taught by Chou (¶0049) (MPEP 2144.05).
Further, Yoshimochi teaches a thickness of the passivation layer (8) (Yoshimochi, Fig. 8, ¶0047, ¶0055-¶0057) under the end of the source field plate (12) of about 100 nm, to protect electron supply layer, and thus to obtain improved a nitride semiconductor device.
Thus, a person of ordinary skill in the art would recognize that with a second thickness between 200 nm and 400 nm (corresponding to at least two insulating layers over the gate electrode and under the source field plate as taught by Chou), and with the first thickness of about 100 nm (as taught by Yoshimochi), the second thickness would be between 2 and 4 times the first thickness.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tanaka/Joh by adjusting a distance between the field plate and the barrier (electron supply), wherein the second thickness of the insulating layer over the gate and under the source field plate is in a range as taught by Chou, and wherein the first thickness corresponds to a thickness of the passivation layer on the barrier (electron supply) layer and under the end of the source field plate as taught by Yoshimochi to have the method, wherein the second thickness is greater than or equal to 1.2 times the first thickness and less than or equal to 5.0 times the first thickness (as claimed in claim 2); wherein the first thickness is greater than or equal to 50 nm and less than or equal to 200 nm, and the second thickness is greater than or equal to 100 nm and less than or equal to 400 nm (as claimed in claim 3), in order to improve the breakdown voltage; and to protect electron supply layer (Chou, ¶0049; Yoshimochi, ¶0055-¶0057).
Claims 8-9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0104091 to Tanaka in view of Joh (US Patent No. 9,882,041) as applied to claim 1 (claim 16), and further in view of Chen (US 2021/0013331).
Regarding claims 8 and 9, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 4. Further, Tanaka does not specifically disclose that the spacer layer and the passivation layer are composed of a same material (as claimed in claim 8); wherein each of the spacer layer and the passivation layer is composed of SiN (as claimed in claim 9).
However, Chen teaches the nitride semiconductor device, wherein the spacer layer (121) (Chen, Fig. 5, ¶0049-¶0051) and the passivation layer (130) (Chen, Fig. 5, ¶0049-¶0051, ¶0054) are composed of a same material (e.g., silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, or combination of thereof), wherein each of the spacer layer (121) and the passivation layer (130) is composed of SiN (Chen, Fig. 5, ¶0049, ¶0054, ¶0067), to provide insulation layers under the source field plate to reduce the effect of the electric field from the drain structure on the gate electrode to improve performance and reliability of the HEMT device (Chen, ¶0034, ¶0078).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the nitride semiconductor device of Tanaka/Joh by forming the dielectric layer under the source field plate having a specific material as taught by Chen to have the nitride semiconductor device, wherein the spacer layer and the passivation layer are composed of a same material (as claimed in claim 8); wherein each of the spacer layer and the passivation layer is composed of SiN (as claimed in claim 9), in order to provide the source field plate and to shield the source field plate from the electric field and to improve the problem of charge trapping, and to reduce the effect of the electric field from the drain structure on the gate electrode to improve performance and reliability of the HEMT device (Chen, ¶0003, ¶0034, ¶0067, ¶0069, ¶0078).
Regarding claim 12, Tanaka in view of Joh discloses the nitride semiconductor device according to claim 4. Further, Tanaka discloses the nitride semiconductor device, wherein the gate electrode (8) (Tanaka, Fig. 11, ¶0161, ¶0059) includes a first surface (e.g., a bottom surface) in contact with the gate layer (7), a second surface (e.g., a top surface) opposite to the first surface, and a third surface (e.g., sidewall surfaces) extending between the first surface and the second surface, and the spacer layer (14) is formed on the second surface (e.g., the top surface) of the gate electrode (8), but does not specifically disclose that the spacer layer is formed on the third surface of the gate electrode.
However, Chen discloses the nitride semiconductor device, wherein the spacer layer (121) (Chen, Fig. 5, ¶0049, ¶0054, ¶0067) is formed on the top surface and the sidewall surface of the gate electrode (118), to provide insulation layers under the source field plate to reduce the effect of the electric field from the drain structure on the gate electrode to improve performance and reliability of the HEMT device (Chen, ¶0034, ¶0078).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the nitride semiconductor device of Tanaka/Joh by forming the dielectric layers under the source field plate as taught by Chen to have the nitride semiconductor device, wherein the spacer layer is formed on the third surface of the gate electrode, in order to provide the source field plate and to shield the source field plate from the electric field and to improve the problem of charge trapping, and to reduce the effect of the electric field from the drain structure on the gate electrode to improve performance and reliability of the HEMT device (Chen, ¶0003, ¶0034, ¶0067, ¶0069, ¶0078).
Response to Arguments
Applicant's arguments filed 04/24/2026 have been fully considered but they are not persuasive.
In response to Applicant’s argument that “Tanaka has not been shown to teach or suggest the claimed planar arrangement in which the source electrode entirely, i.e., completely, surrounds the drain electrode”, the examiner submits that newly discovered prior art by Joh teaches forming a high electron mobility transistor (HEMT) having a drain centered layout where the drain is completely enclosed by the gate and the source, and the source field plate is formed by the metal of the source (122) on top of the dielectric layer provided over the metal of the gate (114), such that the source (122) including field plates has an end located between the drain (120) and the gate (114) in a plan view (e.g., Figs. 2, 3B-3D of Joh), as required by the amended claim 1. Thus, the above Applicant’s argument is not persuasive, and the rejection of claim 1 (claim 16) over 35 USC 103 over Tanaka in view of Joh is maintained.
Regarding dependent claims 2-14 and 17-21 which depend on the independent claims 1 and 16, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
Prosecution Insights