DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7, and 11-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sano et al. (U.S. Pub. 2016/0322374) [Hereafter “Sano”].
Regarding claims 1-4, Sano [Figs.1-15] discloses a manufacturing method of a semiconductor structure, comprising:
providing a substrate [8], and forming a stacked structure [32-42] on the substrate;
forming a hard mask layer [36] on the stacked structure, wherein the hard mask layer comprises a first etched window [59A-F], and the first etched window exposes part of a top surface of the stacked structure [Fig.2];
forming a photoresist layer [47] [Para.54], wherein the photoresist layer covers the first etched window [Fig.3]; and
trimming the photoresist layer for a plurality of times [Figs.4-7], after each trimming of the photoresist layer, etching the stacked structure according to a trimmed photoresist layer, and forming a plurality of steps [69A-F] in the stacked structure along a direction away from the substrate [Fig.7];
wherein the first etched window [59] extends along a first direction; in a second direction, a width of the first etched window is less than a width of the stacked structure [See close-up in Fig.2; Para.53]; the first direction and the second direction are parallel to a top surface of the substrate, and the first direction is perpendicular to the second direction [Fig.2];
wherein the stacked structure comprises a storage region [100/300] and a step region [300], the storage region extends along the first direction, the step region is arranged in the storage region along the first direction, and the first etched window [59] exposes a top surface of the stacked structure located in the step region [Figs.2-3];
further comprising:
from a first end [59A] of the first etched window to a second end [59F] of the first etched window, dividing the first etched window into a plurality of sub-windows arranged along the first direction; and
sequentially trimming the photoresist layer [57] from the first end of the first etched window to the second end of the first etched window, gradually reducing a width of the photoresist layer in the first direction each time, and sequentially exposing each of the sub-windows of the first etched window [Figs.3-7].
Regarding claims 6-7, Sano [Figs.1-15] discloses a manufacturing method of a semiconductor structure, comprising:
wherein the trimming the photoresist layer for a plurality of times, and after each trimming of the photoresist layer, etching the stacked structure according to a trimmed photoresist layer comprises:
trimming the photoresist layer [47] to expose part of the first etched window;
etching the stacked structure with the trimmed photoresist layer and the hard mask layer as a mask, removing part of the stacked structure exposed by the first etched window, and forming an opening [69A] in the stacked structure; and
repeating the steps of trimming the photoresist layer and etching the stacked structure exposed by the first etched window with the trimmed photoresist layer and the hard mask layer as a mask, wherein a depth of a formed opening is increased as the stacked structure is etched each time [Figs.3-7];
wherein the stacked structure comprises a plurality of layers of laminated units [32-42] sequentially laminated on the substrate, and the etching the stacked structure with the trimmed photoresist layer and the hard mask layer as a mask comprises:
etching and removing part of the laminated unit located on a top layer of the stacked structure to expose a top surface of the laminated unit of a next layer and stopping etching [Figs.4-5];
wherein the depth of the formed opening [69A] is increased by a thickness of one of the laminated units, as the stacked structure is etched each time [Figs.4-7].
Regarding claims 11-13, Sano [Figs.1-15] discloses a semiconductor structure, wherein the semiconductor structure is manufactured according to the manufacturing method of a semiconductor structure according to claim 1, and the semiconductor structure comprises:
a substrate [8]; and
a stacked structure [32-42] arranged on the substrate, wherein a plurality of steps [69A-F] are arranged in the stacked structure along a direction away from the substrate [Fig.7];
wherein the plurality of steps [69A-F] are arranged along a first direction and the plurality of steps are raised step by step along the direction away from the substrate; in a second direction, a width of the step is less than a width [See close-up in Fig.6] of the stacked structure; the first direction and the second direction are parallel to a top surface of the substrate, and the first direction is perpendicular to the second direction;
wherein the stacked structure comprises a storage region [100/300] and a step region [300], the storage region extends along the first direction, the step region is arranged in the storage region along the first direction, and the plurality of steps [69A-F] are arranged in the step region [300] along the first direction [Fig.6].
Allowable Subject Matter
Claims 5, 8-10, and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not fairly disclose or make obvious the claimed device/method taken as a whole, and specifically, the limitations of
wherein the stacked structure is etched according to a trimmed photoresist layer after each trimming of the photoresist layer, to form a plurality of openings in the stacked structure; the plurality of openings and the plurality of sub-windows are arranged in a one-to-one correspondence from the first end of the first etched window to the second end of the first etched window, depths of the plurality of openings sequentially decrease, two adjacent ones of the openings form one of the steps in the stacked structure, and the plurality of steps are raised step by step along the direction away from the substrate;
wherein along the direction away from the substrate, the laminated unit of each layer comprises an active layer and a support layer that are laminated sequentially, each of the steps formed in the stacked structure comprises the active layer and the support layer that are laminated, and a side face of each of the steps comprises a side face of the active layer and a side face of the support layer;
wherein the stacked structure further comprises:
a plurality of openings, wherein the plurality of openings are arranged along the first direction, depths of the plurality of openings sequentially decrease, and two adjacent ones of the openings form one of the steps in the stacked structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/BAC H AU/Primary Examiner, Art Unit 2898