DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 01/08/2026.
Applicant’s amendments filed 01/08/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1, 7, 11-14, 17, and 19-20; cancelation of claims 6 and 18; and the addition of new claims 24-25.
Election/Restrictions
Newly submitted claim 11 is directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
The amended claim 11 recites limitations “the n-doped cathode layer is arranged over an entire first main surface of the second semiconductor layer stack”, and is drawn to the embodiment of Fig. 1 or Fig. 5. However, claim 12 (and previously presented 8) recites “the n-doped cathode layer is arranged in the central portion of the diode at the first main surface of the second semiconductor layer stack”, and is drawn to the embodiment of Fig. 3A. These features of claims 11 and 12 (or 8) are independent or distinct because the claims 11 and 12 (or 8) recite the mutually exclusive characteristics of these features; specifically, wherein “the n-doped cathode layer is arranged over an entire first main surface of the second semiconductor layer stack”; and wherein “the n-doped cathode layer is arranged in the central portion of the diode at the first main surface of the second semiconductor layer stack”. In addition, these features are not obvious variants of each other based on the current record.
Since applicant has received an action on the merits for the originally presented invention (e.g., as recited in claims 8 and 12), this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 11 (including dependent claims 12-14 and 24-25) are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-9, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067174 to Seok in view of Yang et al. (CN 105405895 A, hereinafter Yang).
With respect to claim 1, Seok discloses a semiconductor device (e.g., a packaged semiconductor device) (Seok, Figs. 1-6, ¶0003-¶0004, ¶0021-¶0041), comprising:
a transistor (e.g., NFET die 8) (Seok, Figs. 1-3, ¶0021-¶0026) formed in a first semiconductor layer stack (e.g., N++ type substrate layer 37/N- type drift layer 36);
a diode (e.g., the inverse diode die 9) (Seok, Figs. 1-2, 5-6, ¶0021-¶0022, ¶0027-¶0032) formed in a second semiconductor layer stack (e.g., P- type substrate layer 50/N- type drift layer 52), the diode (9) comprising an anode metal layer (e.g., bottomside anode metal terminal 23) (Seok, Figs. 1-2, 5-6, ¶0031); and
a carrier (e.g., metal die attach tab 7) (Seok, Figs. 1-3, 5-6, ¶0021),
wherein the transistor (e.g., NFET 8) and the diode (9) are mounted to the carrier (7),
wherein a terminal (e.g., bottomside drain metal electrode 21) (Seok, Figs. 1-3, 5-6, ¶0022) of the transistor (8) is electrically connected to the carrier (7),
wherein the anode metal layer (23) is in direct contact with the carrier (7),
wherein the diode (9) comprises a low doped drift region (52) between an anode region (50) and a cathode region (53/55).
Further, Seok does not specifically disclose that a conductivity type of the low doped drift region is different from a conductivity type of a drift zone of the transistor.
However, Yang teaches forming a fast recovery diode chip (Yang, Fig. 4, pp. 1-2, 6-7) with increased switching speed capability and comprising P-type drift region to realize high electron mobility, wherein the diode comprises a p-doped substrate layer (20/21) and an n-doped cathode layer (22/26) formed over the p-doped substrate layer (20/21), and wherein the semiconductor device further comprises a p-doped drift region (21) in the p-doped substrate layer (20/21).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Seok by forming a diode chip having P-type drift region as taught by Yang to have the semiconductor device, wherein a conductivity type of the low doped drift region is different from a conductivity type of a drift zone of the transistor, in order to provide a fast recovery diode chip having high electron mobility to increase switching speed capability (Yang, Abstract, pp. 1-3, 6-7).
Regarding claim 2, Seok in view of Yang discloses the semiconductor device of claim 1. Further, Seok discloses the semiconductor device, wherein the second semiconductor layer stack (e.g., P- type substrate layer 50/N- type layer 52) (Seok, Figs. 1-2, 5-6, ¶0021, ¶0027) comprises semiconductor layers that do not form part of the first semiconductor layer stack (e.g., N++ type substrate layer 37/N- type drift layer 36) (Seok, Figs. 1-2, 5-6, ¶0021, ¶0025).
Regarding claim 3, Seok in view of Yang discloses the semiconductor device of claim 1. Further, Seok discloses the semiconductor device, wherein the terminal (e.g., bottomside drain metal electrode 21) (Seok, Figs. 1-3, 5-6, ¶0022) of the transistor (8) is in direct contact with the carrier (7).
Regarding claim 4, Seok in view of Yang discloses the semiconductor device of claim 1. Further, Seok discloses the semiconductor device, wherein the transistor (e.g., NFET die 8) (Seok, Figs. 1-3, ¶0021-¶0026) is a MOSFET and the terminal (21) (Seok, Figs. 1-3, ¶0022) of the transistor is a drain terminal.
With respect to claim 7, Seok discloses a semiconductor device (e.g., a packaged semiconductor device) (Seok, Figs. 1-6, ¶0003-¶0004, ¶0021-¶0041), comprising:
a transistor (e.g., NFET die 8) (Seok, Figs. 1-3, ¶0021-¶0026) formed in a first semiconductor layer stack (e.g., N++ type substrate layer 37/N- type drift layer 36);
a diode (e.g., the inverse diode die 9) (Seok, Figs. 1-2, 5-6, ¶0021-¶0022, ¶0027-¶0032) formed in a second semiconductor layer stack (e.g., P- type substrate layer 50/N- type drift layer 52), the diode (9) comprising an anode metal layer (e.g., bottomside anode metal terminal 23) (Seok, Figs. 1-2, 5-6, ¶0031); and
a carrier (e.g., metal die attach tab 7) (Seok, Figs. 1-3, 5-6, ¶0021),
wherein the transistor (e.g., NFET 8) and the diode (9) are mounted to the carrier (7),
wherein a terminal (e.g., bottomside drain metal electrode 21) (Seok, Figs. 1-3, 5-6, ¶0022) of the transistor (8) is electrically connected to the carrier (7),
wherein the anode metal layer (23) is in direct contact with the carrier (7),
wherein the diode (9) comprises a low doped drift region (52) between an anode region (50) and a cathode region (53/55).
Further, Seok does not specifically disclose that the diode comprises a p-doped substrate layer and an n-doped cathode layer formed over the p-doped substrate layer, and wherein the semiconductor device further comprises a p-doped drift region in the p-doped substrate layer.
However, Yang teaches forming a fast recovery diode chip (Yang, Fig. 4, pp. 1-2, 6-7) with increased switching speed capability and comprising P-type drift region to realize high electron mobility, wherein the diode comprises a p-doped substrate layer (20/21) and an n-doped cathode layer (22/26) formed over the p-doped substrate layer (20/21), and wherein the semiconductor device further comprises a p-doped drift region (21) in the p-doped substrate layer (20/21).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Seok by forming a diode chip having P-type drift region as taught by Yang to have the semiconductor device, wherein the diode comprises a p-doped substrate layer and an n-doped cathode layer formed over the p-doped substrate layer, and wherein the semiconductor device further comprises a p-doped drift region in the p-doped substrate layer, in order to provide a fast recovery diode chip having high electron mobility to increase switching speed capability (Yang, Abstract, pp. 1-3, 6-7).
Regarding claim 8, Seok in view of Yang discloses the semiconductor device of claim 7. Further, Seok discloses the semiconductor device, wherein the n- doped cathode layer (53/55-57) (Seok, Figs. 5, 7, ¶0027-¶0028) is arranged in a central portion of the diode at a first main surface of the second semiconductor layer stack (50/52), and wherein the diode further comprises an edge termination structure (P+ type rings 63) (Seok, Figs. 5, 7, ¶0028) horizontally surrounding the central portion.
Regarding claim 9, Seok in view of Yang discloses the semiconductor device of claim 8. Further, Seok discloses the semiconductor device, wherein the edge termination structure comprises a portion (P+ type rings 63) (Seok, Figs. 5, 7, ¶0028) arranged at the first main surface of the second semiconductor layer stack and isolated from the n-doped cathode layer (53/55-57), but does not specifically disclose that the edge termination structure comprises an n-doped ring portion.
However, Yang teaches forming an n-doped ring portion (23) (Yang, Fig. 4, pp. 6-7) as a field limiting ring region arranged at the first main surface of the second semiconductor layer stack including P-type drift region and isolated from the n-doped cathode layer (22/26) with portions of the oxide layer (24).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Seok/Yang by forming a diode chip having P-type drift region and including N-type rings as taught by Yang to have the semiconductor device, wherein the edge termination structure comprises an n-doped ring portion, in order to provide a field limiting ring region for a fast recovery diode chip having high electron mobility to increase switching speed capability (Yang, Abstract, pp. 1-3, 6-7).
Regarding claim 15, Seok in view of Yang discloses the semiconductor device of claim 1. Further, Seok discloses an electronic device (e.g., converter 18) (Seok, Figs. 1-2, ¶0023) comprising the semiconductor device of claim 1.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067174 to Seok in view of Yang (CN 105405895 A) as applied to claim 1, and further in view of Osawa et al. (US Patent No. 7,750,463, hereinafter Osawa).
Regarding claim 5, Seok in view of Yang discloses the electronic device of claim 1. Further, Seok does not specifically disclose the electronic device, wherein the transistor is an IGBT and the terminal of the transistor is a collector terminal.
However, Osawa teaches forming a packaged power semiconductor module (Osawa, Figs. 3A-3C, 4-5, Col. 1, lines 13-17; Col. 2, lines 37-41; Col. 4, lines 14-24; Col. 5, lines 21-52; Col. 6, lines 30-67; Col. 7, lines 1-67; Col. 8, lines 1-3) comprising an IGBT transistor (Q2) and diode (Di2), wherein the metal base plate (102) and the IGBT transistor (Q2) are connected on a surface of the collector electrode of the IGBT. In Osawa, since an insulating substrate is not used, the heat generated in the power semiconductor element is directly diffused to the metal base to improve heat dissipation characteristics and reliability of the semiconductor device (Osawa, Col. 1, lines 13-17; Col. 2, lines 37-41; Col. 4, lines 14-24; Col. 7, lines 65-67; Col. 8, lines 1-3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Seok/Yang by forming a packaged module comprising an IGBT and diode mounted on the metal plate as taught by Osawa/Yang to have the semiconductor device, wherein the transistor is an IGBT and the terminal of the transistor is a collector terminal, in order to provide a power semiconductor module with improved heat dissipation characteristics and reliability of the semiconductor device (Osawa, Col. 1, lines 13-17; Col. 2, lines 37-41; Col. 4, lines 14-24; Col. 7, lines 65-67; Col. 8, lines 1-3).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067174 to Seok in view of Yang (CN 105405895 A) as applied to claim 8, and further in view of Senoo (US Patent No. 9,035,415).
Regarding claim 10, Seok in view of Yang discloses the semiconductor device of claim 8. Further, Seok does not specifically disclose that the edge termination structure comprises an n-doped termination portion having a decreasing doping concentration in a direction facing away from the central portion and arranged at the first main surface of the second semiconductor layer stack.
However, Senoo teaches forming an edge termination structure (34) (Senoo, Figs. 1-10, Col. 4, lines 1-4; Col. 6, lines 28-39 Col. 7, lines 10-17) for the vertical semiconductor device comprising a diode, wherein the edge termination structure (34) comprises a termination portion having a decreasing doping concentration in a direction facing away from the central portion (e.g., gradually decreases from the end part B near the center of the device to an end part A on the outer periphery of the device) and arranged at the first main surface of a semiconductor layer stack (38/30), to prevent carrier from concentrating in the end part far from the active region to improve breakdown strength of the device (Senoo, Col. 1, lines 57-62; Col. 4, lines 1-4; Col. 6, lines 28-39 Col. 7, lines 10-17).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Seok/Yang by forming the edge termination structure including gradually decreasing doping concentration as taught by Senoo, wherein the diode device includes P-type drift layer and N-type edge termination structure as taught by Yang to have the semiconductor device, wherein the edge termination structure comprises an n-doped termination portion having a decreasing doping concentration in a direction facing away from the central portion and arranged at the first main surface of the second semiconductor layer stack, in order to provide a field limiting ring region for a fast recovery diode chip having high electron mobility to increase switching speed capability; and to prevent carrier from concentrating in the end part far from the active region to improve breakdown strength of the device (Yang, Abstract, pp. 1-3, 6-7; Senoo, Col. 1, lines 57-62; Col. 4, lines 1-4; Col. 6, lines 28-39 Col. 7, lines 10-17).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067174 to Seok in view of Yang (CN 105405895 A) as applied to claim 15, and further in view of in view of Hebert et al. (US 2008/0023825, hereinafter Hebert).
Regarding claim 16, Seok in view of Yang discloses the electronic device of claim 15. Further, Seok discloses the electronic device, wherein the electronic device is boost AC-DC converter (18) (Seok, Figs. 1-2, ¶0023), but does not specifically disclose a buck converter or a DC-DC converter.
However, Hebert teaches forming DC-DC converter (Hebert, Figs. 3A-3C, ¶0006-¶0007, ¶0013, ¶0026-¶0029) using co-packaged vertical MOSFET (41) and diode (40) on a lead frame (40c) with the bottom substrate anode (40a) and bottom substrate drain (41b) electrically connected to a single die pad (40c), to realize efficient semiconductor package having small package size and eliminated parasitic capacitance and inductance (Hebert, ¶0006-¶0007, ¶0013, ¶0026, ¶0029).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the electronic device of Seok/Yang by forming a packaged module including voltage converter as taught by Hebert to have the electronic device, wherein the electronic device is a DC-DC converter, in order to realize efficient semiconductor package having small package size and eliminated parasitic capacitance and inductance (Hebert, ¶0006-¶0007, ¶0013, ¶0026, ¶0029).
Claims 17, 19-21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067174 to Seok in view of Ewe et al. (US 2011/0108971, hereinafter Ewe).
With respect to claim 17, Seok discloses a semiconductor device (e.g., a packaged semiconductor device) (Seok, Figs. 1-6, ¶0003-¶0004, ¶0021-¶0041), comprising:
a transistor (e.g., NFET die 8) (Seok, Figs. 1-3, ¶0021-¶0026) formed in a first semiconductor layer stack (e.g., N++ type substrate layer 37/N- type drift layer 36);
a diode (e.g., the inverse diode die 9) (Seok, Figs. 1-2, 5-6, ¶0021-¶0022, ¶0027-¶0032) formed in a second semiconductor layer stack (e.g., P- type substrate layer 50/N- type drift layer 52), the second semiconductor layer stack (50/52) comprising semiconductor layers that do not form part of the first semiconductor layer stack (36/37);
a carrier (e.g., metal die attach tab 7) (Seok, Figs. 1-3, 5-6, ¶0021); and
an insulating material (e.g., encapsulant 17 including a resin material) (Seok, Figs. 1-3, 5-6, ¶0021),
wherein the transistor (e.g., NFET 8) and the diode (9) are mounted to the carrier (7),
wherein a transistor terminal (e.g., bottomside drain metal electrode 21) (Seok, Figs. 1-3, 5-6, ¶0022) and a diode anode terminal (23) are electrically connected to the carrier (7),
wherein the insulating material (e.g., the injection-molded encapsulant 17) overmolds and encapsulates the transistor die 8 and the diode die 9 bond wires and die attached pad 7, and thus is formed in a space between the transistor die 8 and the diode die 9, as in Fig. 1) is also arranged between the diode (9) and the transistor. (8)
Further, Seok does not specifically disclose an insulating material between the diode and the carrier, and wherein the diode is electrically connected to the carrier through via openings in the insulating material.
However, Ewe teaches forming a power semiconductor device (e.g., MOSFET, IGBT, or power diode) (Ewe, Figs. 1F, 2E, ¶0001, ¶0016-¶0022, ¶0035-¶0040, ¶0047-¶0054) embedded into insulating material (e.g., 30 in Fig. 1F, or 130/150 in Fig. 2E), wherein an insulating material (e.g., 150/130) is provided between the power semiconductor device (120-1, 120-3 or 120-2) and the structured metal layer (140/160), and an electrically conductive material is formed by galvanic deposition (Ewe, Figs. 1F, 2E, ¶0022, ¶0039-¶0040, ¶0052-¶0053) by filling the openings (e.g., 132a-132e) of the insulating material (130/150), to produce an electrical contact between electrode pads of the semiconductor device and the structured metal layer having a small thickness to facilitate further lamination steps, and to promote efficient heat removal.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Seok by forming a packaged module comprising bonding layer formed by galvanically deposited electrically conductive material filled in the openings of the insulating material as taught by Ewe to have the semiconductor device, further comprising: an insulating material between the diode and the carrier, and wherein the diode is electrically connected to the carrier through via openings in the insulating material, in order to provide a packaged device with embedded semiconductor chips, and to produce an electrical contact having a small thickness to facilitate further lamination steps, and to promote efficient heat removal (Ewe, ¶0001, ¶0016, ¶0022, ¶0054).
Regarding claim 19, Seok in view of Ewe discloses the semiconductor device of claim 17. Further, Seok does not specifically disclose further comprising a first galvanic interconnect material for electrically connecting a cathode terminal of the diode.
However, Ewe teaches forming a power semiconductor device including a power diode (Ewe, Figs. 1F, 2E, ¶0001, ¶0016-¶0022, ¶0035-¶0040, ¶0047-¶0054) embedded into insulating material (e.g., 30 in Fig. 1F, or 130/150 in Fig. 2E), wherein an insulating material (e.g., 30 or 130) is provided on the power semiconductor device (20 or 120-1) and the structured metal layer (40/140) is formed on the insulating material (30/130), and further comprising a galvanic interconnect material formed by galvanically deposited electrically conductive material (Ewe, Figs. 1F, 2E, ¶0022, ¶0039-¶0040, ¶0052-¶0053) filled in the openings (32a-32b or 132d) of the insulating material (30/130) onto the electrode pads of the semiconductor chips, to produce an electrical contact between electrode pads of the semiconductor device and the structured metal layer having a small thickness to facilitate further lamination steps, and to promote efficient heat removal.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Seok/Ewe by forming a packaged module comprising bonding layer formed by galvanically deposited electrically conductive material filled in the openings of the insulating material as taught by Ewe, wherein the semiconductor device includes a power diode having an electrical contact to a topside cathode electrode covered with insulating material to have the semiconductor device, further comprising a first galvanic interconnect material for electrically connecting a cathode terminal of the diode, in order to provide a packaged device with embedded semiconductor chips, and to produce an electrical contact having a small thickness to facilitate further lamination steps, and to promote efficient heat removal (Ewe, ¶0001, ¶0016, ¶0022, ¶0054).
Regarding claim 20, Seok in view of Ewe discloses the semiconductor device of claim 17. Further, Seok does not specifically disclose further comprising a second galvanic interconnect material for electrically connecting the anode terminal of the diode to the carrier.
However, Ewe teaches forming a power semiconductor device including a power diode (Ewe, Figs. 1F, 2E, ¶0001, ¶0016-¶0022, ¶0035-¶0040, ¶0047-¶0054) embedded into insulating material (e.g., 30 in Fig. 1F, or 130/150 in Fig. 2E), wherein an insulating material (e.g., 150) is provided on the power semiconductor device (120-2/120-3) and the structured metal layer (160) is formed on the insulating material (150), and further comprising a galvanic interconnect material formed by galvanically deposited electrically conductive material (Ewe, Fig. 2E, ¶0022, ¶0039-¶0040, ¶0052-¶0053) filled in the openings (132a-132b, 132e) of the insulating material (150) onto the electrode pads of the semiconductor chips, to produce an electrical contact between electrode pads of the semiconductor device and the structured metal layer having a small thickness to facilitate further lamination steps, and to promote efficient heat removal.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Seok/Ewe by forming a packaged module comprising bonding layer formed by galvanically deposited electrically conductive material filled in the openings of the insulating material as taught by Ewe, wherein the semiconductor device includes a power diode having an electrical contact to a bottomside anode electrode covered with insulating material to have the semiconductor device, further comprising a second galvanic interconnect material for electrically connecting the anode terminal of the diode to the carrier, in order to provide a packaged device with embedded semiconductor chips, and to produce an electrical contact having a small thickness to facilitate further lamination steps, and to promote efficient heat removal (Ewe, ¶0001, ¶0016, ¶0022, ¶0054).
Regarding claim 21, Seok in view of Ewe discloses the electronic device of claim 17. Further, Seok discloses the electronic device, wherein the carrier (7) (Seok, Figs. 1-3, 5-6, ¶0021) comprises a metal layer (e.g., copper sheet 7).
Regarding claim 22, Seok in view of Ewe discloses the semiconductor device of claim 21. Further, Seok discloses an electronic device (e.g., converter 18) (Seok, Figs. 1-2, ¶0023) comprising the semiconductor device of claim 21.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067174 to Seok in view of Ewe (US 2011/0108971) as applied to claim 22, and further in view of Hebert (US 2008/0023825).
Regarding claim 23, Seok in view of Ewediscloses the electronic device of claim 22. Further, Seok discloses the electronic device, wherein the electronic device is boost AC-DC converter (18) (Seok, Figs. 1-2, ¶0023), but does not specifically disclose a buck converter or a DC-DC converter.
However, Hebert teaches forming DC-DC converter (Hebert, Figs. 3A-3C, ¶0006-¶0007, ¶0013, ¶0026-¶0029) using co-packaged vertical MOSFET (41) and diode (40) on a lead frame (40c) with the bottom substrate anode (40a) and bottom substrate drain (41b) electrically connected to a single die pad (40c), to realize efficient semiconductor package having small package size and eliminated parasitic capacitance and inductance (Hebert, ¶0006-¶0007, ¶0013, ¶0026, ¶0029).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the electronic device of Seok/Ewe by forming a packaged module including voltage converter as taught by Hebert to have the electronic device, wherein the electronic device is a DC-DC converter, in order to realize efficient semiconductor package having small package size and eliminated parasitic capacitance and inductance (Hebert, ¶0006-¶0007, ¶0013, ¶0026, ¶0029).
Response to Arguments
Applicant's arguments filed 01/08/2026 have been fully considered but they are not persuasive.
In response to applicant’s argument that “Modifying Seok's inverse diode device 9 to include a p-type layer in place of the n-type silicon region 52 would clearly change the principle of operation of Seok's inverse diode device 9, possibly to the detriment of the clearly stated advantageous performance characteristics. Moreover, the Yang reference describes advantages of the disclosed device relating only to reduced stored charge and increased switching speed. By contrast, Seok describes numerous advantageous performance characteristics which include the improved switching speed addressed by the Yang reference and additional advantageous characteristics of a low forward voltage drop, a high reverse breakdown voltage, and a low reverse leakage current”, the examiner submits that the Office Action does not suggest to modify Seok's inverse diode device 9 to include a p-type layer in place of the n-type silicon region 52. Specifically, the Office Action suggest to modify the semiconductor device of Seok by forming a diode chip having P-type drift region as taught by Yang. The fast recovery diode chip of Yang has various advantageous characteristics including greatly reduced storage charge value in addition to the improved switching speed capabilities, and improved total power consumptions efficiency. Thus, a person of ordinary skill in the art would be motivated to form a diode chip having P+/P-/N+ diode structure as taught by Yang to have various advantageous characteristics including improved total power consumptions efficiency. Thus, the above applicant’s argument is not persuasive, and the rejection of claim 1 under 35 USC 103 over Seok in view of Yang is maintained.
In response to applicant’s argument regarding claim 11 that is written in independent form “[t]o include the features of original claim 1 (i.e., prior to the present amendment to claim 1) and additional features. Specifically, claim 11 is amended to further recite, inter alia: wherein the diode comprises... the n-doped cathode layer is arranged over an entire first main surface of the second semiconductor layer stack”, the examiner submits that the amended claim 11 is directed to an invention that is independent or distinct from the invention originally claimed as indicated above. Specifically, the amended claim 11 reciting “the n-doped cathode layer is arranged over an entire first main surface of the second semiconductor layer stack” is drawn to the embodiment of Fig. 1 or Fig. 5. However, claim 12 (and previously presented 8) reciting “the n-doped cathode layer is arranged in the central portion of the diode at the first main surface of the second semiconductor layer stack” is drawn to the embodiment of Fig. 3A. These features of claims 11 and 12 (or 8) are independent or distinct because the claims 11 and 12 (or 8) recite the mutually exclusive characteristics of these features. Since applicant has received an action on the merits for the originally presented invention (e.g., as recited in claims 8 and 12), this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 11 (including dependent claims 12-14 and 24-25) are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
In response to applicant’s argument that “The Office's proposed modification of Seok with the features of Ewe clearly lacks rational underpinning. Seok‘s semiconductor device 1 is a molded device in which the NFET die 8 and inverse diode die 9 are first both attached (e.g. soldered20) to the die attach tab 7 and electrically coupled to package terminals with bond wires, and then overmolded with the injection molded plastic encapsulant 17…By contrast, Ewe teaches laminated device structure in which chips are embedded in insulating layers which are then stacked on one another to form the laminated device. The metal filled openings that the Office alleged would be obvious to include in Seok's semiconductor device 1 (openings 132a, 132b, 1320, 132d, 132e) are formed to provide electrical connections between chips in the multiple layers of the laminated device but would clearly serve no purpose in Seok's device, …Rather, forming such openings would only unnecessarily increase manufacturing complexity with no benefit and, in fact, could actually negatively impact the performance of Seok's semiconductor device 1 by increasing electrical and/or thermal resistance between the NFET die 8 / inverse diode die 9 and the die attach tab 7. The Office's proposed modification of Seok with Ewe would therefore clearly not be obvious nor beneficial to Seok's semiconductor device 1”. In response, the examiner submits that the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). In the instant case, the laminated device structure of Ewe in which chips are embedded in insulating layers which are then stacked on one another to form the laminated device does not have to be bodily incorporated into the structure of the Seok. However, a person of ordinary skill in the art would recognize that forming an insulating material between the diode and the carrier, wherein the diode is electrically connected to the carrier through via openings in the insulating material (as taught by Ewe) would be advantageous in promoting efficient heat removal from the power device (Ewe, ¶0001, ¶0016, ¶0022, ¶0054).
Thus, the above applicant’s argument is not persuasive, and the rejection of claim 17 under 35 USC 103 over Seok in view of Ewe is maintained.
Regarding dependent claims 2-5, 8-10, 15-16, and 19-23 which depend on the independent claim 1, 7, and 17, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891