DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/3/2023 and 11/7/2025 are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Van et al. (US 20220077062 A1, IDS) in view of Park et al. (US 20160351472 A1) and Lee et al. (US 20140084375 A1).
Re Claim 1 Van teaches a semiconductor device (FIG. 1A-C), comprising:
a substrate (102) [0023] having first (top) and second (bottom) surfaces opposing each other, and comprising a fin-type active pattern (109) [0024] that extends in a first direction (X-axis, FIG. 2);
an isolation insulating layer (118) [0022] on side surfaces of the fin-type active pattern (109);
a gate structure (122, 121 and 123 combined) [0027] that extends in a second direction (Y-axis, FIG. 4) and intersects (from top-down view, FIG. 2) the fin-type active pattern (109);
source/drain regions (124a/b) [0025] on the fin-type active pattern (109) and on side surfaces of the gate structure (121 and 123, FIG. 1C);
an interlayer insulating layer (130) [0022] on the isolation insulating layer (118), on side surfaces of the gate structure (121 and 123) and on the source/drain region (124a/b);
a contact structure (131) [0028] that penetrates the interlayer insulating layer (130) and is electrically connected to the source/drain regions (131 is directly connected to 124b, and 124a and 124b are electrically connected since they are part of same transistor, 131 is therefore electrically connected to 124a and 124b);
a buried conductive structure (128a) [0032] electrically connected to the contact structure (131, 128a and 131 are both electrically connected to 124a/b) and in the interlayer insulating layer (130) and the isolation insulating layer (118); and
a power delivery structure (116) [0028] that extends from the second surface (bottom) of the substrate (102) toward the first surface (top) of the substrate, is in (electrical) contact with a bottom surface of the buried conductive structure (128a), and is electrically connected to the buried conductive structure (116 and 128a are both connected to 114a [0028], and 128a and 116 are therefore electrically connected).
Van does not teach the buried conductive structure comprises a first contact plug, a first conductive barrier on a side surface of the first contact plug and spaced apart from a bottom portion of the side surface of the first contact plug, and a first insulating liner on the first conductive barrier, and
wherein the power delivery structure comprises a second contact plug, a second conductive barrier on a side surface of the second contact plug and an upper surface of the second contact plug and in direct contact with a bottom surface of the first contact plug, and a second insulating liner between the second conductive barrier and the substrate.
Park teaches the buried conductive structure (30) [0034] comprises a first contact plug (32), a first conductive barrier (34) on a side surface of the first contact plug (32) and spaced apart from a bottom portion of the side surface of the first contact plug (32), and a first insulating liner (40) [0042] on the first conductive barrier (34), and
wherein the power delivery structure (60 & 70) [0043] comprises a second contact plug (70), a second conductive barrier (60) on a side surface of the second contact plug (70) and an upper surface of the second contact plug (70) and in direct contact with a bottom surface of the first contact plug (32, FIG. 6).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Park into the structure of Van since Park teaches a semiconductor structure with conductive lines integrated through the substrate.
The ordinary artisan would have been motivated to modify Kim in combination with Van in the above manner for the motivation of optimally integrating the buried conductive structure and power structure into the semiconductor device to increase the device’s storage capacity. [0003] states, “Semiconductor dies are vertically stacked to form a three-dimensional (3D) package to increase storage capacity.”
Van in view of Park does not teach a second insulating liner between the second conductive barrier and the substrate.
Lee teaches a second insulating liner (325) [0055] between the second conductive barrier (420) [0052] and the substrate (100, [0053], FIG. 1A&B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Van in view of Park since Lee teaches a semiconductor device with a power delivery structure.
The ordinary artisan would have been motivated to modify Lee in combination with Van in view of Park in the above manner for the motivation of optimally integrating an insulating liner around the power structure to increase the degree of integration in the semiconductor device. [0003] states, “Technology for forming through-silicon via (TSV) structures and back side bonding structures has been suggested to increase a degree of integration in semiconductor devices and electronic systems.”
Re Claim 2 Van in view of Park and Lee teaches the semiconductor device of claim 1, wherein the first conductive barrier (Park, 34) is open in a side region that is adjacent to the bottom surface of the first contact plug (32, FIG. 6).
Re Claim 3 Van in view of Park and Lee teaches the semiconductor device of claim 2, wherein the second conductive barrier (Park, 60) has an extended portion (region on sidewalls of 32) that extends along a portion of the side region of the first contact plug (32, FIG. 6).
Re Claim 4 Van in view of Park and Lee teaches the semiconductor device of claim 3, wherein the extended portion of the second conductive barrier (Park, 60) is between the side surface of the first contact plug (32) and the first insulating liner (40, FIG. 6).
Re Claim 5 Van in view of Park and Lee teaches the semiconductor device of claim 1,
wherein the second conductive barrier (Park, 60) has a first region in contact with the bottom surface of the first contact plug (30B) and a second region on side surfaces of the second contact plug (70), and
wherein the first region (60 under 30B) is recessed toward the bottom surface of the first contact plug (32, FIG. 6).
Re Claim 6 Van in view of Park and Lee teaches the semiconductor device of claim 1, wherein the first conductive barrier (Park, 34, use Ta called out in [0036]) and the second conductive barrier (60, use Al called out in [0045]) comprise different conductive materials.
Re Claim 7 Van in view of Park and Lee teaches the semiconductor device of claim 1, wherein the buried conductive structure (Lee, 200) [0040] extends into the substrate (100) through the isolation insulating layer (130) [0040], and the buried conductive structure (200) is in contact with the power delivery structure (400) [0040] in the substrate (100, FIG. 1A&B).
Re Claim 8 Van in view of Park and Lee teaches the semiconductor device of claim 7,
wherein an upper surface of the power delivery structure (Lee, 400) has a first region in contact with the bottom surface of the buried conductive structure (200), and a second region on a side surface of the buried conductive structure (420 [0052] is part of 400 and directly on a sidewall of 210 which is part of 200), and
wherein the second insulating liner (325) has a portion that extends onto an upper surface of the second conductive barrier (420, FIG. 1A&C, see modified FIG. 1A below).
See modified FIG. 1A below for mapping details
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Re Claim 9 Van in view of Park and Lee teaches the semiconductor device of claim 1,
wherein the buried conductive structure (Lee, 200) [0040] extends to the first surface (top) of the substrate (100) through the isolation insulating layer (130), and
wherein the buried conductive structure (200) is in contact with the power delivery structure (400) in a region adjacent to the first surface of the substrate (top of 100) of the isolation insulating layer (130, FIG. 1A&B).
Re Claim 10 Van in view of Park and Lee teaches the semiconductor device of claim 9,
wherein an upper surface of the power delivery structure (Lee, 400) has a first region (see image below claim 8 for regions) in contact with the bottom surface of the buried conductive structure (200), and a second region that is in contact with the isolation insulating layer (all of 400 is in mechanical contact with 130, FIG. 1A&B).
Re Claim 11 Van in view of Park and Lee teaches the semiconductor device of claim 1, further comprising:
a plurality of channel layers (Van, 126) spaced apart from each other in a direction (Z-axis) perpendicular to the first surface of the substrate (top of 102) on the fin-type active pattern (109),
wherein the gate structure (122) [0027] comprises a gate electrode (121) on the plurality of channel layers (126) and extending in the second direction (Y-axis), and a gate insulating layer (123) between the plurality of channel layers (126) and the gate electrode (121, FIG. 1A-C & FIG. 2).
Re Claim 12 Van in view of Park and Lee teaches the semiconductor device of claim 1, wherein the power delivery structure (Van, 116) [0028] comprises a through-via structure (FIG. 1A).
Re Claim 13 Van in view of Park and Lee teaches the semiconductor device of claim 1, wherein the power delivery structure (116) comprises a rail structure that extends in the first direction (X-axis, FIG. 2).
Claims 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Van et al. (US 20220077062 A1, IDS) in view of Park et al. (US 20160351472 A1).
Re Claim 14 Van teaches a semiconductor device (FIG. 1A-C), comprising:
a substrate (102) [0023] having first (top) and second (bottom) surfaces opposing each other, that extends in a first direction, and comprising a fin-type active pattern (109) [0024] defined by an isolation insulating layer (118) [0022];
a source/drain region (124a/b) [0025] on the fin-type active pattern (109);
an interlayer insulating layer (130) [0022] on the isolation insulating layer (118) and on the source/drain regions (124a/b);
a contact structure (131) [0028] that penetrates the interlayer insulating layer (130) and is electrically connected to the source/drain regions (131 is directly connected to 124b, and 124a and 124b are electrically connected since they are part of same transistor, 131 is therefore electrically connected to 124a and 124b);
a first wiring portion (132) [0028] on the interlayer insulating layer (130) and electrically connected to the contact structure (131);
a buried conductive structure (128a) [0032] in the interlayer insulating layer (130) and the isolation insulating layer (118), electrically connected to the contact structure (131, 128a and 131 are both electrically connected to 124a/b), and having a bottom surface that penetrates the substrate (102) and spaced apart from the second surface (bottom) of the substrate; and
a second wiring portion (116) [0028] on the second surface (bottom) of the substrate (102) and having a power delivery structure (116) electrically connected to the bottom surface of the buried conductive structure (116 and 128a are both connected to 114a [0028], and 128a and 116 are therefore electrically connected);
wherein the buried conductive structure (128a, FIG. 6B) comprises a first contact plug (606 in 130 region) [0040], a first conductive barrier (608 in 130 region) on a side surface of the first contact plug (606 in 130 region), and
wherein the power delivery structure (116) comprises a second contact plug (606 in 102 region) [0068], and a second conductive barrier (608 in 102 region) on a side surface and an upper surface of the second contact plug (606 in 102 region, FIG. 6B).
Van does not teach a first insulating liner on the first conductive barrier, and
the power delivery structure is in direct contact with a bottom surface of the first contact plug.
Park teaches a first insulating liner (40) [0042] on the first conductive barrier (32) [0034], and
the power delivery structure (60 & 70) [0043] is in direct contact with a bottom surface of the first contact plug (32, [0034], FIG. 6).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Park into the structure of Van since Park teaches a semiconductor structure with conductive lines integrated through the substrate.
The ordinary artisan would have been motivated to modify Park in combination with Van in the above manner for the motivation of optimally integrating the insulating liner and conductive lines in a vertical manner to increase storage capacity in the device. [0003] states, “Semiconductor dies are vertically stacked to form a three-dimensional (3D) package to increase storage capacity. In the 3D package, each semiconductor dies are electrically connected to each other using various electrical connection structures.”
Re Claim 15 Van in view of Park teaches the semiconductor device of claim 14,
wherein the first conductive barrier (Park, 34) [0034] is open in a side region that is adjacent to the bottom surface of the first contact plug (32), and
wherein the second conductive barrier (60) has a portion that extends along the side region of the first contact plug (32, FIG. 6).
Re Claim 16 Van in view of Park teaches the semiconductor device of claim 14, but does not explicitly teach a width of the bottom surface of the buried conductive structure is in a range of 0.3 to 1.2 times a width of an upper surface of the power delivery structure.
Van does teach a width of the bottom surface of the buried conductive structure (Van, 128a) is about 0.5 times a width of an upper surface of the power delivery structure (116, FIG. 1A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Van into the structure of Van in view of Park.
The ordinary artisan would have been motivated to modify Kim in combination with Van in view of Park in the above manner for the motivation of finding optimal widths for the top of the power delivery network and the bottom surface of the buried conductive structure.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal widths for the top surface of the power delivery network and the width of the bottom surface of the buried conductive structure.
Re Claim 17 Van in view of Park teaches the semiconductor device of claim 14,
wherein the second conductive barrier (Park, 60) has a first region in contact with the bottom surface of the first contact plug and a second region on side surfaces of the second contact plug (32), and
wherein the first region (30B are of 60) is recessed toward the bottom surface of the first contact plug (32, FIG. 6).
Re Claim 18 Van in view of Park teaches the semiconductor device of claim 14, wherein at least one of the first conductive barrier (Van, 608 in 130 region) and the second conductive barrier comprises a material selected from a group consisting of Ta, TaN, Mn, MnN, WN, Ti, and TiN [0040].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Van et al. (US 20220077062 A1, IDS) in view of Park et al. (US 20160351472 A1) as applied to claim 14 above, and further in view of Lee et al. (US 20140084375 A1).
Re Claim 19 Van in view of Park teaches the semiconductor device of claim 14,
Van in view of Park does not teach the power delivery structure further comprises a second insulating liner that is between the second conductive barrier and the substrate, and
wherein at least one of the first insulating liner and the second insulating liner comprises a material selected from a group consisting of SiO2, SiN, SiCN, SiC, SiCOH, SiON, Al2O3, and AlN.
Lee teaches the power delivery (400) [0040] structure further comprises a second insulating liner (325) [0055] that is between the second conductive barrier (420) [0052] and the substrate (100) [0053] and
wherein at least one of the first insulating liner (210) [0048] and the second insulating liner comprises a material selected from a group consisting of SiO2, SiN, SiCN, SiC, SiCOH, SiON, Al2O3, and AlN (FIG. 1A&B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Van in view of Park since Lee teaches a semiconductor device with a power delivery structure.
The ordinary artisan would have been motivated to modify Lee in combination with Van in view of Park in the above manner for the motivation of optimally integrating an insulating liner around the power structure and using silicon oxide to form the first insulating liner to increase the degree of integration in the semiconductor device. [0003] states, “Technology for forming through-silicon via (TSV) structures and back side bonding structures has been suggested to increase a degree of integration in semiconductor devices and electronic systems.”
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Van et al. (US 20220077062 A1, IDS) in view of Kim et al. (US 20210028112 A1, IDS) and Lee et al. (US 20140084375 A1) and Park et al. (US 20160351472 A1).
Re Claim 20 Van teaches a semiconductor device (FIG. 1A-C), comprising:
a substrate (102) [0023] having a first surface (top) and a second surface (bottom) opposing each other, and comprising an active region (areas between 109 regions) [0024] defined by a first isolation insulating layer (118 on outside of 109 regions) [0022];
a fin-type active pattern (109) that extends in a first direction (X-axis) on the active region and is defined by a second isolation insulating layer (108 between 109 regions);
a source/drain region (124a/b) on the fin-type active pattern (109);
a plurality of channel layers (126) [0025] that are stacked and spaced apart from each other on the fin-type active pattern (109);
a gate electrode (121) [0027] that extends across the fin-type active pattern (109) in a second direction (Y-axis) that intersects (from top-view) the first direction (X-axis), and is on the plurality of channel layers (126);
a gate insulating layer (123) [0022] between the plurality of channel layers (126) and the gate electrode (121);
an interlayer insulating layer (130) [0022] on the second isolation insulating layer (118 between 109 regions) and on the gate electrode (121) and the source/drain regions (124a/b);
a contact structure (131) [0028] that penetrates the interlayer insulating layer (130) and is electrically connected to the source/drain regions (131 is directly connected to 124b, and 124a and 124b are electrically connected since they are part of same transistor, 131 is therefore electrically connected to 124a and 124b);
a buried conductive structure (128a) [0030] electrically connected to the contact structure (131, 128a and 131 are both electrically connected to 124a/b), this is in the first isolation insulating layer (118 to left of 128a in FIG. 1A) and the second isolation insulating layer (118 between 109 regions), and extends into the substrate (102); and
a power delivery structure (116) [0028] that extends into the substrate (102) from the second surface (bottom) of the substrate and is electrically connected to a bottom surface of the buried conductive structure (116 and 128a are both connected to 114a [0028], and 128a and 116 are therefore electrically connected).
Van does not teach the second isolation insulating layer having a depth less than a depth of the first isolation insulating layer with respect to the substrate.
Kim teaches the second isolation insulating layer (162b) having a depth less than a depth of the first isolation insulating layer (162a) with respect to the substrate (101, [0025], FIG. 2).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Van since Kim teaches a semiconductor device containing insulation layers around the fins.
The ordinary artisan would have been motivated to modify Kim in combination with Van in the above manner for the motivation of optimally forming isolation regions to allow one to reach ideal device architecture as device size continues to reduce while maintaining transistor performance. [0004] states, “However, with higher integration of semiconductor devices, when the size of an active element such as a transistor is reduced, or a line width and/or pitch of metal wiring is reduced, there may be problems in which undesired short-circuits may occur in interconnecting the metal wiring and the active regions.”
Van in view of Kim does not teach the buried conductive structure comprises a first contact plug, a first conductive barrier on a side surface of the first contact plug, and a first insulating liner on the first conductive barrier, and
wherein the power delivery structure comprises a second contact plug, a second conductive barrier on a side surface and an upper surface of the second contact plug, and a second insulating liner between the second conductive barrier and the substrate.
Lee teaches the buried conductive structure (200) [0040] comprises a first contact plug (240) [0047], a first conductive barrier (220) [0048] on a side surface of the first contact plug (240), and a first insulating liner (210) [0048] on the first conductive barrier (220), and
wherein the power delivery structure (400) [0040] comprises a second contact plug (440) [0051], a second conductive barrier (420) [0052] on a side surface and an upper surface (FIG. 1B) of the second contact plug (440), and a second insulating liner (325) [0055] between the second conductive barrier (420) and the substrate (100, [0053], FIG. 1A&B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Van in view of Kim since Lee teaches a semiconductor device with a power delivery structure.
The ordinary artisan would have been motivated to modify Lee in combination with Van in view of Kim in the above manner for the motivation of optimally integrating a conductive structure and a power structure to increase the degree of integration in the semiconductor device. [0003] states, “Technology for forming through-silicon via (TSV) structures and back side bonding structures has been suggested to increase a degree of integration in semiconductor devices and electronic systems.”
Van in view of Kim and Lee does not teach the second conductive barrier is in direct contact with a bottom surface of the first contact plug.
Park teaches the second conductive barrier (60) [0043] is in direct contact with a bottom surface of the first contact plug (32, [0034], FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Van in view of Kim and Lee since Park teaches a semiconductor device with a power delivery structure.
The ordinary artisan would have been motivated to modify Park in combination with Van in view of Kim and Lee in the above manner for the motivation of optimally integrating the buried conductive structure and power structure into the semiconductor device to increase the device’s storage capacity. [0003] states, “Semiconductor dies are vertically stacked to form a three-dimensional (3D) package to increase storage capacity.”
Conclusion
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/16/26