Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, e.g. claims 1-8, 17-18 and 20, in the reply filed on January 9, 2016 is acknowledged. Please note that claim 19 is withdrawn from further consideration as being drawn to a nonelected Species. See Restriction Requirement mailed on December 30, 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 17-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shepard et al. (US 2015/0214384).
Regarding claim 1, Shepard discloses a structure comprising:
a semiconductor layer (101) [Fig. 1]; and
a transistor including, within the semiconductor layer (101):
a channel region (106) [Fig. 1];
a drain region (108) and a source region (108) above the channel region [Fig. 1];
a first gate region (Bottom p-Gate 104) below the channel region [Fig. 1]; and
a second gate region (107) above the channel region positioned laterally between the drain region (108) and the source region (108) [Fig. 1], wherein the first gate region (104) underlies the drain region (108) and is offset (horizontally and/or vertically offset) from the source region (108) and at least a portion of the second gate region (107) adjacent to the source region (108) [Fig. 1].
Regarding claim 2, Shepard discloses isolation structures (STI) between the second gate region (Top Gate p+ 107) and the source region (108) and the drain region (108) [Fig. 1].
Regarding claim 3, Shepard discloses wherein the first gate region (104) is completely offset (vertically offset) from the source region (108) and the second gate region (107) and has an end (interface between 104 and 105) below an isolation structure (STI) between the second gate region (consider portion of the M-shaped region 107 sandwiched between adjacent STI regions and positioned above PW 105) and the drain region (108) [Fig. 1].
Regarding claim 4, Shepard discloses wherein the first gate region (104) only partially underlies the second gate region (M-shaped region 107) and has an end (interface between 104 and 105) below the second gate region (consider portion of the M-shaped region 107 sandwiched between adjacent STI regions and positioned above PW 105) [Fig. 1].
Regarding claim 5, Shepard discloses wherein the transistor further includes a gate link-up region (PW 105) in the semiconductor layer immediately adjacent to the first gate region (104), positioned laterally immediately adjacent to the channel region (106), and further separated from the drain region (108) by an isolation structure (STI) [Fig. 1].
Regarding claim 17, Shepard discloses a method comprising:
providing a semiconductor layer (101) [Fig. 1]; and
forming a transistor that includes, within the semiconductor layer:
a channel region (106) [Fig. 1];
a drain region (108) and a source region (108) above the channel region [Fig. 1];
a first gate region (104) below the channel region [Fig. 1]; and
a second gate region (Top Gate p+ 107) above the channel region positioned laterally between the drain region (108) and the source region (108) [Fig. 1],
wherein the first gate region (104) underlies the drain region (108) and is offset (horizontally and/or vertically offset) from the source region (108) and at least a portion of the second gate region (Top Gate p+ 107) adjacent to the source region (108) [Fig. 1].
Regarding claim 18, Shepard discloses:
wherein the semiconductor layer (101) includes a semiconductor substrate (P-sub) [Fig. 1],
wherein the method includes forming a buried well region (103) in the semiconductor substrate [Fig. 1], and
wherein the forming of the transistor includes forming the transistor above the buried well region (103) [Fig. 1].
Regarding claim 20, Shepard discloses wherein the first gate region (104) has an end (interface between 104 and 105) either below an isolation structure (STI) between the drain region (108) and the second gate region (portion of the M-shaped region 107 sandwiched between adjacent STI regions and positioned above PW 105) or below the second gate region [Fig. 1].
Claims 1-5, 17-18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Koga (US 2024/0332430).
Regarding claim 1, Koga discloses a structure comprising:
a semiconductor layer (41/42) [Fig. 3]; and
a transistor including, within the semiconductor layer (41/42):
a channel region (12/13) [Fig. 3 and paragraph 0061];
a drain region (11) and a source region (10) above the channel region [Fig. 3];
a first gate region (7,71,72) below the channel region [Fig. 3]; and
a second gate region (8) above the channel region positioned laterally between the drain region (108) and the source region (108) [Fig. 3], wherein the first gate region (7,71,72) underlies the drain region (11) and is offset (horizontally and/or vertically offset) from the source region (7, 71,72) and at least a portion of the second gate region (8) adjacent to the source region (10) [Fig. 3].
Regarding claim 2, Koga discloses isolation structures (14) between the second gate region (8) and the source region (10) and the drain region (11) [Fig. 3].
Regarding claim 3, Koga discloses wherein the first gate region (72) is completely offset (vertically and/or horizontally offset, respectively) from the source region (10) and the second gate region (8) and has an end (interface between portion 75 and portion 73, or between portion 75 and region 13) below an isolation structure (14) between the second gate region (8) and the drain region (11) [Fig. 3].
Regarding claim 4, Koga discloses wherein the first gate region (71 or 72) only partially underlies the second gate region (8) and has an end (interface between 71 and 72) below the second gate region (8) [Fig. 3].
Regarding claim 5, Koga discloses wherein the transistor further includes a gate link-up region (77) in the semiconductor layer immediately adjacent to the first gate region (7,71,72), positioned laterally immediately adjacent to the channel region (12), and further separated from the drain region (11) by an isolation structure (14) [Fig. 3].
Regarding claim 17, Koga discloses a method comprising:
providing a semiconductor layer (41/42) [Fig. 3]; and
forming a transistor that includes, within the semiconductor layer:
a channel region (12/13) [Fig. 3 and paragraph 0061];
a drain region (11) and a source region (10) above the channel region [Fig. 3];
a first gate region (7,71,72) below the channel region [Fig. 3]; and
a second gate region (8) above the channel region positioned laterally between the drain region (11) and the source region (10) [Fig. 3],
wherein the first gate region (7,71,72) underlies the drain region (11) and is offset (horizontally and/or vertically offset) from the source region (10) and at least a portion of the second gate region (8) adjacent to the source region (10) [Fig. 3].
Regarding claim 18, Koga discloses:
wherein the semiconductor layer includes a semiconductor substrate (41/42) [Fig. 3],
wherein the method includes forming a buried well region (6) in the semiconductor substrate [Fig. 3], and
wherein the forming of the transistor includes forming the transistor above the buried well region (3) [Fig. 3].
Regarding claim 20, Koga discloses wherein the first gate region (7,71,72) has an end (interface between 71 and 72) either below an isolation structure (14) between the drain region (11) and the second gate region (8) or below the second gate region (8) [Fig. 3].
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Candra et al. (US 2012/0292669) discloses a first and second gate regions (22/30), and a channel (26) in Figure 1.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815