Prosecution Insights
Last updated: April 19, 2026
Application No. 18/364,893

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Aug 03, 2023
Examiner
FAN, SU JYA
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toshiba Electronic Devices & Storage Corporation
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
86%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
700 granted / 929 resolved
+7.3% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
53 currently pending
Career history
982
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
24.9%
-15.1% vs TC avg
§112
19.7%
-20.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 929 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant’s election without traverse of species A, fig. 4, claims 1-7 and new claims 11-17, in the reply filed on 12/9/25 is acknowledged. Claims 8-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/9/25. Relevant Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kent Larson, "Low Temperature Characteristics of Silicones": pages 1-25 (Retrieved from https://www.electronics.org/system/files/technical_resource/E14%26S05-04.pdf) "Typical values of PBT", SpecialChem: page 1 (Retrieved from https://www.specialchem.com/plastics/guide/polybutylene-terephthalate-pbt-plastic) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hitomi et al., US Publication No. 2022/0165700 (from the IDS) in view of Kaji et al., US Publication No. 2022/0223546 A1. Hitomi teaches: 1. A semiconductor device comprising (see fig. 1): a base plate (37); a substrate (10) provided on the base plate, the substrate having a first metal layer (e.g. 12 right) and a second metal layer (e.g. 12 left) on a surface thereof; a semiconductor chip (15) provided on the first metal layer, the semiconductor chip including an upper electrode (17), a lower electrode (18) connected to the first metal layer, and a semiconductor layer (e.g. para. [0042]) provided between the upper electrode and the lower electrode; a bonding wire (20) having a first end portion (e.g. right end) and a second end portion (e.g. left end), the first end portion being connected to the upper electrode (17), and the second end portion being connected to the second metal layer (e.g. 12 left); a first resin layer (40) covering the substrate, the semiconductor chip, and the bonding wire, the first resin layer containing a first resin; a second resin layer (33) covering at least a part of a bonding portion between the first end portion (e.g. right end of 20) and the upper electrode (17), the second resin layer containing a second resin having a Young's modulus higher than a Young's modulus of the first resin (e.g. para. [0055], [0061]); and a frame body (38) surrounding the substrate, the first resin layer, and the third resin layer. See Hitomi at para. [0001] – [0119], figs. 1-31. Regarding claim 1: Hitomi does not expressly teach: a third resin layer provided on the first resin layer so as to be in contact with the first resin layer, the third resin layer containing a third resin having a moisture permeability lower than a moisture permeability of the first resin; the frame body surrounding the third resin layer. In an analogous art, Kaji teaches: (see fig. 8) a third resin layer (91) provided on the first resin layer (77) so as to be in contact with the first resin layer, the third resin layer containing a third resin (e.g. material at para. [0049]) having a moisture permeability (e.g. para. [0050], para. [0028]) lower than a moisture permeability of the first resin (77; material at para. [0030]); a frame body (61) surrounding a substrate (21), the first resin layer (77), and the third resin layer (91), para. [0048] – [0050]. Hitomi further teaches: 2. The semiconductor device according to claim 1, wherein the Young's modulus of the second resin is equal to or more than 1000 MPa, para. [0055], [0061]. 3. The semiconductor device according to claim 1, wherein a glass transition temperature of the second resin is equal to or more than 250° C, para. [0059]. Regarding claim 4: Hitomi teaches the first resin (40 in fig. 1) comprises a silicone get at para. [0060] Kaji teaches the third resin (91 in fig. 8) comprises thermoplastic resin such as polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), polyether ether ketone (PEEK), or polytetrafluoroethylene (PTFE) at para. [0049]. One of ordinary skill in the art modifying Hitomi with Kaji to form the third resin to comprise polybutylene terephthalate (PBT) would arrive at the claimed limitation: wherein an elongation rate of the third resin (e.g. PBT) is more than an elongation rate of the first resin (e.g. silicon gel). (e.g. See properties of materials cited in the Relevant Art section above.) It is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose. “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle. 325 U.S. at 335, 65 USPQ at 301.” Kaji further teaches: 5. The semiconductor device according to claim 1, further comprising: (see fig. 8) a fourth resin layer (41) provided between the base plate (21) and the frame body (61) and bonding the base plate and the frame body, the fourth resin layer containing a fourth resin (e.g. material para. [0021]); and a fifth resin layer (51) provided between the first resin layer (77) and the fourth resin layer (41), the fifth resin layer containing a fifth resin (e.g. material at para. [0022]), para. [0048] – [0060]. Kaji is silent: the fifth resin layer containing a fifth resin having a moisture permeability lower than the moisture permeability of the first resin and a moisture permeability of the fourth resin. However, it would have been obvious to one of ordinary skill in the art to form “the fifth resin layer containing a fifth resin having a moisture permeability lower than the moisture permeability of the first resin and a moisture permeability of the fourth resin”because Kaji teaches in fig. 4 that layers (42, 52) prevent infiltration of moisture at para. [0037]; in fig. 6 that layers (43, 51) prevent infiltration of moisture at para. [0043]; in fig.7 that layers (44, 51) prevent infiltration of moisture at para. [0045]; and from the materials disclosed at para. [0021] – [0022]. Kajii further teaches: 6. The semiconductor device according to claim 5, wherein the fifth resin layer (51) is in contact with the first resin layer (77) and the fourth resin layer (41), fig. 8. 7. The semiconductor device according to claim 6, wherein the fifth resin layer (51) is provided between the frame body (61) and the first resin layer (77), and the fifth resin layer (51) covers at least a part of the substrate (21), fig. 8. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Hitomi with the teachings of Kaji because (i) “…by providing the barrier layer 91 on the sealing member 77 in a region inside the case 61, it is possible to prevent the infiltration of moisture from the upper surface of the sealing member 77, which makes it possible to prevent the deterioration of the semiconductor element, and therefore, it is possible to further improve the reliability of the semiconductor device” (e.g. Kaji at para. [0050]); and (ii) forming fourth and fifth resin layers around the case help prevent infiltration of moisture (e.g. Kaji at para. [0037], [0043], [0045]). Claim(s) 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaji et al., US Publication No. 2022/0223546 A1 in view of Hitomi et al., US Publication No. 2022/0165700 (from the IDS). Kaji teaches: 11. A semiconductor device comprising (see fig. 8): a base plate (21); a substrate (31) provided on the base plate, the substrate having a first metal layer (31A) and a second metal layer (31B) on a surface thereof; a first semiconductor chip (71 left) provided on the first metal layer (31A), a second semiconductor chip (71 right) provided on the second metal layer (31B), the second semiconductor chip including an upper electrode (e.g. upper electrode implicit at connection point to 84), a lower electrode (e.g. lower electrode implicit at interface with 81) connected to the second metal layer (31B), and a semiconductor layer (e.g. silicon at para. [0018]) provided between the upper electrode and the lower electrode; a bonding wire (84) having a first end portion (e.g. left end) and a second end portion (e.g. right end), the first end portion (e.g. left end) being connected to the upper electrode (e.g. upper electrode implicit at connection point to 84), and the second end portion (e.g. right end) being connected to a first terminal (74 right), the second semiconductor chip (71 right) being located between the first semiconductor chip (71 left) and the first terminal (74 right); a first resin layer (77) covering the substrate, the first and second semiconductor chips, and the bonding wire, the first resin layer containing a first resin; … a third resin layer (91) provided on the first resin layer so as to be in contact with the first resin layer, the third resin layer containing a third resin having a moisture permeability lower than a moisture permeability of the first resin; and a frame body (61)surrounding the substrate, the first resin layer, and the third resin layer. See Kaji at para. [0001] – [0084], figs. 1-9. Regarding claim 11: Kaji does not expressly teach: a second resin layer covering at least a part of a bonding portion between the first end portion and the upper electrode, the second resin layer containing a second resin having a Young's modulus higher than a Young's modulus of the first resin; In an analogous art, Hitomi teaches: (see fig. 1) a second resin layer (33) covering at least a part of a bonding portion between the first end portion (e.g. right end of 20) and the upper electrode (17), the second resin layer containing a second resin having a Young's modulus higher than a Young's modulus of the first resin (e.g. para. [0055], [0061]). See Hitomi at para. [0040] – [0050]. Regarding claim 12: Hitomi teaches the limitations as applied to claim 2 above. Regarding claim 13: Hitomi teaches the limitations as applied to claim 3 above. Regarding claim 14: Kaji teaches the first resin (77) comprises an electrically insulating resin such as epoxy resin, silicone resin, urethane resin, polyimide resin, polyamide resin, or acrylic resin at para. [0030]. Kaji teaches the third resin (91) comprises thermoplastic resin such as polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), polyether ether ketone (PEEK), or polytetrafluoroethylene (PTFE) at para. [0049]. One of ordinary skill in the art forming the first resin to be the material silicon resin and the third resin to be the material polybutylene terephthalate (PBT) would arrive at the claimed limitation: wherein an elongation rate of the third resin (e.g. PBT) is more than an elongation rate of the first resin (e.g. silicon gel). (e.g. See properties of materials cited in the Relevant Art section above.) It is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose. “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle. 325 U.S. at 335, 65 USPQ at 301.” Regarding claim 15: Kaji teaches the limitations as applied to claim 5 above. Regarding claim 16: Kaji teaches the limitations as applied to claim 6 above. Regarding claim 17: Kaji teaches the limitations as applied to claim 7 above. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kaji with the teachings of Hitomi because “When the power semiconductor module 1 is subjected to a heat cycle, the second resin member 33 having the second tensile elastic modulus greater than the first tensile elastic modulus of the first resin member 30 may sufficiently prevent the deformation of the conductive wire 20. The second resin member 33 may prevent the breaking of the first resin member 30 caused by the deformation of the conductive wire 20.” See Hitomi at para. [0058]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michele Fan/ Primary Examiner, Art Unit 2818 23 February 2026
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Prosecution Timeline

Aug 03, 2023
Application Filed
Feb 23, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
86%
With Interview (+11.2%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 929 resolved cases by this examiner. Grant probability derived from career allow rate.

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