DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 & 10 are rejected under 35 U.S.C. 103 as being unpatentable over (CN-10-4637968) by Zhao et al (“Zhao”; part of Applicant’s IDS) in view of (US-2019/0067345) by Qi et al (“Qi”).
Regarding claim 1, Zhao discloses in FIG. 13 and related text, e.g., a semiconductor device, comprising:
a substrate (100) defining a pixel area (directly under 115);
a trench fill structure (109/110) formed in the substrate in the pixel area;
a buffer dielectric layer (113; anti-reflective layer is a dielectric; and it is a buffer between layers above and below) formed over a surface of the substrate in the pixel area, the buffer dielectric layer defining a first opening (has 114 in it), which at least exposes a portion of the substrate surrounding the trench fill structure (the right 114 at bottom corners exposes the substrate around the trench fill 109/110); and a metal grid layer (114) formed on the buffer dielectric layer, the metal grid layer filling the first opening to at least directly contact with and electrically connect to the exposed portion of the substrate (see FIG. 13; there is direct contact between 114 and substrate 100; hence, “electrically connect”, since one is metal and the other is semiconductor)
Zhao does not explicitly state “the metal grid layer … to apply a voltage to the substrate through the metal grid layer”.
To elaborate briefly on the above, Zhao likely has such feature in his device. It is a notoriously well-known in the electrical arts that one does not leave “floating metal” (metal with no voltage applied to it), due to various negative consequences such inattention will cause. For example, loose charges may collect on a “floating metal”, and such loose charges may cause a multitude of electrical issues in underlying electrical circuit. However, to eliminate all doubt, a teaching by Qi is provided.
Qi discloses in FIG. 8 and related text, e.g., “the metal grid layer (801) … to apply a voltage (par. 43; 801 is connected to bonding pad 601 to apply voltage) to the substrate through the metal grid layer”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Zhao with ““the metal grid layer … to apply a voltage” as taught by Qi, in order to provide an additional function of being a carrier of electrical potential (par. 43).
When these specific teachings of Qi are applied to device of Zhao it will result in “the metal grid layer … to apply a voltage to the substrate through the metal grid layer”, since Zhao teaches direct contact between substrate and grid (as was explained above and Qi teaches to connect the grid to a bonding pad, in order to carry potential.
Regarding claim 2, the combined device of Zhao and Qi disclose in cited figures and related text, e.g., wherein both a portion of the substrate surrounding a top edge of the trench fill structure and an entire top surface of the trench fill structure are exposed in the first opening (see FIG. 13), the metal grid layer (right 114) being in direct contact with and electrically connected to both the portion of the substrate surrounding the top edge of the trench fill structure and the entire top surface of the trench fill structure (see FIG. 13).
Regarding claim 3, Zhao and Qi disclose in cited figures and related text, e.g., wherein part of the top surface of the trench fill structure is exposed in the first opening (the whole is exposed; meaning, all the parts are exposed; thus meeting limitations), the metal grid layer being in direct contact with and electrically connected to the part of the top surface of the trench fill structure (see FIG. 13).
Regarding claim 4, Zhao and Qi disclose in cited figures and related text, e.g., wherein only a portion of the substrate surrounding a top edge of the trench fill structure is exposed in the first opening (see FIG. 13; only a small portion of substrate is exposed), the metal grid layer being in direct contact with and electrically connected to the portion of the substrate surrounding the top edge of the trench fill structure.
Regarding claim 5, Zhao and Qi disclose in cited figures and related text, e.g., wherein the metal grid layer is in direct contact with and electrically connected to the exposed portion of the substrate (see FIG. 13) to apply a bias voltage to a backside of the substrate (these limitations carry no patentable weight in a claim drawn to device; Applicant is claiming a “method of operating” limitations; these are not structural; one can apply any voltage they want to the structure [Wingdings font/0xE0] whether bias, or AC, or anything a person wants; that would not change the structure, and thus is not given patentable weight).
Regarding claim 6, Zhao and Qi disclose in cited figures and related text, e.g., wherein the trench fill structure comprises an isolation oxide layer (109) covering a surface of the trench in the substrate (see FIG. 13) and a filler material (110) that fills the trench, the isolation oxide layer at least located between a sidewall of the filler material and the substrate (see FIG. 13).
Regarding claim 10, Zhao and Qi disclose in cited figures and related text, e.g., wherein the metal grid layer extends to a peripheral region of the substrate (as shown by Qi in FIG. 8), and wherein the metal grid layer includes a contact portion configured for electrical connection to an external voltage source in the peripheral region (specifically to pad 601, as shown in FIG. 8).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over (CN-10-4637968) by Zhao et al (“Zhao”; part of Applicant’s IDS) in view of (US-2019/0067345) by Qi et al (“Qi”) as applied to claims above, and further in view of (US-20210066225) by Chou et al (“Chou”).
Regarding claim 7, Zhao and Qi disclose in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, except wherein the substrate further defines a pad area lateral to the pixel area, and wherein a metal interconnect structure and a plug structure above the metal interconnect structure are formed in the substrate in the pad area, the plug structure electrically connected at a bottom thereof to the metal interconnect structure.
Zhao is silent about pad area and related limitations. However, Chou fixes the deficiency.
Chou discloses in FIG. 5 and related text, e.g., wherein the substrate further defines a pad area (FIG. 5) lateral to the pixel area (see FIG. 3; pixel area is shown to the side of pad area), and wherein a metal interconnect structure (108a/108, etc.) and a plug structure (contains 116) above the metal interconnect structure are formed in the substrate in the pad area, the plug structure electrically connected at a bottom thereof to the metal interconnect structure (see FIG. 5; direct physical/electrical connection between the two).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Zhao and Qi with “wherein the substrate further defines a pad area lateral to the pixel area, and wherein a metal interconnect structure and a plug structure above the metal interconnect structure are formed in the substrate in the pad area, the plug structure electrically connected at a bottom thereof to the metal interconnect structure”, as taught by Chou, since applying a known technique (technique of Chou exactly how to form bond pads) to a known device ready for improvement (device of Zhao, which does not teach how to form pads; and thus would benefit from having outside connection for the chip) to yield predictable results (results are predictable, because both references deal with back side illuminated imagers; results are also predictable because Zhao already has “trenches” with “insulator” and “conductive layer” inside it, between pixels; Chou teaches a similar structure (“trenches” with “insulator” and “conductive layer” inside it) for the pad area; hence, results are predictable) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Regarding claim 8, the combined device of Zhao, Qi and Chou disclose in cited figures and related text, e.g., wherein the trench fill structure comprises a first conductive metal layer in a trench formed in the pixel area (110 of Zhao), and the plug structure comprises: an isolation oxide layer (115; can be oxide; see par. 35) covering a sidewall of a through-hole in which a top surface of the metal interconnect structure is partially exposed (through-hole goes down all the way to 108a/108; and that is where “top surface” of it is exposed); and a first conductive metal layer (116; par. 48 lists some materials for it) that fills the through-hole.
Regarding claim 9, the combined device of Zhao, Qi and Chou disclose in cited figures and related text, e.g., wherein the buffer dielectric layer also covers a surface of the substrate in the pad area (entirety of Chou’s FIG. 5 is being defined as “pad area”; presence of 118a/118b/118c is noted; the materials for these 3 layers are listed in par. 44, and they are some of the same ones as the ones listed by Zhao for his buffer dielectric layer; hence, Chou shows “buffer … layer” that “covers a … substrate in a pad area”, as required by claim) and defines a second opening (together with 115 it defines a second opening; the claim preamble says “comprising” not “consisting”; hence, this portion of claim is not limited to just “buffer dielectric layer” defining the opening; nothing prevents it being one of the layers defining an opening) in which a top surface of the plug structure is partially exposed (118a shows an opening, through which 116 comes through, and top surface thereof is being exposed), and wherein a pad structure (portion of 116 directly above 118a and directly in the top of the opening; keep in mind that in MPEP 2144.04 it is made clear that making things “separable” or “integral” are some of the well-recognized rationales for obviousness; so the fact that the Chou has it as a single piece and Applicant has it as 2 pieces, these are obvious over each other, as MPEP makes clear) is formed on the buffer dielectric layer in the pad area and completely fills the second opening (as was defined above; defined by 118 and 115; 116 completely fills it) so as to be electrically connected to the exposed portion of the top surface of the plug structure (it is one piece, as was described above; could be 2, as was described above; hence, meeting limitations).
Response to Arguments
Applicant’s arguments with respect to above claims have been considered but are moot because the arguments do not apply to the current rejection.
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
04/04/26
/Mounir S Amer/Primary Examiner, Art Unit 2818