Prosecution Insights
Last updated: August 16, 2026
Application No. 18/364,921

SEMICONDUCTOR DEVICE

Non-Final OA §112
Filed
Aug 03, 2023
Priority
Dec 02, 2019 — CN 201911216003.8 +2 more
Examiner
BELOUSOV, ALEXANDER
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
OA Round
3 (Non-Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
396 granted / 519 resolved
+8.3% vs TC avg
Strong +16% interview lift
Without
With
+16.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
22 currently pending
Career history
545
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
61.9%
+21.9% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 519 resolved cases

Office Action

§112
DETAILED ACTION Response to Arguments Applicant’s arguments with respect to above claims have been considered but are moot because the arguments do not apply to the current rejection. Specifically, the current Action contains only 112 rejections. The Applicant’s arguments do not apply to 112 rejections presented below. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1 & 3-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. To elaborate briefly on the above, the amended claim 1 requires the following: “a trench fill structure (Applicant’s FIG. 6, 212; this is the figure specified by Applicant as applying to amended claim 1, on Page 4 of Applicant’s Remarks, near top of the page) formed in the substrate in the pixel area (21); a buffer dielectric layer (25) formed over a surface of the substrate in the pixel area (21), the buffer dielectric layer defining a first opening (FIG. 5e, 2133; still present, but unmarked, in FIG. 6), which at least exposes a portion of the substrate surrounding the trench fill structure (see FIG. 6); and a metal grid layer (217) …, the metal grid layer filling the first opening to at least directly contact with and electrically connect to the exposed portion of the substrate (see FIG. 6) …, wherein the first opening exposes at most a portion of the top surface of the trench fill structure, and wherein the metal grid layer is electrically connected only to that exposed portion”. The issue that resulted in 112, 1st (New Matter) rejection are the words “only to that exposed portion”. That is directly contradicted by FIG. 6. As can be clearly seen in FIG. 6, each of the three “metal grid layer” (217) elements shown in FIG. 6 is “electrically connected” to at least two exposed portions of substrate (on each side of “trench fill structure” (212)). It gets worse. In reality, the three “metal grid layer” elements are all a single metal grid layer (this is just a side cut view, which makes them appear as multiple elements; it is all a single grid, as the name implies). This grid will have at least one connection to each and every single pixel (as shown in FIG. 6; pixels are located between “trench fill” 212 elements). Hence, “a first opening” in each and every single pixel has such a connection. Therefore, “the metal grid layer” being “electrically connected only to that exposed portion” is physically impossible, and is directly contradicted by teachings of FIG. 6. In regards to Prior Art rejections, it is impossible to write one. Examiner would have to find Art that teaches a “metal grid layer”, located over “pixel area”, but inside the entire pixel area, the “metal grid layer” electrically connects to one and only one pixel. There is no such Art. The whole point of having a pixel array is to have consistent and repeatable architecture over all pixels of the same type. So, this rejection contains only the 112, 1st rejections seen above. Conclusion Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Alexander Belousov/Patent Examiner, Art Unit 2894 07/11/26 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Aug 03, 2023
Application Filed
Oct 02, 2025
Non-Final Rejection mailed — §112
Dec 17, 2025
Response Filed
Apr 08, 2026
Final Rejection mailed — §112
Jun 23, 2026
Request for Continued Examination
Jun 26, 2026
Response after Non-Final Action
Jul 16, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
3y 6m to grant Granted Aug 11, 2026
Patent 12707746
IMAGE SENSOR AND METHOD OF FABRICATING THE SAME
3y 5m to grant Granted Aug 11, 2026
Patent 12708042
SEMICONDUCTOR DEVICE WITH VOLUMETRICALLY-EXPANDED SIDE-CONNECTED INTERCONNECTS
2y 11m to grant Granted Aug 11, 2026
Patent 12701797
METHOD OF THINNING A SEMICONDUCTOR SUBSTRATE TO HIGH EVENNESS AND SEMICONDUCTOR SUBSTRATE HAVING A DEVICE LAYER OF HIGH EVENNESS
5y 1m to grant Granted Aug 04, 2026
Patent 12701798
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
3y 7m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
93%
With Interview (+16.5%)
2y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 519 resolved cases by this examiner. Grant probability derived from career allowance rate.

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