DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bu et al. (2008/0308872).
Re claim 1, Bu teaches a method of fabricating a semiconductor apparatus (Figs. 1-10), comprising: providing a semiconductor substrate (10); forming a first gate stack [68] and a second gate stack [68] on a first semiconductor device region (100) and a second semiconductor device region (200), respectively, of the semiconductor substrate (10), the first gate stack [68] comprising a first gate (44A) and a first gate dielectric (40A), and the second gate stack [68] comprising a second gate (44B) and a second gate dielectric (40B); performing a first deposition operation [69] of depositing a first dielectric material (“nitride”) to form a first dielectric material [69] over a top surface and sidewalls of the first gate stack [68] and over a top surface and sidewalls of the second gate stack (Fig. 2); removing portions of the first dielectric material (“nitride”) over the sidewalls of the second gate stack (Fig. 6); and performing a second deposition operation [87] of depositing the first dielectric material (“nitride”) over the top surface and sidewalls of the first gate stack [87] and over the top surface and sidewalls of the second gate stack [87] to form the first dielectric material over the sidewalls of the first gate stack and the sidewalls of the second gate stack (Fig. 10), so that a first gate spacer (50’, 64, 70) formed over the sidewalls of the first gate stack (44A, [87]) has a thickness larger (Fig. 10) than that of a second gate spacer (64’, 70’) formed over the sidewalls of the second gate stack (44B, [87]).
Re claim 2, Bu teaches the method of claim 1, wherein the first semiconductor device region (100) and the second semiconductor device region (200) comprise first active areas [84] and second active areas [75-77], respectively, wherein the first active areas [84] are located on opposite sides of the first gate stack [84, 87], and the second active areas [75-77] are located on opposite sides of the second gate stack [75-77, 87], and wherein the first deposition operation [69] further comprises: depositing the first dielectric material over top surfaces of the first active areas and over top surfaces of the second active areas [69, 75-77, 87]. Re claim 3, Bu teaches the method of claim 2, wherein removing the portions of the first dielectric material over the sidewalls of the second gate stack [78] comprises: forming a mask layer over the first semiconductor device region (100); and removing the portions of the first dielectric material over the sidewalls of the second gate stack (Figs. 5-6). Re claim 4, Bu teaches the method of claim 3, wherein the second deposition operation comprises: after removing the mask layer, depositing the first dielectric material over the top surfaces of the first active areas and the top surface and sidewalls of the first gate stack and over the top surfaces of the second active areas and the top surface and sidewalls of the second gate stack (Figs. 7-9); and removing portions of the first dielectric material over the top surfaces of the first active areas and the top surface of the first gate stack and portions of the first dielectric material over the top surfaces of the second active areas and the top surface of the second gate stack (Figs. 7-10).
Re claim 5, Bu teaches the method of claim 1, wherein, before removing the portions of the first dielectric material over the sidewalls of the second gate stack, the method further comprises: removing portions of the first dielectric material over top surfaces of first active areas of the first semiconductor device region and a top surface of the first gate stack and portions of the first dielectric material over top surfaces of second active areas of the second semiconductor device region and a top surface of the second gate stack (Figs. 6-7).
Re claim 6, Bu teaches the method of claim 5, wherein removing the portions of the first dielectric material over the sidewalls of the second gate stack comprises: forming a mask layer over the first semiconductor device region [81-86]; and removing the portions of the first dielectric material over the sidewalls of the second gate stack [81-86]. Re claim 7, Bu teaches the method of claim 6, wherein the second deposition operation comprises: after removing the mask layer, depositing the first dielectric material over the top surfaces of the first active areas and the top surface and sidewalls of the first gate stack and over the top surfaces of the second active areas and the top surface and sidewalls of the second gate stack [84-87]; and removing portions of the first dielectric material over the top surfaces of the first active areas and the top surface of the first gate stack and portions of the first dielectric material over the top surfaces of the second active areas and the top surface of the second gate stack [84-87].
Re claim 8, Bu teaches the method of claim 1, wherein, before the first deposition operation, the method further comprises depositing a second dielectric material (“oxide”, [87]) different from the first dielectric material (“nitride”, [87]) over the first semiconductor device region (100) and the second semiconductor device region (200).
Re claim 9, Bu teaches the method of claim 8, wherein the first dielectric material (“nitride”) comprises silicon nitride [87], and the second dielectric material (“oxide”) comprises silicon oxide [87]. Claim(s) 11 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bu et al. (2008/0308872). Re claim 11, Bu teaches a semiconductor apparatus (Fig. 10), comprising: a first semiconductor device (100), comprising a first semiconductor device region of a semiconductor substrate (10), a first gate stack [87], and a first gate spacer (50’, 64, 70); and a second semiconductor device (200), comprising a second semiconductor device region of the semiconductor substrate (10), a second gate stack [87], and a second gate spacer (64’, 70’), wherein a number of layers (“2”) of a first dielectric material (“nitride”, 50’ and 70) in the first gate spacer (50’, 64, 70) is larger than a number of layers (“1”) of the first dielectric material (“nitride”, 70) in the second gate spacer (64’, 70’) by one, and a thickness (Fig. 10) of the first gate spacer (50’, 64, 70) is larger than that of the second gate spacer (64’, 70’).
Re claim 17, Bu teaches the semiconductor apparatus of claim 11, further comprising an isolating structure (20) between the first semiconductor device region (100) and the second semiconductor device region (200).
Re claim 18, Bu teaches the semiconductor apparatus of claim 17, wherein the isolating structure (20) comprises oxide [82].
Re claim 19, Bu teaches the semiconductor apparatus of claim 11, wherein an operating voltage of the first semiconductor device (100) is larger than that of the second semiconductor device (200, [63]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Bu et al. (2008/0308872) in view of the following reasons. Re claim 10, Bu teaches the method of claim 9.
Bu does not explicitly teach wherein the first dielectric material deposited during the first deposition operation has a first thickness larger than a second thickness of the first dielectric material deposited during the second deposition operation.
However, Applicant has not shown wherein the first dielectric material deposited during the first deposition operation has a first thickness larger than a second thickness of the first dielectric material deposited during the second deposition operation has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the dielectric thicknesses so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Bu et al. (2008/0308872) in view of the following reasons. Re claim 12, Bu teaches the semiconductor apparatus of claim 11, wherein the first gate spacer (50’, 64, 70) comprises two dielectric layers (50’, 70) formed of the first dielectric material (“nitride”) and the second gate spacer (64’, 70’) comprises one dielectric layer (70’) formed of the first dielectric material (“nitride”), and the thickness of the first gate spacer larger than that of the second gate spacer (Fig. 10), and wherein the two dielectric layers (50’, 70) comprise a first dielectric layer (50’) proximate to the first gate stack [87] and a second dielectric layer (70) further away from the first gate stack [87]. Bu does not explicitly teach a thickness of the first dielectric layer is larger than that of the second dielectric layer. However, Applicant has not shown wherein a thickness of the first dielectric layer is larger than that of the second dielectric layer has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the dielectric thicknesses so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Re claim 13, Bu teaches the semiconductor apparatus of claim 12, wherein the first gate spacer (50’, 64, 70) comprises a second dielectric material (“oxide”), which is different from the first dielectric material (“nitride”) and is disposed (60) between the two dielectric layers (50’, 70) and the first gate stack [87], and the second gate spacer (64’, 70’) comprises the second dielectric material (“oxide”) disposed between the one dielectric layer (70’) and the second gate stack [87].
Re claim 14, Bu teaches the semiconductor apparatus of claim 13, wherein the first dielectric material (“nitride”) comprises silicon nitride [87], and the second dielectric material (“oxide”) comprises silicon oxide [87].
Re claim 15, Bu teaches the semiconductor apparatus of claim 14. Bu does not explicitly teach wherein the thickness of the first dielectric layer is in a range of 40-60 nm, and the thickness of the second dielectric layer is in a range of 20-35 nm. However, Applicant has not shown wherein the thickness of the first dielectric layer is in a range of 40-60 nm, and the thickness of the second dielectric layer is in a range of 20-35 nm has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the dielectric thicknesses so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Re claim 16, Bu teaches the semiconductor apparatus of claim 15, wherein the second dielectric material has a thickness in a range of 6-15 nm [86-87].
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Bu et al. (2008/0308872) in view of Kim et al. (2017/0162576).
Re claim 20, Bu teaches a first semiconductor device (Fig. 10), comprising a first semiconductor device region (100) of a semiconductor substrate (10), a first gate stack [87], and a first gate spacer (50’, 64, 70); and a second semiconductor device (200), comprising a second semiconductor device region (200) of the semiconductor substrate (10), a second gate stack [87], and a second gate spacer (64’, 70’), wherein a number of layers (“2”) of a first dielectric material (“nitride”, 50’ and 70) in the first gate spacer (50’, 64, 70) is larger than a number of layers (“1”) of the first dielectric material (“nitride”, 70) in the second gate spacer (64’, 70’) by one, and a thickness (Fig. 10) of the first gate spacer (50’, 64, 70) is larger than that of the second gate spacer (64’, 70’).
Bu does not explicitly teach a memory system, comprising: a memory; and a memory controller coupled to the memory and configured to control operations of the memory, wherein at least one of the memory and the memory controller comprises a semiconductor apparatus. Kim teaches a semiconductor device (Fig. 3, 21) comprising a memory system (1100), comprising: a memory (1130); and a memory controller (1110) coupled to the memory (1130) and configured to control operations of the memory [239-244], wherein at least one of the memory (1130) and the memory controller (1110) comprises a semiconductor apparatus [243].
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Bu as taught by Kim since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897