Prosecution Insights
Last updated: October 02, 2026

Examiner: BOWEN, ADAM S

Tech Center 2800 • Art Units: 2897

This examiner grants 96% of resolved cases

Analysis

Adam S. Bowen serves in Tech Center 2800 and Art Unit 2897. The examiner has a record of 744 resolved cases. These cases result in an allowance rate of 96.5%, which indicates the frequency of grants for applications reaching a final disposition. The median days to allowance is 645, providing a benchmark for the expected duration of the prosecution cycle. Practitioners can use the 96.5% allowance rate to assess the likelihood of a successful outcome when an application is assigned to this examiner.

The data shows an interview lift of 2.4%. This lift suggests that while interviews are a tool for communication, the 96.5% allowance rate is already achieved in the majority of the 744 resolved cases. The 645-day median to allowance reflects the pace of the examination process in Art Unit 2897. Practitioners should consider these metrics when advising clients on the timeline and probability of grant. The consistency seen across 744 resolved cases offers a predictable environment for patent prosecution.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

96.5%
Allow Rate
+28.5% vs TC avg
748
Total Applications
+2.4%
Interview Lift
645
Avg Prosecution Days
Based on 744 resolved cases, 2023–2026

Rejection Statute Breakdown

2.4%
§101 Eligibility
33.5%
§102 Novelty
46.0%
§103 Obviousness
5.6%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18597930 DISPLAY DEVICE AND ELECTRONIC APPARATUS Non-Final OA SEIKO EPSON CORPORATION
18648577 METHOD FOR PRODUCING A VERTICAL FIELD-EFFECT TRANSISTOR STRUCTURE AND CORRESPONDING VERTICAL FIELD-EFFECT TRANSISTOR STRUCTURE Non-Final OA Robert Bosch GmbH
18734746 CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITANCE TO SURFACE MOUNTED DIE Non-Final OA Intel Corporation
18654855 TECHNIQUES FOR ACHIEVING MULTIPLE TRANSISTOR FIN DIMENSIONS ON A SINGLE DIE Non-Final OA Intel Corporation
18772382 CELL PLACEMENT OPTIMIZATION Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18770367 SOURCE/DRAIN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR DEVICES Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18766003 STRUCTURE AND METHOD FOR FINFET DEVICE WITH SOURCE/DRAIN MODULATION Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18746930 SOURCE/DRAIN STRUCTURE FOR SEMICONDUCTOR DEVICE Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18741963 Contact Structures In Semiconductor Devices Non-Final OA Taiwan Semiconductor Manufacturing Company, LTD.
18731593 SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18673432 SOURCE/DRAIN EPI STRUCTURE FOR IMPROVING CONTACT QUALITY Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18645481 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18775943 SEMICONDUCTOR DEVICE AND METHODS OF FORMING Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18774643 Semiconductor Device with Cut Metal Gate and Method of Manufacture Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18771714 GATE STRUCTURES IN TRANSISTOR DEVICES AND METHODS OF FORMING SAME Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18766853 FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18671732 Contact Structures With Deposited Silicide Layers Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18662374 DUAL SILICIDE STRUCTURE AND METHODS THEREOF Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18635641 ASYMMETRIC EPITAXY REGIONS FOR LANDING CONTACT PLUG Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.

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