DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to claims 1, 4-6, 11, 13, and 14 have been fully considered. Based on the cited prior arts Hung, Gandhi, Arguedas, and Loo and new grounds of rejection from Yeh (US20220270949A1) the claims 1 - 20 are rejected.
Response to Amendment
Applicant’s amendments to claim 13 has been fully considered and resolve the USC 112(d) rejection. The USC 112(d) rejections to claim 13 has been withdrawn.
Claim Objections
Claims 1 and 5 are objected to because of the following informalities:
Claim 1 recites “the recessed region having a reduced thickness relative to the first portion and the second portion, and a width that is less than or equal to a width of a gap between the system-on-chip die and the stiffener structure.”; this should be written as “the recessed region having a reduced thickness relative to the first portion and the second portion, wherein the recessed region has a width that is less than or equal to a width of a gap between the system-on-chip die and the stiffener structure.”
Claim 5 recites “the width of the recessed region comprises a second width (W2) less than the first width (W2)”; this should be written as ““the width of the recessed region comprises a second width (W2) less than the first width (W1).”
Appropriate corrections are required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 7 and 11 - 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US20220359322A1; hereinafter Hung) in view of Yeh et al. (US20220270949A1; hereinafter Yeh).
Regarding Claim 1 (Currently amended), Hung discloses a module comprising:
a module substrate (102), FIG. 2A reproduced below, [0014];
a system-on-chip die (the chip package 104 is a system on chip (SoC)) coupled to the module substrate (102), FIG. 2A, [0014];
a thermal interface material layer (116) coupled to the system-on-chip die (104), FIG. 2A, [0018];
a stiffener structure (stiffener structure 108 including a stiffener ring 110a and a pair of the stiffener ribs 112a) positioned around the system-on-chip die (104) and coupled to the module substrate (102), FIG. 1, FIG. 2A, [0018]; and
a lid (114) having a first portion (bottom central portion of 114 directly above die 104) coupled to the thermal interface material layer (116), a second portion (bottom peripheral region of lid 114 over stiffener 110a and adhesive 118’) coupled to the stiffener structure (110), FIG. 2A, [0022].
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Hung: FIG. 2A
Hung (FIG. 2A, [0022]) discloses the first recess portion 113 located on the bottom of the lid 114 over the stiffener 112a and the second recess portion 115 located on the peripheral bottom of the lid, but does not disclose “a recessed region formed around the first portion and the recessed region having a reduced thickness relative to the first portion and the second portion, and a width that is less than or equal to a width of a gap between the system-on-chip die and the stiffener structure.”
In a similar art, Yeh discloses semiconductor packages [0001].
Yeh discloses the package lid 700 has a recessed region (thinner portion formed by the roof 710 of thickness T710) interposed along the Y direction between the first portion (thicker portions formed by the island 730 of thickness T730) and the second portion (footing 720 of thickness T720), FIG. 3E reproduced below, [0032].
Yeh discloses the thickness T720 of the footing 720 is greater than the thickness T710 of the roof 710; the thickness T730 of the island 730 is greater than the thickness T710 of the roof; and may be about equal to the thickness T720 of the footing 720, FIG. 3E, [0029], [0030].
Hence, second portion thickness T720 > recessed region thickness T710;
first portion thickness T730 > recessed region thickness T710;
and first portion thickness T730 may be equal to second portion thickness T720.
Yeh discloses a package lid 1200, with first portion 1230, recessed portion 1210, and the second portion 1220. Yeh discloses the ribs 1242 and 1244 are disconnected from the first portion 1230, indicating the recessed portion 1210 is formed around the first portion 1230, FIG. 9, [0042].
Yeh discloses: a recessed region (1210) formed around the first portion (1230), and the recessed region (1210) having a reduced thickness relative to the first portion (1230) and the second portion (1220), FIG. 3E, FIG. 9, [0029], [0030], [0042].
Yeh discloses: the recessed region (710) having a width (H2) that is less than or equal to a width of a gap (H3) between the system-on-chip die (220) and the stiffener structure (500), FIG. 3E, [0031], [0032], [0034].
Yeh [0032] discloses the lateral Y direction width H2 of the recessed region 710 is about 5 to 10% of the lateral Y direction width H700 of the package lid 700.
Yeh [0034] discloses lateral Y direction width H3 of the gap between the die 220 and the second portion 720 (stiffener 500, [0029]) may be 1 to 1.5 times the lateral Y direction width H730 of the first portion.
Yeh [0031] discloses the lateral Y direction width H730 may be 55% to 80% of the lateral Y direction H700.
Therefore, H3 is at least 55 – 80% of H700, while H2 is only about 5-10% of H700, indicating the width of the recessed region is less than or equal to a width of a gap between the system-on-chip die and the stiffener structure.
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Yeh: FIG. 3E
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 2, The combination of Hung and Yeh discloses the module of claim 1.
Hung does not disclose “wherein the lid is a single integrally formed structure.”
Yeh discloses: wherein the lid (700) is a single integrally formed structure (package lid 700 may be an integrally formed piece, [0026]).
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 3, The combination of Hung and Yeh discloses the module of claim 1.
Hung does not disclose “wherein the recessed region is formed entirely around the first portion.”
Yeh discloses a package lid 1200, with first portion 1230, recessed portion 1210, and the second portion 1220. Yeh discloses the ribs 1242 and 1244 are disconnected from the first portion 1230, indicating the recessed portion 1210 is formed around the first portion 1230, (FIG. 9, [0042]).
Yeh discloses: wherein the recessed region (1210) is formed entirely around the first portion (1230), FIG. 9, [0042].
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 4 (Currently amended), The combination of Hung and Yeh discloses the module of claim 1.
Hung discloses: wherein the recessed region (113) is aligned with the gap (119) between the system-on-chip die (104) and the stiffener structure (112a), FIG. 2A, [0021].
Regarding Claim 5 (Currently amended), The combination of Hung and Yeh discloses the module of claim 1.
Hung does not explicitly disclose: wherein the width of the gap between the system-on-chip die and the stiffener structure comprises a first width (W1), the width of the recessed region comprises a second width (W2) less than the first width (W1).
Yeh discloses: wherein the width of the gap (H3) between the system-on-chip die (220) and the stiffener structure (500) comprises a first width (W1), the width of the recessed region (H2) comprises a second width (W2) less than the first width (W1), FIG. 3E, [0031], [0032], [0034].
Yeh [0032] discloses the lateral Y direction width H2 of the recessed region 710 is about 5 to 10% of the lateral Y direction width H700 of the package lid 700. Yeh [0034] discloses lateral Y direction width H3 of the gap between the die 220 and the second portion 720 (stiffener 500, [0029]) may be 1 to 1.5 times the lateral Y direction width H730 of the first portion. Yeh [0031] discloses the lateral Y direction width H730 may be 55% to 80% of the lateral Y direction H700. Therefore, H3 is at least 55 – 80% of H700, while H2 is only about 5-10% of H700, indicating the width of the gap between the system-on-chip die and the stiffener structure comprises a first width (W1), the width of the recessed region comprises a second width (W2) less than the first width (W1).
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 6 (Currently amended), The combination of Hung and Yeh discloses the module of claim 1.
Hung does not disclose “wherein the recessed region comprises a depth (D) that is greater than zero and less than a thickness (T) of the first portion and the second portion of the lid, and the thickness (T) of the first portion and the second portion are the same.”
Yeh discloses: wherein the recessed region (710) comprises a depth (D) (difference between thicknesses T730 and T710) that is greater than zero and less than a thickness (T) of the first portion (T730) and the second portion (T720) of the lid, and the thickness (T) of the first portion (T730) and the second portion are the same (T720), FIG. 3E, [0029], [0030].
Yeh discloses the thickness T720 of the footing 720 is greater than the thickness T710 of the roof 710; the thickness T730 of the island 730 is greater than the thickness T710 of the roof; and may be about equal to the thickness T720 of the footing 720, FIG. 3E, [0029], [0030].
Hence, second portion thickness T720 > recessed region thickness T710;
first portion thickness T730 > recessed region thickness T710;
and first portion thickness T730 may be equal to second portion thickness T720.
Depth of the recessed region 710 corresponds to the difference between T730 and T710 which is greater than zero and less than the thickness of the first portion and the second portion, since the first portion thickness T730 is greater than thickness T710 and the first portion thickness and the second portion thickness may be the same.
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 7, The combination of Hung and Yeh discloses the module of claim 1.
Hung does not disclose “wherein the first portion comprises a polygonal shape.”
Yeh discloses: wherein the first portion (730) comprises a polygonal shape, FIG. 9, [0031].
Yeh discloses the width W220 and the height H220 of the semiconductor die 220 are at most respectively equal to the width W730 and the height H730 of the island 730, indicating the first portion (730) comprises a polygonal shape, FIG. 9, [0031].
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 11 (Currently amended), Hung discloses a module (semiconductor package100) comprising:
a module substrate (102), FIG. 2A, [0014];
a system-on-chip die (the chip package 104 is a system on chip (SoC)) coupled to the module substrate (102), FIG. 2A, [0014];
a thermal interface material layer (116) coupled to the system-on-chip die (104), FIG. 2A, [0018];
a stiffener structure (stiffener structure 108 including a stiffener ring 110a and a pair of the stiffener ribs 112a) positioned around the system-on-chip die (104) and coupled to the module substrate (102), FIG. 1, FIG. 2A, [0018]; and
a lid (114) having a bottom side comprising a first portion (bottom central portion of 114 directly above die 104) coupled to the thermal interface material layer (116) and a recessed region (113) formed around the first portion that is aligned with a gap (119) between the system-on-chip die (104) and the stiffener structure (112), FIG. 2A, [0021], [0022].
Hung does not disclose “the recessed region formed entirely around the first portion; and wherein the gap between the system-on-chip die and the stiffener structure comprises a first width (W1) and the recessed region comprises a second width (W2) that is greater than zero and equal to or less than the first width (W1).”
In a similar art, Yeh discloses semiconductor packages [0001].
Yeh discloses: wherein the recessed region (1210) is formed entirely around the first portion (1230), FIG. 9, [0042].
Yeh discloses a package lid 1200, with first portion 1230, recessed portion 1210, and the second portion 1220. Yeh discloses the ribs 1242 and 1244 are disconnected from the first portion 1230, indicating the recessed portion 1210 is formed around the first portion 1230, (FIG. 9, [0042]).
Yeh discloses: wherein the gap (H3) between the system-on-chip die (220) and the stiffener structure (500) comprises a first width (W1), and the recessed region (H2) comprises a second width (W2) that is greater than zero and equal to or less than the first width (W1), FIG. 3E, [0031], [0032], [0034].
Yeh [0032] discloses the lateral Y direction width H2 of the recessed region 710 is about 5 to 10% of the lateral Y direction width H700 of the package lid 700. Yeh [0034] discloses lateral Y direction width H3 of the gap between the die 220 and the second portion 720 (stiffener 500, [0029]) may be 1 to 1.5 times the lateral Y direction width H730 of the first portion. Yeh [0031] discloses the lateral Y direction width H730 may be 55% to 80% of the lateral Y direction H700. Therefore, H3 is at least 55 – 80% of H700, while H2 is only about 5-10% of H700, indicating the width of the gap between the system-on-chip die and the stiffener structure comprises a first width (W1), the width of the recessed region comprises a second width (W2) that is greater than zero and equal to or less than the first width (W1).
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 12, The combination of Hung and Yeh discloses the module of claim 11.
Hung does not disclose “wherein the lid is a single inseparable structure formed of a metal material.”
Yeh discloses: wherein the lid (700) is a single inseparable structure formed of a metal material (package lid 700 may be an integrally formed of a material for e.g. copper foil, [0026]).
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 13 (Currently amended), The combination of Hung and Yeh discloses the module of claim 11.
Hung does not disclose “wherein W2/W1 is less than 1.”
Yeh discloses: wherein the width of the gap (H3) between the system-on-chip die (220) and the stiffener structure (500) comprises a first width (W1), the width of the recessed region (H2) comprises a second width (W2) less than the first width (W2), FIG. 3E, [0031], [0032], [0034].
Yeh [0032] discloses the lateral Y direction width H2 of the recessed region 710 is about 5 to 10% of the lateral Y direction width H700 of the package lid 700. Yeh [0034] discloses lateral Y direction width H3 of the gap between the die 220 and the second portion 720 (stiffener 500, [0029]) may be 1 to 1.5 times the lateral Y direction width H730 of the first portion. Yeh [0031] discloses the lateral Y direction width H730 may be 55% to 80% of the lateral Y direction H700. Therefore, H3 is at least 55 – 80% of H700, while H2 is only about 5-10% of H700 and the ratio of H2/H3 is less than 1 which corresponds to the ratio of W2/W1 less than 1.
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 14 (Currently amended), The combination of Hung and Yeh discloses the module of claim 11.
Hung does not explicitly disclose: wherein the second width (W2) is less than the first width (W1).
Yeh discloses: wherein the second width (W2) is less than the first width (W1).
Yeh [0032] discloses the lateral Y direction width H2 of the recessed region 710 is about 5 to 10% of the lateral Y direction width H700 of the package lid 700. Yeh [0034] discloses lateral Y direction width H3 of the gap between the die 220 and the second portion 720 (stiffener 500, [0029]) may be 1 to 1.5 times the lateral Y direction width H730 of the first portion. Yeh [0031] discloses the lateral Y direction width H730 may be 55% to 80% of the lateral Y direction H700. Therefore, H3 is at least 55 – 80% of H700, while H2 is only about 5-10% of H700, indicating the second width (W2) is less than the first width (W1).
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 15, The combination of Hung and Yeh disclose the module of claim 11.
Hung does not disclose “wherein the recessed region comprises a depth (D) that is greater than zero and less than a thickness (T) of the lid.”
Yeh discloses: wherein the recessed region (710) comprises a depth (D) (difference between thicknesses T730 and T710) that is greater than zero and less than a thickness (T) of the lid (700), FIG. 3E, [0029], [0030].
Yeh discloses the thickness T720 of the footing 720 is greater than the thickness T710 of the roof 710; the thickness T730 of the island 730 is greater than the thickness T710 of the roof; and may be about equal to the thickness T720 of the footing 720, FIG. 3E, [0029], [0030].
Hence, second portion thickness T720 > recessed region thickness T710;
first portion thickness T730 > recessed region thickness T710;
and first portion thickness T730 may be equal to second portion thickness T720.
Depth of the recessed region 710 corresponds to the difference between T730 and T710 which is greater than zero and less than the thickness of the first portion and the second portion, since the first portion thickness T730 is greater than thickness T710 and the first portion thickness and the second portion thickness may be the same and corresponds to the thickness of the lid 700.
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Regarding Claim 16, The combination of Hung and Yeh disclose the module of claim 11.
Hung does not disclose “wherein the first portion comprises a rectangular or a square shape.”
Yeh discloses: wherein the first portion (730) comprises a rectangular or a square shape, FIG. 9, [0031].
Yeh discloses the width W220 and the height H220 of the semiconductor die 220 are at most respectively equal to the width W730 and the height H730 of the island 730, indicating the first portion (730) comprises a rectangular or a square shape, FIG. 9, [0031].
Yeh discloses that the structure as taught improves the manufacturing yield and reliability of the package [0057]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s semiconductor package in order to improve the manufacturing yield and reliability of the package as disclosed by Yeh [0057].
Claims 9, 10, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Yeh, further in view of Gandhi et al. (US20180358280A1; hereinafter Gandhi).
Regarding Claim 9, The combination of Hung and Yeh discloses the module of claim 1.
The combination of Hung and Yeh does not explicitly disclose “wherein the recessed region is a first recessed region and a second recessed region is formed in at least one corner or along at least one side of the first portion.”
In a similar art, Gandhi discloses an integrated circuit (IC) package 100 [0025].
Gandhi discloses the four recessed areas 256 are arranged in the lid 250 such that these areas will be located above four different corners of the IC die(s) 114 in the IC package 100, FIG. 3A, [0045].
Gandhi discloses another example lid 250 having multiple recessed areas 256
at each of multiple locations, FIG. 2A, [0042].
Gandhi discloses: wherein the recessed region (256) is a first recessed region (a first recessed area 256 at first corner) and a second recessed region (a second recessed area 256 at the first corner) is formed in at least one corner or along at least one side of the first portion (one corner of the non-recessed portion of lid 250 including an inner surface 254), FIG. 2A, [0042].
Gandhi discloses that a structure as taught enables reduction of thermal interface material bond line thickness in order to achieve lower thermal resistance and improved heat dissipation [0036]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung and Yeh’s semiconductor package, in order to lower thermal resistance and improve heat dissipation as disclosed by Gandhi [0036].
Regarding Claim 10, The combination of Hung, Yeh, and Gandhi discloses the module of claim 9.
The combination of Hung and Yeh does not disclose “wherein the thermal interface material layer comprises a single thermal interface material having a first thickness and a second thickness, the second thickness is formed in the second recessed region and is greater than the first thickness.”
Gandhi discloses bond line thickness (BLT) of the TIM 140 is reduced in the area between the first inner surface 254 and the IC dies 114; and the recessed areas 256
take in the excess portion of the TIM 140 forming bulbous portions which are thicker. FIG. 2, [0038].
Gandhi discloses: wherein the thermal interface material layer (TIM 140) comprises a single thermal interface material having a first thickness (bond line thickness of TIM 140 in the area between 254 and the IC dies) and a second thickness (bulbous portions of the TIM 140 in the recessed region 256), the second thickness is formed in the second recessed region (second recess 256 at first corner, FIG. 2A, [0042]) and is greater than the first thickness, FIG. 2, [0038].
Gandhi discloses that a structure as taught enables reduction of thermal interface material bond line thickness in order to achieve lower thermal resistance and improved heat dissipation [0036]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package, in order to lower thermal resistance and improve heat dissipation as disclosed by Gandhi [0036].
Regarding Claim 18, The combination of Hung and Yeh discloses the module of claim 11.
The combination of Hung and Yeh does not explicitly disclose “wherein the recessed region is a first recessed region and a second recessed region is formed in each corner of the first portion.”
Gandhi discloses the four recessed areas 256 are arranged in the lid 250 such that these areas will be located above four different corners of the IC die(s) 114 in the IC package 100, FIG. 3A, [0045].
Gandhi discloses another example lid 250 having multiple recessed areas 256
at each of multiple locations, FIG. 2A, [0042].
Gandhi discloses: wherein the recessed region (256) is a first recessed region (a first recessed area 256 at first corner) and a second recessed region (a second recessed area 256 at the first corner) is formed in at least one corner of the first portion (one corner of the non-recessed portion of lid 250 including an inner surface 254), FIG. 2A, [0042].
Gandhi discloses that a structure as taught lowers thermal resistance and improves heat dissipation [0036]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung and Yeh’s semiconductor package, in order to lower thermal resistance and improve heat dissipation as disclosed by Gandhi [0036].
Regarding Claim 19, The combination of Hung, Yeh, and Gandhi discloses the module of claim 18.
The combination of Hung and Yeh does not disclose “wherein the thermal interface material layer comprises a single thermal interface material having a greater thickness within the second recessed region formed in each corner of the first portion than a remainder of the first portion.”
Gandhi discloses bond line thickness (BLT) of the TIM 140 is reduced in the area between the first inner surface 254 and the IC dies 114; and the recessed areas 256
take in the excess portion of the TIM 140 forming bulbous portions which are thicker. FIG. 2, [0038].
Gandhi discloses: wherein the thermal interface material layer (TIM 140) comprises a single thermal interface material having a greater thickness (bulbous portions of the TIM 140 in the recessed region 256) within the second recessed region (second recess 256 at each corner, FIG. 2A, [0042]) formed in each corner of the first portion than a remainder of the first portion (thinner BLT at each corner of portion between 254 and IC dies), FIG. 2, [0038].
Gandhi discloses that a structure as taught enables reduction of thermal interface material bond line thickness in order to achieve lower thermal resistance and improved heat dissipation [0036]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package, in order to lower thermal resistance and improve heat dissipation as disclosed by Gandhi [0036].
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Yeh, further in view of Arguedas et al. (US20200373220A1; hereinafter Arguedas).
Regarding Claim 8, The combination of Hung and Yeh discloses the module of claim 7.
The combination of Hung and Yeh does not disclose “wherein the thermal interface material layer comprises a first thermal interface material arranged along a center of the first portion and a second thermal interface material arranged along a corner of the first portion.”
In a similar art, Arguedas discloses an IC package 100 that includes thermal interface materials (TIMs) having different material compositions [0015].
Arguedas discloses a first TIM 104A is proximate to a center of the die 106 and a second TIM 104B, having a different material composition than the first TIM 104A, is proximate to the edge of the die 106, FIG. 1, [0021].
The combination of Hung, Yeh, and Arguedas discloses: wherein the thermal interface material layer comprises a first thermal interface material (Arguedas: first TIM 104A) arranged along a center of the first portion (Hung: center of bottom central portion of 114 directly above die 104) and a second thermal interface material (Arguedas: second TIM 104B) arranged along a corner of the first portion (Hung: corner of bottom central portion of 114 directly above die 104).
Arguedas discloses that the package structure as taught provides improved mechanical performance, thermal performance, and/or manufacturability [0022]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung and Yeh’s semiconductor package in order to improve mechanical performance, thermal performance, and/or manufacturability as disclosed by Arguedas [0022].
Regarding Claim 17, The combination of Hung and Yeh discloses the module of claim 16.
The combination of Hung and Yeh does not disclose “wherein the thermal interface material layer comprises a first thermal interface material and a second thermal interface material having a different thermal conductivity than the first thermal interface material, and the first or the second thermal interface material is confined to at least one corner of the first portion.”
Arguedas discloses a first TIM 104A is proximate to a center of the die 106 and a second TIM 104B, having a different material composition than the first TIM 104A, is proximate to the edge of the die 106, FIG. 1, [0021]; and the second TIM 104B may have a lower thermal conductivity than the first TIM 104A [0022].
The combination of Hung, Yeh, and Arguedas disclose: wherein the thermal interface material layer comprises a first thermal interface material (Arguedas: TIM 104A) and a second thermal interface material (Arguedas: TIM 104B, FIG. 1, [0022]) having a different thermal conductivity than the first thermal interface material, and the first or the second thermal interface material is confined to at least one corner (Arguedas: TIM 104B confined to corners, FIGS. 2D, 2E [0028]) of the first portion (Hung: bottom central portion of 114 directly above die 104).
Arguedas discloses that the package structure as taught provides improved mechanical performance, thermal performance, and/or manufacturability [0022]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung and Yeh’s semiconductor package in order to improve mechanical performance, thermal performance, and/or manufacturability as disclosed by Arguedas [0022].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Yeh, further in view of Loo et al. (US20110018125A1; hereinafter Loo).
Regarding Claim 20, The combination of Hung and Yeh discloses the module of claim 11.
The combination of Hung and Yeh does not explicitly disclose ”wherein the stiffener structure is an integrally formed part of the lid and surrounds the recessed region.”
In a similar art, Loo discloses a semiconductor package including supporting stiffening and heat spreading characteristics [0002].
Loo discloses the lid 44 has an integrally formed stiffener 50 that surrounds the interior region of the package, FIG. 6, [0023].
The combination of Hung, Yeh, and Loo discloses: wherein the stiffener structure (Loo: 50) is an integrally formed part of the lid (Loo: 44) and surrounds the recessed region (Yeh: recess 1210, FIG. 9, [0042]).
Loo discloses that a structure as taught improves package rigidity and reduces warpage [0031]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hung and Yeh’s semiconductor package in order to improve package rigidity and reduce warpage as disclosed by Loo [0031].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to Krishna J Palaniswamy whose telephone number
is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM -
5PM EST.
Examiner interviews are available via telephone, in-person, and video
conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request
(AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number
for the organization where this application or proceeding is assigned is 571-483-7639.
Information regarding the status of published or unpublished applications may be
obtained from Patent Center. Unpublished application information in Patent Center is
available to registered users. To file and manage patent submissions in Patent Center,
visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-
center for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format. For
additional questions, contact the Electronic Business Center (EBC) at 866-217-9197
(toll-free). If you would like assistance from a USPTO Customer Service
Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Krishna J Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights