DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 8/27/26 have been fully considered but they are not persuasive. Regarding applicants argument “Currently, the amended claim 1 recites the feature of a first plasmonic bridge vertically overlapped and electrically connected with both the first electric integrated circuit component…" Applicant deems Kim at least fails to disclose the foregoing feature”, Examiner assert that through a reinterpretation of the structural relationships of the limitations as cited below, Kim does in fact teach the new combination of claim limitations.
Allowable Subject Matter
Claims 16 – 20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, taken alone or in combination, fails to disclose or render obvious a semiconductor package comprising, among other things, a first plasmonic bridge embedded in the insulating encapsulant, wherein the first plasmonic bridge comprises a first electrical-optical conversion module, a second electrical-optical conversion module, and a first plasmonic waveguide optically connecting the first electrical-optical conversion module and the second electrical-optical conversion module; a first redistribution structure sandwiched between the first electric integrated circuit component and the insulating encapsulant, wherein the first redistribution structure electrically connects the first electric integrated circuit component and the first electrical-optical conversion module; and a second redistribution structure sandwiched between the second electric integrated circuit component and the insulating encapsulant, wherein the second redistribution structure electrically connects the second electric integrated circuit component and the second electrical-optical conversion module.
The closest relevant prior art of record, Kim (U.S. PG Pub. # 2013/0011094 A1), teaches the encapsulant (hashed area) embedding a plasmonic waveguide (110, 120 130) and not the modules as claimed nor the redistribution structures as claimed.
Thus, with no teaching from the prior art, and without the benefit of applicant's teachings, there is no motivation for one of ordinary skill in the art to combine/modify the prior art of record in a manner so as to create the claimed invention.
Claim 3, 5, 6, 11 – 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, taken alone or in combination, fails to disclose or render obvious a package comprising, among other things, wherein the first plasmonic waveguide optically connects the first electric integrated circuit component and the second electric integrated circuit component respectively through the first electrical-optical conversion module and the second electrical-optical conversion module;
a plurality of through vias penetrating through the substrate and the insulating encapsulant;
and an insulating encapsulant filled among the substrate, the first electric integrated circuit component, and the second electric integrated circuit component, wherein the insulating encapsulant encapsulates the first plasmonic bridge.
The closest relevant prior art of record, Kim (U.S. PG Pub. # 2008/0080807 A1), teaches electrically coupling from 112 and 119 to 106, not optically coupling nor does it teach vias or insulating encapsulant as claimed.
Thus, with no teaching from the prior art, and without the benefit of applicant's teachings, there is no motivation for one of ordinary skill in the art to combine/modify the prior art of record in a manner so as to create the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. PG Pub. # 2013/0011094 A1).
In Re claim 1, ‘094 teaches a semiconductor package (fig. 5), comprising: a first electric integrated circuit component (510); a second electric integrated circuit component (520) aside the first electric integrated circuit component; and a first plasmonic bridge (structures of fig. 5, except for 530, 540, 550 and 560) vertically overlapped and electrically connected (150, pars. 0034 – 0035, 0037, 0045 and 0046) with both the first electric integrated circuit component and the second electric integrated circuit component, wherein the first plasmonic bridge comprises a first plasmonic waveguide (110, 120 and 130) optically connecting the first electric integrated circuit component and the second electric integrated circuit component (fig. 5).
Claims 1, 2, 4, 7, 9 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. PG Pub. # 2008/0080807 A1).
In Re claim 1, ‘807 teaches a semiconductor package (fig. 3B), comprising: a first electric integrated circuit component (106 on left); a second electric integrated circuit component (106 on the right) aside the first electric integrated circuit component; and a first plasmonic bridge (109 and 112 OR 109, 111 and 112 OR 109, 111, 112 119 and 119B as boundaries of the bridge have not been recited) vertically overlapped and electrically connected (via 112) with both the first electric integrated circuit component and the second electric integrated circuit component, wherein the first plasmonic bridge comprises a first plasmonic waveguide (111, pars. 0018, 0053, 0078) optically connecting the first electric integrated circuit component and the second electric integrated circuit component.
In Re claim 2, ‘807 teaches wherein the first plasmonic bridge further comprises: a first electrical-optical conversion module (104), electrically coupled to the first electric integrated circuit component and optically coupled to the first plasmonic waveguide; and a second electrical-optical conversion module (113), electrically coupled to the second electric integrated circuit component and optically coupled to the first plasmonic waveguide.
In Re claim 4, ‘807 teaches a substrate (101) underneath the first plasmonic bridge; and an insulating encapsulant (around 109, par. 0053) disposed on the substrate, wherein the insulating encapsulant encapsulates the first plasmonic bridge (pars. 0060, 112 and 111 are inside the encapsulant).
In Re claim 7, ‘807 teaches a second plasmonic bridge embedded in the insulating encapsulant, and the second plasmonic bridge is coupled to the second electric circuit component (as seen as an array in fig. 5A).
In Re claim 9, ‘807 teaches a plurality of conductive terminals on the substrate opposite to the insulating encapsulant (118).
In Re claim 10, ‘807 teaches a semiconductor package, comprising: a first electric integrated circuit component (106 on left); a second electric integrated circuit component (106 on right) disposed adjacent to the first electric integrated circuit component; and a first plasmonic bridge comprising a first terminal (108 on left or 119), a second terminal (108 on right or 119a), and a first plasmonic waveguide (111, pars. 0018, 0053, 0078) optically connecting the first terminal and the second terminal, wherein the first terminal is electrically connected to the first electric integrated circuit component, and the second terminal is electrically connected to the second electric integrated circuit component (figs 1A, 1B, 3B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub. # 2008/0080807 A1).
‘807 teaches the package of claim 7, and an array of bridges (fig. 5A), but is silent to wherein the second plasmonic bridge comprises a third electrical-optical conversion module, a fourth electrical- optical conversion module, and a second plasmonic waveguide extending horizontally between the third electrical-optical conversion module and the fourth electrical-optical conversion module, and both of the third electrical-optical conversion module and the fourth electrical- optical conversion module are electrically connected to the second integrated circuit component and are optically connected to the second plasmonic waveguide.
However, it is well known that arrays of E/O conversion module connected to arrays of waveguides or bridges allows for a greater amount of communication within a circuit.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify ‘807 to use an array of bridges and corresponding E/O conversion modules as taught by ‘807 so as to allow for a greater amount of communication within a circuit thus making a more robust system as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAD SMITH whose telephone number is (571)270-1294. The examiner can normally be reached M-F 7:30 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 1-571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHAD H SMITH/ Primary Examiner, Art Unit 2874
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