DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed January 27, 2026 have been entered and considered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20070072370 A1), in view of Wu et al. (US 9917165 B2).
Regarding claim 1, Chang teaches:
A memory structure, comprising:
a substrate [100, paragraph [0039], Fig. 1A-5];
charge storage layers [130, paragraph [0043], Fig. 1A-5] located on the substrate [100, Fig. 1A-5]; and
a gate [150, paragraph [0045], Fig. 1E-1F, 2E, 3E, 4E, 2F, 3F, 4F, 5] located on the substrate [100, Fig. 1A-5] on one side of the charge storage layers [130, Fig. 1A-5] and extending along a first direction, wherein the gate [150, Fig. 2F, 2D] has a protruding portion [135, paragraph [0044], [0049], Fig. 2F, 2D, 4D, 2E] protruding along a second direction, the second direction intersects the first direction, the protruding portion [135, Fig. 2D, 4D] is located between two adjacent charge storage layers [130, paragraph [0049], Fig. 2D] arranged along the first direction.
Chang does not teach:
in a top view, the protruding portion protrudes from a sidewall of the gate along the second direction.
Wu et al. teaches:
in a top view, the protruding portion [150A, 150B, Col. 5, Lines 32-39; Col. 10, Lines 64-67 to Col. 11, Lines 1-5 and 65-66, Fig. 1A-1D, 17-21B] protrudes from a sidewall of the gate [130, Col. 4, Lines 12-25; Col. 5, Lines 27-44; Col. 11, Lines 61-66, Fig. 1A-1D, 17-21B] along the second direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Wu et al. into the teachings of Chang to include in a top view, the protruding portion protrudes from a sidewall of the gate along the second direction, for the purpose of increasing electric field strength, and increasing electron tunneling and erase speed.
Regarding claim 2, Chang and Wu et al. teach the memory structure according to claim 1.
Chang further teaches:
dielectric layers [120, paragraph [0042], [0051-0052], Fig. 1B-5] located between the charge storage layers [130, Fig. 1A-5] and the substrate [100, Fig. 1A-5].
Regarding claim 3, Chang and Wu et al. teach the memory structure according to claim 1.
Chang further teaches:
a dielectric layer [140, paragraph [0044], Fig. 1D, 1E, 1F, 2D, 3D, 4D, 2E, 3E, 4E, 2F, 3F, 4F, 5] located between the gate [150, Fig. 2F, 3F, 4F, 2E, 3E, 4E, 5] and the substrate [100, Fig. 1A-5].
Regarding claim 4, Chang and Wu et al. teach the memory structure according to claim 1.
Chang further teaches:
wherein the charge storage layers [130, paragraph [0043], Fig. 1A-5] comprise floating gates.
Regarding claim 5, Chang and Wu et al. teach the memory structure according to claim 1.
Chang further teaches:
an isolation structure [101, paragraph [0039], Fig. 1A-5] located in the substrate [100, Fig. 1A-5].
Regarding claim 6, Chang and Wu et al. teach the memory structure according to claim 5.
Chang further teaches:
wherein there is a trench [135, paragraph [0044], Fig. 2D, 2E] in the isolation structure [101, paragraph [0044], Fig. 2D, 2E] and between two adjacent charge storage layers [130, Fig. 2D, 2E] arranged along the second direction, and the trench [135, Fig. 2C, 2F, 2D, 2E] extends along the first direction.
Regarding claim 7, Chang and Wu et al. teach the memory structure according to claim 6.
Chang further teaches:
the isolation structure [101, Fig. 2F, 2D, 2E] has a recess between the two adjacent charge storage layers [130, Fig. 2C, 2F, 2D, 2E] arranged along the first direction,
the recess is connected to the trench [135, Fig. 2C, 2F, 2D, 2E], and
the protruding portion [135, Fig. 2C, 2F, 2D, 2E] is located in the recess.
Regarding claim 10, Chang and Wu et al. teach the memory structure according to claim 5.
Chang further teaches:
a dielectric layer [140, paragraph [0051], [0053], Fig. 2E, 3E, 4E] located between the gate [150, Fig. 2E, 3E, 4E] and the charge storage layers [130, Fig. 2E, 3E, 4E] and between the gate [150, Fig. 2E, 3E, 4E] and the isolation structure [101, Fig. 2E, 3E, 4E].
Regarding claim 13, Chang and Wu et al. teach the memory structure according to claim 1.
Chang further teaches:
wherein the second direction is perpendicular to the first direction. [Fig. 1A-5]
Regarding claim 14, Chang teaches:
A manufacturing method of a memory structure, comprising:
providing a substrate [100, paragraph [0039], Fig. 1A-5];
forming charge storage layers [130, paragraph [0043], Fig. 1C, 1D, 2C, 3C, 2F, 3F, 2D, 3D, 2E, 3E, 5] on the substrate [100, Fig. 1A-5]; and
forming a gate [150, paragraph [0045], Fig. 1E-1F, 2E, 3E, 4E, 2F, 3F, 4F, 5] on the substrate [100, Fig. 1A-5] on one side of the charge storage layers [130, Fig. 2F, 3F, 4F], wherein the gate [150] extends along a first direction, the gate [150] has a protruding portion [135, paragraph [0044], [0049], Fig. 2F, 2D, 4D, 2E] protruding along a second direction, the second direction intersects the first direction, the protruding portion [135, Fig. 2F, 2D, 4D, 2E] is located between two adjacent charge storage layers [130, Fig. 2F] arranged along the first direction.
Chang does not teach:
in a top view, the protruding portion protrudes from a sidewall of the gate along the second direction.
Wu et al. teaches:
in a top view, the protruding portion [150A, 150B, Col. 5, Lines 32-39; Col. 10, Lines 64-67 to Col. 11, Lines 1-5 and 65-66, Fig. 1A-1D, 17-21B] protrudes from a sidewall of the gate [130, Col. 4, Lines 12-25; Col. 5, Lines 27-44; Col. 11, Lines 61-66, Fig. 1A-1D, 17-21B] along the second direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Wu et al. into the teachings of Chang to include in a top view, the protruding portion protrudes from a sidewall of the gate along the second direction, for the purpose of increasing electric field strength, and increasing electron tunneling and erase speed.
Regarding claim 15, Chang and Wu et al. teach the manufacturing method of the memory structure according to claim 14.
Chang further teaches:
forming dielectric layers [120, paragraph [0042], [0051-0052], Fig. 1B-5] between the charge storage layers [130, Fig. 1A-5] and the substrate [100, Fig. 1A-5].
Regarding claim 16, Chang and Wu et al. teach the manufacturing method of the memory structure according to claim 14.
Chang further teaches:
forming a dielectric layer [140, paragraph [0044], Fig. 1D, 1E, 1F, 2D, 3D, 4D, 2E, 3E, 4E, 2F, 3F, 4F, 5] between the gate [150, Fig. 2F, 3F, 4F, 2E, 3E, 4E, 5] and the substrate [100, Fig. 1A-5].
Regarding claim 17, Chang and Wu et al. teach the manufacturing method of the memory structure according to claim 14.
Chang further teaches:
forming an isolation structure [101, paragraph [0039], Fig. 1A-5] in the substrate [100, Fig. 1A-5].
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20070072370 A1), in view of Wu et al. (US 9917165 B2) as applied to claim 5 above, and further in view of Dutta et al. (US 20130163340 A1).
Regarding claim 8, Chang and Wu et al. teach the memory structure according to claim 5.
Chang further teaches:
a hard mask layer [110, paragraph [0040], [0047], Fig. 1A-5] located on the isolation structure [101, paragraph [0041], Fig. 2A, 3A, 4A], wherein the hard mask layer [110] extends along the first direction.
Chang and Wu et al. do not teach:
a hard mask layer located on the charge storage layers.
Dutta et al. teaches:
a hard mask layer [Hard Mask, paragraph [0049], Fig. 6D] located on the charge storage layers [Floating Gate, paragraph [0049], Fig. 6D].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Dutta et al. into the teachings of Chang and Wu et al. to include a hard mask layer located on the charge storage layers, for the purpose of protecting charge storage layers and etching only desired locations. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
Regarding claim 9, Chang, Wu et al. and Dutta et al. teach the memory structure according to claim 8.
Chang further teaches:
wherein the protruding portion [135, Fig. 2F, 2D, 4D, 2E] is located between the hard mask layer [110, Fig. 2D, 3D, 4D] and the isolation structure [101, Fig. 2D, 3D, 4D].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20070072370 A1), in view of Wu et al. (US 9917165 B2) as applied to claim 1 above, and further in view of Chowdhury (KR 20050085415 A).
Regarding claim 11, Chang and Wu et al. teach the memory structure according to claim 1.
Chang and Wu et al. do not teach:
wherein a width of the portion protruding is greater than 0 and less than or equal to 25 nm.
Chowdhury teaches:
wherein a width of the portion protruding is greater than 0 and less than or equal to 25 nm. [paragraph [0009-0010]]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chowdhury into the teachings of Chang and Wu et al. to include wherein a width of the portion protruding is greater than 0 and less than or equal to 25 nm, for the purpose of enhancing electric field and improving performance.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20070072370 A1), in view of Wu et al. (US 9917165 B2) as applied to claim 1 above, and further in view of Hayashi et al. (US 20180097008 A1).
Regarding claim 12, Chang and Wu et al. teach the memory structure according to claim 1.
Chang and Wu et al. do not teach:
spacers located on sidewalls of the charge storage layers away from the gate.
Hayashi et al. teaches:
spacers [SW, paragraph [0089], Fig. 33] located on sidewalls of the charge storage layers [107, paragraph [0087-0088], Fig. 33] away from the gate [CG (105), paragraph [0084-0086], Fig. 33].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hayashi et al. into the teachings of Chang and Wu et al. to include spacers located on sidewalls of the charge storage layers away from the gate, for the purpose of increasing operation speed, reducing gate leakage, and protecting underlying features.
Claim 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20070072370 A1), in view of Wu et al. (US 9917165 B2) as applied to claim 17 above, and further in view of Kim et al. (US 20080099821 A1).
Regarding claim 18, Chang and Wu et al. teach the manufacturing method of the memory structure according to claim 17.
Chang further teaches:
there is a trench [135, paragraph [0044], Fig. 2D, 2E] in the isolation structure [101, paragraph [0044], Fig. 2D, 2E] and between two adjacent charge storage layers [130, Fig. 2D, 2E] arranged along the second direction,
the trench [135, Fig. 2C, 2F, 2D, 2E ] extends along the first direction.
Chang and Wu et al. do not teach:
the trench exposes a sidewall of the isolation structure.
Kim et al. teaches:
the trench [613, paragraph [0044-0045], Fig. 6D-6E] exposes a sidewall of the isolation structure [605, paragraph [0045], Fig. 6D-6E].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kim et al. into the teachings of Chang and Wu et al. to include the trench exposes a sidewall of the isolation structure, for the purpose of prepping for the protrusion, enhancing electric field, and improving performance.
Regarding claim 19, Chang, Wu et al. and Kim et al. teach the manufacturing method of the memory structure according to claim 18.
Chang further teaches:
wherein a method of forming the gate [150, paragraph [0045], Fig. 1E-1F, 2E, 3E, 4E, 2F, 3F, 4F, 5] comprises:
removing a portion of the isolation structure [101, paragraph [0042], Fig. 2C-2F] exposed by the trench [135, Fig. 2C-2E] to form a recess in the isolation structure [101], wherein the portion of the isolation structure [101] exposed by the trench [135, Fig. 2D-2E] is removed by a wet etching process; and
forming the gate [150, Fig. 2D-2E] in the trench [135, Fig. 2D-2E] and the recess.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20070072370 A1), in view of Wu et al. (US 9917165 B2) and Kim et al. (US 20080099821 A1) as applied to claim 19 above, and further in view of Yu (CN 104733396 A).
Regarding claim 20, Chang, Wu et al. and Kim et al. teach the manufacturing method of the memory structure according to claim 19.
Chang, Wu et al. and Kim et al. do not teach:
wherein a duration of the wet etching process is 20 seconds to 130 seconds.
Yu teaches:
wherein a duration of the wet etching process is 20 seconds to 130 seconds. [paragraph [0049]]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yu into the teachings of Chang, Wu et al. and Kim et al. to include wherein a duration of the wet etching process is 20 seconds to 130 seconds, for the purpose of lowering cost of manufacturing, improving simplicity, highly selective allowing for removal of specific materials while leaving others intact, improving versatility and uniform results.
Response to Arguments
Applicant’s arguments with respect to independent claims 1 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on pages 2-4, Section: Discussion of Claim Rejections under 35 U.S.C. 102 & 103, in remarks filed January 27, 2026 that the current prior art of record does not teach the amendments to independent claims 1 and 14. Examiner agrees with Applicant; However, after a new line of search and consideration of the prior art, the amended limitations of independent claims 1 and 14 can be overcome by newly cited source Wu et al. (US 9917165 B2).
Applicant argues on page 4, Section: Discussion of Claim Rejections under 35 U.S.C. 102 & 103, in remarks filed January 27, 2026 that claims dependent on independent claims 1 and 14 should also be in condition for allowance. Examiner disagrees with Applicant due to the introduction of newly cited source Wu et al. (US 9917165 B2) being able to overcome the amended limitations.
In summary, the amended limitations of independent claims 1 and 14 can be overcome by newly cited source Wu et al. (US 9917165 B2). All claims directly or indirectly dependent on independent claims 1 and 14 are also rejected for at least the reasons mentioned above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.M.H./Examiner, Art Unit 2815 05/06/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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