DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species H (FIG. 9) in the reply filed on 27 Mar 2026 is acknowledged. The traversal is on the grounds that “it should be no serious burden on the Examiner to examine all of the claims directed to Species A, Species B, Species C, Species D, Species E, Species F, Species G, and Species H. Specifically, Species A, Species B, Species C, Species D, Species E, Species F, Species G, and Species H recite similar technical features.”
This is found to be persuasive because this Office Action finds that the independent claims 1, 14, and 21 contain allowable subject matter; thus, claims 4, 10, and 13 (which were not included in the list of the claims which Applicant’s reply identified as reading on the elected Species H), previously withdrawn from consideration as a result of a restriction requirement, require all the limitations of an allowable claim. Pursuant to the procedures set forth in MPEP § 821.04(a), the restriction requirement between Species A–H, as set forth in the Office action mailed on 2 Feb 2026, is hereby withdrawn and claims 4, 10, and 13 are hereby rejoined and fully examined for patentability under 37 CFR 1.104. In view of the withdrawal of the restriction requirement, applicant(s) are advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3 Dec 2025 has been considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
In many different places, the specification refers to interfaces 102DDR-1, 102DDR-2 / 102DDR-2′, 102DDR-3, and 102DDR-4. However, these labels appear in the drawings without hyphens as 102DDR1, 102DDR2 / 102DDR2′, 102DDR3, and 102DDR4. It is suggested to amend the specification to remove the hyphens in all mentions of these drawing labels so that the specification will agree with the drawings.
Paragraph [0007] states, in the second sentence: “The semiconductor package assembly includes a bottom package and a top package.” Later, the second-to-last sentence of the same paragraph states: “The through via (TV) interconnects are disposed beside the first semiconductor die and the second semiconductor die and are arranged on a first package edge of the first package corresponding to the first edge of the first semiconductor die.” The examiner believes that “the first package” is referring to the “bottom package” that was previously introduced; therefore, “the first package” should most likely be amended to “the bottom package”.
Paragraph [0018] includes the following sentence (starting from line 12 of the paragraph): “The first semiconductor die 102 has an active surface 102a and a backside surface 102b opposite to the active surface 102a. The second semiconductor die 132 has an active surface 132a and a backside surface 132b opposite to the active surface 112a.” It appears that the last portion should be amended to “… opposite to the active surface 132a”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21–25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 21, starting from line 6 of page 8, the claim recites: “through via (TV) interconnects disposed beside the first semiconductor die and the second semiconductor die and arranged on a first package edge of the first package corresponding to the first edge of the first semiconductor die”. The term “the first package” lacks antecedent basis; rather, the second line of the claim on page 7 introduces “a bottom package”. Based on the examiner’s understanding of the claim in view of the drawings and specification, “the first package” should be changed to “the bottom package”.
Also regarding claim 21, in the last three lines of the claim, the way in which “the first interface” is mentioned twice, first as one of the two objects being electrically connected, and second as the means of electrically connecting the two objects, does not make logical sense. The examiner suggests the following modification to the last three lines of the claim to remedy this problem:
“a top package stacked on the bottom package and electrically connected to the first semiconductor die by the TV interconnects and the first interface rather than the second interface.”
Claims 22–24 depend on claim 21 and thus include by reference the problems described above in regard to claim 21.
Regarding claim 25, the claim states, in part: “The semiconductor package assembly as claimed in claim 21, wherein the top package comprises conductive structures arranged in a region of the memory package …” However, neither claim 25 nor claim 21 has introduced “a memory package”. Thus, the term “the memory package” lacks antecedent basis. Claim 21 introduced, in its last paragraph, “a top package”. Based on the examiner’s understanding of the claim in view of the drawings and specification, “the memory package” in claim 25 should be changed to “the top package” to agree with claim 21.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 is allowable. The closest prior art of US 2018/0012843 A1 (from the IDS, “Chen” hereinafter) teaches the following limitations from claim 1:
A semiconductor package assembly 100 (FIGS. 1–2, “package structure 100” ¶[0016]), comprising:
a first semiconductor die 200 (on the right side of FIGS. 1–2) and a second semiconductor die 200 (on the left side of FIGS. 1–2) arranged side-by-side, wherein the first semiconductor die 200 (right) comprises:
a first interface Int1 (see examiner’s annotation in FIG. 4) arranged on a first edge (top edge in FIG. 4) of the first semiconductor die 200 (on the right side of FIGS. 1–2); and
a second interface Int2 (see examiner’s annotation in FIG. 4) arranged on a second edge (left edge in FIG. 4) of the first semiconductor die 200 (on the right side of FIGS. 1–2) that is close to the second semiconductor die 200 (on the left side of FIGS. 1–2) and connected to the first edge (top edge in FIG. 4) (i.e., in FIG. 2, the left edge of the first semiconductor die 200 [on the right side of FIG. 2] is close to the second semiconductor die 200 [on the left side of FIG. 2], and in FIG. 4, the left edge of the first semiconductor die 200 is connected to the top edge of the first semiconductor die 200); and
a third semiconductor die (inside of the element 280; “the element 280 includes a package structure that contains one or more integrated circuit dies” ¶[0028]) stacked on the first semiconductor die 200 (on the right side of FIG. 1) and the second semiconductor die 200 (on the left side of FIG. 1).
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However, Chen fails to teach:
“wherein the third semiconductor die (inside element 280) is electrically connected to the first semiconductor die 200 (on the right side of FIGS. 1–2) by the first interface Int1 (see examiner’s annotation in FIG. 4), and wherein the first semiconductor die 200 (on the right side of FIGS. 1–2) is electrically connected to the second semiconductor die 200 (on the left side of FIGS. 1–2) by the second interface Int2 (see examiner’s annotation in FIG. 4).”
Chen’s specification does not describe an electrical connection between the two integrated circuit dies 200 in FIGS. 1–2. Chen states that “The redistribution structure 300 is electrically connected to the connectors 240 of the integrated circuit dies 200 and the conductive features 270” ¶[0022]. However, the fact that the two dies 200 are electrically connected to the redistribution structure 300 does not prove that the two dies 200 are electrically connected to each other. For instance, the redistribution structure 300 could have the function of routing the connectors 240 of the left and right dies 200 to separate external connectors 330 such that the left and right dies 200 do not share any electrical connections in common, as appears to be the case as drawn in FIG. 1.
Likewise, Chen does not describe an electrical connection between the third semiconductor die (inside element 280) and either one of the first or second semiconductor dies 200.
Furthermore, Chen does not distinguish between separate interfaces on the different edges of the integrated circuit die 200 in FIG. 4, although in the annotated FIG. 4 above, the examiner has chosen to label the group of connectors 240 near the top edge of the integrated circuit die 200 as belonging to a first interface “Int1”, and to label the group of connectors 240 near the left edge of the integrated circuit die 200 as belonging to a second interface “Int2”. Rather, Chen describes the connectors 240 as belonging to a single “ring region” along the periphery of each integrated circuit die 200 (“a ring region may be defined in the package structure 100. The ring region extends across the interface 340 and further extends along the interface 340 as viewed from a top view” ¶[0052]). There is no indication in Chen’s specification that different groupings of connectors 240, such as one group along the top edge and another group along the left edge of the integrated circuit die 200 in FIG. 4, are to be dedicated as different interfaces for connecting to different dies, such as the top-edge group of connectors 240 being used for connecting to the third semiconductor die (inside element 280 above the first/second semiconductor dies 200), and the left-edge group of connectors 240 being used for connecting to the second semiconductor die 200 (adjacently leftward of the first semiconductor die 200).
The prior art of US 2022/0367374 A1 (“Yu” hereinafter) discloses in FIG. 14 a device stack 400 that is a package-on-package arrangement sharing many features in common with the semiconductor package assembly of claim 1 of the present application, including a first semiconductor die 10 arranged side-by-side with a second semiconductor die 20, and a third semiconductor die 210 (i.e., either one of the stacked dies 210A or 210B) that is stacked on the first and second semiconductor dies 10 and 20.
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Yu’s third semiconductor die 210 is electrically connected with the first semiconductor die 10 as required by claim 1 (“the stacked dies 210 may be coupled to the integrated circuit dies 10 and 20 through the wire bonds 212, the bond pads 204 and 206, the conductive vias 208, the conductive connectors 138, the through vias 108, and the redistribution structure 114” ¶[0099]).
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As shown in FIG. 17, Yu’s first semiconductor die 10 has two groups of die connectors 66A and 66B, which may be considered analogous to the first and second interfaces of claim 1 of the present application. However, FIG. 17 also shows that the die connectors 66A and 66B are spread across the bottom surface of the first semiconductor die 10; thus, the die connectors 66A and 66B do not meet the requirements of claim 1 of the present application that the first and second interfaces are arranged on edges of the first semiconductor die 10.
Also, Yu explains that the difference between the die connectors 66A and 66B is that the die connectors 66A have a greater pitch than the die connectors 66B: “The die connectors 66A and 66B are electrically coupled to the respective integrated circuits of the integrated circuit die 10. In some embodiments, a width W1 of the die connectors 66A is greater than a width W2 of the die connectors 66B. In some embodiments, a pitch P1 of the die connectors 66A is greater than a pitch P2 of the die connectors 66B” ¶[0056]. Yu does not indicate that the die connectors 66A and 66B serve as two separate interfaces to provide electrical connection to two separate dies, as required by claim 1 of the present application.
Claims 2–13 are allowable at least for the reason that they depend on allowable claim 1.
Claim 14 is allowable. The closest prior art of Chen and Yu, as cited above in regard to claim 1, either singularly or in combination fails to anticipate or render obvious
“a first interface arranged on a first edge of the first semiconductor die; and
a second interface arranged on a second edge of the first semiconductor die that is close to the second semiconductor die and adjacent to the first edge; and
through via (TV) interconnects disposed beside the first semiconductor die and the second semiconductor die and arranged on a first package edge of the fan-out package corresponding to the first edge of the first semiconductor die; and
a memory package stacked on the fan-out package and electrically connected to the second semiconductor die by the TV interconnects, the first interface and the second interface”
in combination with all other limitations in the claim as claimed and defined by applicant.
In the above quotation from claim 14, the examiner understands “corresponding to” to require that the first package edge of the fan-out package and the first edge of the first semiconductor die are edges in a same lateral direction. For instance, in FIG. 9 of the present application, the first package edge 312E1 of the fan-out package 312 “corresponds to” the first edge 102E1 of the first semiconductor die 102 in the sense that both 312E1 and 102E1 are “top” edges of their respective structures as seen in the top-down view of FIG. 9 (“top edge” here meaning that these are edges in the +110 direction). Paragraph [0037] explains that the proximity of the first package edge 312E1 (where the TV interconnects 314 are located) to the first edge 102E1 (where the first interface 102DDR1 of the first semiconductor die 102 is located) allows for short routing paths (e.g., the routing paths 316P of the front-side RDL structure).
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Comparing with the prior art, Yu’s stacked dies 210 in FIG. 14 are “stacked memory dies” ¶[0097] and therefore the top package 200 that includes the stacked dies 210 may be considered as the “memory package” of claim 1 of the present application. However, FIG. 5 shows that Yu’s through via (TV) interconnects 108 (“through vias 108” ¶[0068]) are arranged adjacent to the entire periphery of the bottom package 100, not specifically on a single edge of the package 100 corresponding to the first edge of the first semiconductor die where the first interface is to be located, as required by claim 14 of the present application.
As explained above in regard to claim 1, Yu’s connectors 66A and 66B do not meet the requirements for the first interface and second interface of the first semiconductor die 10 because the connectors 66A and 66B in FIG. 17 are spread across the bottom surface of the first semiconductor die 10, not just along a first edge (as required for the first interface) and along a second edge adjacent to the first edge (as required for the second interface).
Furthermore, claim 14 of the present application specifically requires that the second semiconductor die is electrically connected to the memory package through the first interface and second interface of the first semiconductor die; that is, the first semiconductor die acts as a “go between” to connect the second semiconductor die to the memory package. However, Yu states: “the stacked dies 210 may be coupled to the integrated circuit dies 10 and 20 through the wire bonds 212, the bond pads 204 and 206, the conductive vias 208, the conductive connectors 138, the through vias 108, and the redistribution structure 114” ¶[0099]. That is, according to Yu, each of the first semiconductor dies 10 and 20 is connected to the stacked dies 210 of the memory package 200 in the same way (through the redistribution structure 114, the through vias 108, etc.); therefore, Yu’s first semiconductor die 10 does not act as a “go between” to connect the second semiconductor die 20 to the memory package 200.
Claims 15–20 are allowable at least for the reason that they depend on allowable claim 14.
Claim 21 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. The closest prior art of Chen and Yu, as cited above in regard to claim 1, either singularly or in combination fails to anticipate or render obvious
“a first interface arranged on a first edge of the first semiconductor die;
a second interface arranged on a second edge of the first semiconductor die that is close to the second semiconductor die and connected to the first edge; and
a third interface arranged on a third edge connected to the first edge and opposite the second edge; and
through via (TV) interconnects disposed beside the first semiconductor die and the second semiconductor die and arranged on a first package edge of corresponding to the first edge of the first semiconductor die; and
a top package stacked on the bottom package and electrically connected to the first semiconductor die by the TV interconnects and the first interface rather than the second interface”
in combination with all other limitations in the claim as claimed and defined by applicant.
Claims 22–24 would be allowable (if the rejection of claim 21 under 35 USC 112(b) were overcome) at least for the reason that they depend on claim 21, which contains allowable subject matter as described above.
Claim 25 would be allowable if both claims 25 and 21 were rewritten or amended to overcome the rejections of claims 25 and 21 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Claim 25 would be allowable at least for the reason that it depends on claim 21, which contains allowable subject matter as described above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2019/0378827 A1 (from the IDS)—FIG. 11 shows a similar package-on-package structure to that disclosed in the Chen and Yu references cited above.
US 2021/0272906 A1—FIG. 8 shows a similar package-on-package structure to that disclosed in the Chen and Yu references cited above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam J Mott whose telephone number is (571)272-2367. The examiner can normally be reached Mon-Fri 8:30AM-5:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.J.M./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
Prosecution Insights