Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 is objected to because of the following informalities: Claim 3 states that the forth number is less than the fourth number. Examiner believes it should state that the third number is less than the fourth number. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, and 12-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kajigaya (US PGPub 2008/0259707).
Claim 1: Kajigaya teaches an apparatus comprising: a three dimensional non-volatile memory array that includes non-volatile memory cells (MC); and a control circuit below the three dimensional non-volatile memory array and configured to control the three dimensional non-volatile memory array (Fig. 16), the control circuit including: a first number of sense amplifier tiers (11), each comprising a plurality of sense amplifiers (SA) arranged as a contiguous group along a first axis, wherein the sense amplifier tiers are spaced from one another along a second axis that is perpendicular to the first axis; a second number of bit line switch regions, each comprising bit line switches (TS0, TS1), each bit line switch coupled to a corresponding one of the sense amplifiers, the second number greater than the first number, wherein the bit line switch regions are arranged along the second axis and each sense amplifier tier is adjacent a corresponding one of the bit line switch regions; and a plurality of cross bit lines (BL) routed along an axis parallel to the first axis and arranged along a second axis perpendicular to the first axis, each cross bit line coupled to a corresponding one of the bit line switches, wherein each bit line switch is configured to selectively couple a corresponding one of the cross bit lines to a corresponding one of the sense amplifiers (Fig. 1).
Claim 2: Kajigaya teaches (Fig. 1) each sense amplifier tier includes a third number of sense amplifiers, each bit line switch region includes a fourth number of bit line switches, and the third number does not equal the fourth number.
Claim 3: Kajigaya teaches (Fig. 1) the third number is less than the fourth number.
Claim 7: Kajigaya teaches (Fig. 1) fewer than all of the plurality of cross bit lines are routed above the sense amplifiers. Fewer can equal zero.
Claim 12: Kajigaya teaches (Fig. 1, 16) (see claim 1) A system comprising: a control die comprising a control circuit for a three dimensional non-volatile memory array, the control circuit comprising: a sense amplifier region comprising sense amplifiers arranged as a contiguous group along a first axis and cross bit lines routed along an axis parallel to the first axis; and arranged along a second axis that is perpendicular to the first axis, each cross bit line coupled to a corresponding one of the sense amplifiers; and a peripheral region comprising circuits other than sense amplifiers, the peripheral region disposed separate from the sense amplifier region, wherein a first plurality of the cross bit lines are routed above the peripheral region.
Claim 13: Kajigaya teaches (Fig. 1) the sense amplifier region further comprises bit line switches, each coupled to a corresponding one of the sense amplifiers and a corresponding one of the cross bit lines.
Claim 14: Kajigaya teaches (Fig. 1) each bit line switch is configured to selectively couple a corresponding one of the cross bit lines to a corresponding one of the sense amplifiers.
Claim 15: Kajigaya teaches (Fig. 1) the sense amplifiers are disposed in a first number of sense amplifier tiers, and the bit line switches are disposed in a second number of bit line switch regions, the second number greater than the first number.
Claim 16: Kajigaya teaches (Fig. 1) the sense amplifier region further comprises: a sense amplifier tier comprising a third number of the sense amplifiers; and a bit line switch region comprising a fourth number of the bit line switches, wherein and the third number is greater than the fourth number.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5, 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (US PGPub 20210210506), as applied to claims 1 and 12 above, and further in view of Xu et al. (US PGPub 2022/0246208)
Regarding claims 10, as described above, Yan substantially reads on the invention as claimed, except Yan does not teach a memory die comprising the three dimensional non-volatile memory array and a first set of bond pads connected to the three dimensional non-volatile memory array; and a control die comprising the control circuit and a second set of bond pads, the first set of bond pads connected to the second set of bond pads. Xu teaches (Fig. 5A,B) [0084] a memory die comprising the three dimensional non-volatile memory array and a first set of bond pads connected to the three dimensional non-volatile memory array; and a control die comprising the control circuit and a second set of bond pads, the first set of bond pads connected to the second set of bond pads. Connecting chips using bond pads is common in the art of semiconductors. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught Yan to have used bond pads to connect the memory chip to the control die as it is well known in the art of semiconductors.
Regarding claims 18, as described above, Yan substantially reads on the invention as claimed, except Yan does not teach a memory die comprising the three dimensional non-volatile memory array and a first set of bond pads connected to the three dimensional non-volatile memory array and to a second set of bond pads on the control die. Xu teaches (Fig. 5A,B) [0084] a memory die comprising the three dimensional non-volatile memory array and a first set of bond pads connected to the three dimensional non-volatile memory array and to a second set of bond pads on the control die. Connecting chips using bond pads is common in the art of semiconductors. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught Yan to have used bond pads to connect the memory chip to the control die as it is well known in the art of semiconductors.
Regarding claims 4, as described above, Yan substantially reads on the invention as claimed, except Yan does not teach a first of the bit line switches is coupled to a first sense amplifier; a second of the bit line switches is coupled to a second sense amplifier; the first bit line switch is disposed adjacent the first sense amplifier; and the second bit line switch is not disposed adjacent the second sense amplifier. Xu teaches (Fig. 9) [0128-0134] a first of the bit line switches is coupled to a first sense amplifier; a second of the bit line switches is coupled to a second sense amplifier; the first bit line switch is disposed adjacent the first sense amplifier; and the second bit line switch is not disposed adjacent the second sense amplifier to mitigate issues with voltage or resistance variations. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Ya to have the structure claimed to mitigate issues with voltage or resistance variations as taught by Xu [0128-0134].
Claim 5: Xu teaches (Fig. 9) [0128-0134] a first of the bit line switches is coupled to a first one of the sense amplifiers disposed in an adjacent sense amplifier tier; and a second of the bit line switches is coupled to a second one of the sense amplifiers disposed in a non-adjacent sense amplifier tier.
Claim(s) 6, 8-9, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kajigaya (US PGPub 2008/0259707), as applied to claims 1 and 12 above, and further in view of Yan et al. (US PGPub 2021/0210506).
Regarding claim 6, as described above, Kajigaya substantially reads on the invention as claimed, except Kajigaya do not teach one of the bit line switches is coupled via a routing through a first sense amplifier tier to a sense amplifier disposed in a second sense amplifier tier. Yan teaches (Fig. 3) one of the bit line switches is coupled via a routing through a first sense amplifier tier to a sense amplifier disposed in a second sense amplifier tier to accommodate decreased footprint architecture [0063]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Kajigaya to have had one of the bit line switches is coupled via a routing through a first sense amplifier tier to a sense amplifier disposed in a second sense amplifier tier to accommodate decreased footprint architecture as taught by Yan [0063].
Claim 8: Yan teaches (Fig. 2a) the control circuit further comprises a first region comprising the sense amplifier tiers and the bit line switch regions, and a second region adjacent the first region, wherein some of the cross bit lines are routed above the second region.
Claim 9: Yan teaches (Fig. 2a) the control circuit further comprises a plurality of bit lines comprising a bit line pitch, each of the bit line coupled to a corresponding one of the cross bit lines, the cross bit lines comprising a cross bit line pitch greater than the bit line pitch.
Claim 11: Yan teaches (Fig. 3) second number is two more than the first number.
Claim 17: Yan teaches (Fig. 2a) a second plurality of the cross bit lines are routed above the sense amplifier region.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at 5712721705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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