DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Zhan et al. (US 20180012814 A1, hereinafter Zahn‘814) in view of Sakai (US 6020618 A, hereinafter Sakai‘618).
Regarding independent claim 1, Zahn‘814 teaches, “A semiconductor device (fig. 1-14; ¶ [0021] - ¶ [0076]) comprising:
a semiconductor substrate (wafer 10, fig. 1 and SUB in fig. 6) ((of a first conductivity type)) having a main surface;
a plurality of first areas (11, fig. 1-2) provided on the main surface;
a second area (12) provided on the main surface between the first areas (11); and
an evaluation element (TA/TA1..Tan, fig. 2-7) in the second area (12),
wherein the evaluation element (fig. 6) includes:
a first semiconductor region (21) of a second conductivity type (N) opposite to the first conductivity type (P) formed in the second area (12);
a second semiconductor region (23) of the first conductivity type (P) formed on an upper surface of the first semiconductor region (21);
a first electrode pad (P2) electrically connected to the first semiconductor region (21) and provided to a reference voltage to the first semiconductor region (21, ¶ [0006]); and
a second electrode pad (P1) electrically connected to the second semiconductor region (23) and provided to a voltage lower than the reference voltage to the second semiconductor region (¶ [0035]), and
wherein the second semiconductor region (23) has a minimum depth portion of the second semiconductor region (23) in a cross-sectional view”.
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But Zahn‘814 is silent upon the provision of wherein the semiconductor substrate is of a first conductivity type.
However, Sakai‘618 teaches a similar device (fig. 3), wherein the semiconductor substrate (7) is of a first conductivity type (P).
Zahn‘814 and Sakai‘618 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zahn‘814 with the features of Sakai‘618 because they are from the same field of endeavor.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Zahn‘814 and Sakai‘618 to dope the substrate with p type doping according to the teachings of Sakai‘618 as this is conventional in the semiconductor field as this allows building n-channel transistors without additional doping and layer.
Regarding claim 2, Zahn‘814 modified with Sakai‘618 further teaches, “The semiconductor device according to claim 1, wherein the first semiconductor region (21, fig. 6, Zahn‘814) is a region introduced n-type impurities, and the second semiconductor region (23) is a region introduced p-type impurities opposite to the n-type impurities”.
Regarding claim 3, “The semiconductor device according to claim 1, wherein the first semiconductor region is a region introduced p-type impurities, and the second semiconductor region is a region introduced n-type impurities opposite to the p-type impurities”, Zahn‘814 modified with Sakai‘618 teaches a P-type substrate, N-type well to form P-anode and N-cathode of a diode. However, this is conventional and widely known in the relevant field of using opposing polarity of substrate (N-type) and well (P-well) to form similar anode and cathode which meets the instant limitataion.
Regarding claim 4, Zahn‘814 modified with Sakai‘618 further teaches, “The semiconductor device according to claim 2, wherein the first semiconductor region (21, fig. 6, Zahn‘814) and the second semiconductor region are (23) configured a PN-junction diode (D1, fig. 4-6, Zahn‘814).
Regarding claim 5, “The semiconductor device according to claim 1, wherein a shape of an interface between the first semiconductor region and the second semiconductor region in the minimum depth portion of the second semiconductor region is a concave shape in a direction toward the main surface”, Zahn‘814 modified with Sakai‘618 further teaches, first semiconductor region, second semiconductor region, but may not be explicit on the shape of the interface. However, the applicant does not cite any evidence showing the criticality of this shape. The shape of the interface is a matter of choice which a person skilled in the art would have found obvious absent persuasive evidence that the particular shape of the claimed limitation was significant, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04.
Regarding claim 6, “The semiconductor device according to claim 1, wherein a depth of the minimum depth potion of the second semiconductor region is 40nm or more and 200nm or less”, Zahn‘814 modified with Sakai‘618 does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 7, Zahn‘814 modified with Sakai‘618 further teaches, “The semiconductor device according to claim 1, wherein a plurality of evaluation elements (TA, fig. 2, Zahn‘814) is formed in the second area (12), and depths of the minimum depth portion of a plurality of second semiconductor region in each of the plurality of evaluation elements is different each other”.
Regarding claim 8, “The semiconductor device according to claim 7, wherein the depths of the minimum depth potion of the plurality of second semiconductor region in each of the plurality of evaluation elements is 40nm or more and 200nm or less”, Zahn‘814 modified with Sakai‘618 does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 9, Zahn‘814 modified with Sakai‘618 further teaches, “The semiconductor device according to claim 4, wherein a reverse-voltage is applied to the PN-junction diode via the first electrode pad and the second electrode pad (¶ [0056], ¶ [0059], Zahn‘814). Also, a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2144.02. Also, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See MPEP 2112.01.
Regarding claim 10, Zahn‘814 modified with Sakai‘618 further teaches, “The semiconductor device according to claim 1, wherein the plurality of first areas (11, fig. 1, Zahn‘814) is a plurality of semiconductor chip areas, and the second area (12) is a scribe area demarcating the plurality of semiconductor chip areas”.
Regarding claim 11, Zahn‘814 modified with Sakai‘618 further teaches, “The semiconductor device according to claim 1, wherein the plurality of first areas (11, fig. 1, Zahn‘814) is a plurality of cell region in a plurality of first areas, and the second area (12) is an outer peripheral region in the plurality of first areas”.
Response to Arguments
Applicant's arguments filed 06/22/2026 have been fully considered but they are not persuasive.
Applicant argues:
[Page 8] of REMARKS,
Applicant respectfully submits that the cited references, taken individually or in combination, fail to disclose or suggest the features of amended independent claim 1, particularly with respect to the features of "a second semiconductor region of the first conductivity type formed on an upper surface of the first semiconductor region."
For example, the Office maps the claimed first and second semiconductor regions to the source/drain regions of the n-channel MISFET Qn and the p-channel MISFET Qp, respectively, in Asayama's FIG. 5. But these belong to two different transistors, and Asayama states that Qn and Qp "are isolated from each other by an element isolation insulating film 4." (See Asayama, [0092].) The source/drain of Qp is thus separated from the source/drain of Qn by the isolation film, not formed on an upper surface of it as amended independent claim 1 describes.
Accordingly, Asayama does not disclose or even suggest the features of "a second semiconductor region of the first conductivity type formed on an upper surface of the first semiconductor region."
Zhan in view of Sakai does not appear to remedy the deficiencies of Asayama.
Examiner’s reply:
The office disagrees.
Referring to fig. 6 of Zhan et al. (US 20180012814 A1), the P-type second semiconductor region (23) is on the upper surface of the first semiconductor region (21).
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The term “ON” here is explained using broadest reasonable interpretation. “ON” is a directional phrase, meaning an object can be above or bottom or left or right of another object with or without other objects in between. Also, the object can be in direct contact with or near or next to or adjacent to or covering the another object.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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