DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I (semiconductor device) reflected in claims 1-11 in the reply filed on 11/17/2025 is acknowledged. Claims 12-15 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-8, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Asayama et al. (US 20030006795 A1, hereinafter Asayama‘795).
Regarding independent claim 1, Asayama‘795 teaches, “A semiconductor device (fig. 1-22; ¶ [0049] - ¶ [0167]) comprising:
a semiconductor substrate (SW in fig. 1, substrate 1 in fig. 5) of a first conductivity type (P) having a main surface;
a plurality of first areas (CP, fig. 1) provided on the main surface;
a second area (SL, fig. 1) provided on the main surface between the first areas (CP);
an evaluation element (TEG/SL1, SL2, fig. 2A-2B) in the second area;
wherein the evaluation element (TEG, fig. 5) includes;
a first semiconductor region (11, 12, see annotation, S/D region of Qn transistor) of a second conductivity type (N) opposite to the first conductivity type (P) formed in the second area (SL),
a second semiconductor region (see annotation, S/D region of Qp transistor) of the first conductivity type (P) formed on the first semiconductor region (see annotation, S/D region of Qn transistor),
a first electrode pad (BP1, see annotation) electrically connected to the first semiconductor region and provided to a reference voltage to the first semiconductor region, and
a second electrode pad (BP1, see annotation) electrically connected to the second semiconductor region and provided to a voltage ((lower than the reference voltage to the second semiconductor region)),
wherein the second semiconductor region (S/D region of Qp transistor) has a minimum depth potion of the second semiconductor region (of portion 12) in a cross-sectional view”.
Regarding the limitataion, ‘a first electrode pad … provided to a reference voltage to the first semiconductor region, and a second electrode pad .. provided to a voltage lower than the reference voltage to the second semiconductor region’, Asayama‘795 teaches, ‘each of the first electrode pads BP1 is an isolated pattern having no wire-connection with other electrodes’ (¶ [0084]). Thus, as the mapped first electrode and the second electrode are isolated electrode pads, different potentials can be applied to these two electrodes (BP1 and BP1). Regarding applying lower reference voltages to one electrode pad than the other, Asayama‘795 may not be explicitly mentioning this operating feature, however, this operational language is merely a way to operate the same analogous device structure. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2144.02. Also, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See MPEP 2112.01.
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Regarding claim 2, Asayama‘795 further teaches, “The semiconductor device according to claim 1, wherein the first semiconductor region (S/D region of transistor Qn) is a region introduced n-type impurities, and the second semiconductor region (S/D region of transistor Qp) is a region introduced p-type impurities opposite to the n-type impurities”.
Regarding claim 3, Asayama‘795 further teaches, “The semiconductor device according to claim 1, wherein the first semiconductor region is a region introduced p-type impurities, and the second semiconductor region is a region introduced n-type impurities opposite to the p-type impurities (by mapping the S/D region of transistor Qp and Qn to the first and second semiconductor region respectively)”.
Regarding claim 5, Asayama‘795 further teaches, “The semiconductor device according to claim 1, wherein a shape of an interface between the first semiconductor region and the second semiconductor region in the minimum depth potion of the second semiconductor region is a concave shape in a direction toward the main surface” (mapping element 3, 3a as first semiconductor region and S/D region of Qp as second semiconductor region in fig. 5).
Regarding claim 6, “The semiconductor device according to claim 1, wherein a depth of the minimum depth potion of the second semiconductor region is 40nm or more and 200nm or less”, Asayama‘795 does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 7, Asayama‘795 further teaches, “The semiconductor device according to claim 1, wherein a plurality of evaluation elements (TEG, fig. 5, fig. 7) is formed in the second area (SL1), and depths of the minimum depth potion of a plurality of second semiconductor region (minimum depth of S/D regions in fig. 5 and 7 are different) in each of the plurality of evaluation elements is different each other”.
Regarding claim 8, “The semiconductor device according to claim 7, wherein the depths of the minimum depth potion of the plurality of second semiconductor region in each of the plurality of evaluation elements is 40nm or more and 200nm or less”, Asayama‘795 does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 10, Asayama‘795 further teaches, “The semiconductor device according to claim 1, wherein the plurality of first areas (CP, fig. 1) is a plurality of semiconductor chip areas, and the second area (SL) is a scribe area demarcating the plurality of semiconductor chip areas”.
Regarding claim 11, Asayama‘795 further teaches, “The semiconductor device according to claim 1, wherein the plurality of first areas (CP) is a plurality of cell region (chip) in a plurality of first areas, and the second area (SL/SL1, SL2) is an outer peripheral region (scribe region) in the plurality of first areas”.
Claims 1-2, 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Zhan et al. (US 20180012814 A1, hereinafter Zahn‘814) in view of Sakai (US 6020618 A, hereinafter Sakai‘618).
Regarding independent claim 1, Zahn‘814 teaches, “A semiconductor device (fig. 1-14; ¶ [0021] - ¶ [0076]) comprising:
a semiconductor substrate (wafer 10, fig. 1 and SUB in fig. 6) ((of a first conductivity type)) having a main surface;
a plurality of first areas (11, fig. 1-2) provided on the main surface;
a second area (12) provided on the main surface between the first areas (11);
an evaluation element (TA/TA1..Tan, fig. 2-7) in the second area (12);
wherein the evaluation element (fig. 6) includes;
a first semiconductor region (21) of a second conductivity type (N) opposite to the first conductivity type (P) formed in the second area (12),
a second semiconductor region (23) of the first conductivity type (P) formed on the first semiconductor region (21),
a first electrode pad (P2) electrically connected to the first semiconductor region (21) and provided to a reference voltage to the first semiconductor region (21, ¶ [0006]), and
a second electrode pad (P1) electrically connected to the second semiconductor region (23) and provided to a voltage lower than the reference voltage to the second semiconductor region (¶ [0035]),
wherein the second semiconductor region (23) has a minimum depth potion of the second semiconductor region (23) in a cross-sectional view”.
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But Zahn‘814 is silent upon the provision of wherein the semiconductor substrate is of a first conductivity type.
However, Sakai‘618 teaches a similar device (fig. 3), wherein the semiconductor substrate (7) is of a first conductivity type (P).
Zahn‘814 and Sakai‘618 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zahn‘814 with the features of Sakai‘618 because they are from the same field of endeavor.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Zahn‘814 and Sakai‘618 to dope the substrate with p type doping according to the teachings of Sakai‘618 as this is conventional in the semiconductor field as this allows building n-channel transistors without additional doping and layer.
Regarding claim 2, Zahn‘814 modified with Sakai‘618 further teaches, “The semiconductor device according to claim 1, wherein the first semiconductor region (21, fig. 6, Zahn‘814) is a region introduced n-type impurities, and the second semiconductor region (23) is a region introduced p-type impurities opposite to the n-type impurities”.
Regarding claim 4, Zahn‘814 modified with Sakai‘618 further teaches, “The semiconductor device according to claim 2, wherein the first semiconductor region (21, fig. 6, Zahn‘814) and the second semiconductor region are (23) configured a PN-junction diode (D1, fig. 4-6, Zahn‘814).
Regarding claim 9, Zahn‘814 modified with Sakai‘618 further teaches, “The semiconductor device according to claim 4, wherein a reverse-voltage is applied to the PN-junction diode via the first electrode pad and the second electrode pad (¶ [0056], ¶ [0059], Zahn‘814). Also, a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2144.02. Also, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See MPEP 2112.01.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817