Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Semiconductor device including a plurality of gate lines on a plurality of fin structure having different width portions”
Specification
Number of figures submitted does not match the number of figures listed under Brief Description of Drawings in the specification. All of the figures with alphabets should be listed separately. For example, ‘Figs. 1A-1C’ should be ‘Figs. 1A, 1B and 1C’.
In particular, ‘FIGS. 4A to 4C’ in the paragraph [0013], ‘FIGS. 5A to 12A’ in the paragraph [0014] and ‘FIGS. 18A to 18C’ in the paragraph [0020] are objected.
See MPEP 500 - Receipt and Handling of Mail and Papers, MPEP 507 - Drawing Review in the Office of Patent Application Processing (OPAP). This labeling convention ensures clarity and consistency in referencing figures throughout the patent application and publication. Improper labeling may result in an objection from OPAP and require correction.
Additionally, paragraphs [0001] and [0002] on page 27 of SPEC are duplicates, as the same paragraph numbers are already listed on page 1. These duplicate numbers should be corrected.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11, 13 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang (US 20230402444).
Regarding claim 1. Fig 1 of Huang discloses A semiconductor device, comprising:
a substrate 102 [0040];
a first fin structure (the topmost fin 106b/106c) extending on the substrate in a first direction (Y), and having a first fin portion 106c having a first width (T3) in a second direction (X) crossing the first direction and a second fin portion 106b having a second width (T2) in the second direction, greater than the first width [0027];
a second fin structure (the lowermost fin 106b) extending on the substrate in the first direction, and having the second width (T2) in the second direction;
a plurality of first gate lines (the gate lines 112c in the cell 123 and cell 124) that comprises a first gate line 112c [0030], on the first fin portion of the first fin structure and the second fin structure (Fig 1: 112c crossing right end of the 106c of the first fin portion of the first fin, and also crossing left end of the 106b in the second fin), wherein the plurality of first gate lines is extending in the second direction;
a plurality of second gate lines (the gate lines 114b in the cell 123 and cell 124) that comprises a second gate line 114b [0032], on the second fin portion of the first fin structure and the second fin structure (Fig 1), wherein the plurality of second gate lines is extending in the second direction;
a third gate line 112b [0030] on the second fin structure, wherein the third gate line is extending in the second direction between the first gate line and the second gate line (Fig 1); and
a device isolation pattern 104 connected to an end portion of the third gate line, and extending between the first fin portion of the first fin structure and the second fin portion of the first fin structure (Fig 1, [0023]-[0025]/[0036]: ‘provide isolation between adjacent FETs’, each fin and gate line are separated by isolation feature 104, and 104 is connected each left and right end along Y direction of third gate line).
Regarding claim 11. Huang discloses The semiconductor device of claim 1, wherein each of the first and second fin structures comprises a plurality of channel layers 130 [0030]/[0043] spaced apart from each other in a third direction perpendicular to an upper surface of the substrate (Fig 2A),
wherein each of the first, second, and third gate lines comprises a gate electrode on the plurality of channel layers and extending in the second direction, a gate insulating film between the plurality of channel layers and the gate electrode, and a gate capping layer on the gate electrode (Fig 1/Fig 2A).
Regarding claim 13. Huang discloses The semiconductor device of claim 1, further comprising:
first source/drain regions 126 (left) respectively disposed in the first fin structure on opposing sides of each of the first and second gate lines (Fig 2A), and
second source/drain regions 126 (right) respectively disposed in the second fin structure on opposing sides of each of the first to third gate lines (Fig 2A).
Regarding claim 15. Fig 1 and Fig 2A (a lateral portion view of Fig 1) of Huang disclose A semiconductor device, comprising:
a substrate 102;
a first fin structure (the topmost fin 106b/106c) extending on the substrate in a first direction (Fig 1: Y), and having a first fin portion 106c having a first width (T3) in a second direction (X) crossing the first direction and a second fin portion 106b having a second width (T2), greater than the first width [0027], in the second direction;
a second fin structure (the lowermost fin 106b) extending on the substrate in the first direction, and having the second width (T2) in the second direction;
first gate lines (the gate lines 112c in the cell 123 and cell 124) on the first fin portion and the second fin structure, and extending in the second direction (Fig 1: 112c crossing right end of the 106c of the first fin portion of the first fin, and also crossing left end of the 106b in the second fin);
second gate lines (the gate lines 114b in the cell 123 and cell 124) on the second fin portion and the second fin stricture, and extending in the second direction;
a third gate line 112b [0030] on the second fin structure, and extending in the second direction between the first gate lines and the second gate lines, the first and second gate lines and the third gate line being arranged at a same pitch (P) in the first direction (Fig 1);
a first epitaxial pattern 126 (left) on the first fin portion, wherein the first epitaxial pattern is adjacent to the second fin portion (Fig 2A);
a second epitaxial pattern 126 (right) on the second fin portion, wherein the second epitaxial pattern is adjacent to the first fin portion (Fig 2A); and
a device isolation pattern 104 separating the first fin portion and the second fin portion between the first epitaxial pattern and the second epitaxial pattern, and connected to an end portion of the third gate line (Fig 1, [0023]-[0025]/[0036]: ‘provide isolation between adjacent FETs’, each fin and gate line are separated by isolation feature 104, and 104 is connected each left and right end along Y direction of third gate line).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20230402444).
Regarding claim 2. Huang discloses The semiconductor device of claim 1, wherein the first gate line has a first gate width in the first direction, the second gate line has a second gate width in the first direction, and the third gate line has a third gate width in the first direction (Fig 5).
But Huang does not explicitly disclose wherein the first gate width of the first gate line, the second gate width of the second gate line, and the third gate width of the third gate line are equal to each other.
However, Huang discloses each gate line is formed by one-pitch spacing with substantially same dimension [0054] and further Fig 1 of Huang discloses substantially same width of each gate lines.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the widths of Huang’s each gate line are equal to each other.
Regarding claim 3. Huang discloses The semiconductor device of claim 2, wherein the plurality of first gate lines are arranged at a first pitch (P) in the first direction, the plurality of second gate lines are arranged at a second pitch (P) in the first direction, the first gate line and the third gate line are arranged at a third pitch (P) in the first direction, and the second gate line and the third gate line are arranged at the third pitch in the first direction (Fig 1), and
wherein the first pitch, the second pitch, and the third pitch are equal to each other (Fig 1, [0088]: P).
Regarding claim 4. Huang discloses The semiconductor device of claim 3,
wherein the first width of the first fin portion and the second width of the second fin portion are uniform along the first direction (Fig 1).
Regarding claim 14. Huang discloses The semiconductor device of claim 13, wherein the device isolation pattern is positioned between adjacent first source/drain regions among the first source/drain regions, and has a surface that is lower than lower surfaces of the adjacent first source/drain regions relative to the substrate (Fig 2A, [0025]: the top surface of source/drain above top surface of fin structures, and Huang discloses ‘fin structures … above the isolation features 104’. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Huang discloses the claimed feature).
Regarding claim 16. Huang discloses The semiconductor device of claim 15. But Huang does not explicitly disclose wherein each of the first and second gate lines has the same width as each other in the first direction, and the third gate line has the same width in the first direction as the width of each of the first and second gate lines in the first direction.
However, Huang discloses each gate line is formed by one-pitch spacing with substantially same dimension [0054] and further Fig 1 of Huang discloses substantially same width of each gate lines.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the widths of Huang’s each gate line are equal to each other.
Allowable Subject Matter
Claims 19-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 19. Fig 1 of Huang discloses some of the claimed features including A semiconductor device, comprising:
a substrate 102 [0040];
a first fin structure (the topmost fin 106b/106c) extending on the substrate in a first direction (Fig 1: Y), and having a first fin portion 106c having a first width (T3) in a second direction (X) crossing the first direction and a second fin portion having a second width (T2) in the second direction, greater than the first width [0027];
a second fin structure (the lowermost fin 106b) extending on the substrate in the first direction, and having the second width (T2) in the second direction;
first gate lines (the gate lines 112c in the cell 123 and cell 124) extending in the second direction on the first fin portion and the second fin structure (Fig 1: 112c crossing right end of the 106c of the first fin portion of the first fin, and also crossing left end of the 106b in the second fin), and arranged at a first pitch (P) in the first direction;
second gate lines (the gate lines 114b in the cell 123 and cell 124) extending in the second direction on the second fin portion and the second fin structure, and arranged at the first pitch in the first direction (Fig 1);
a third gate line 112b [0030] on the second fin structure, wherein the third gate line is extending in the second direction between the first gate lines and the second gate lines (Fig 1),
a first epitaxial pattern 126 (left) on the first fin portion, wherein the first epitaxial pattern is adjacent to the second fin portion;
a second epitaxial pattern 126 (right) on the second fin portion, wherein the second epitaxial pattern is adjacent to the first fin portion; and
a device isolation pattern 104 separating the first fin portion and the second fin portion between the first epitaxial pattern and the second epitaxial pattern, and connected to an end portion of the third gate line (Fig 1, [0023]-[0025]/[0036]: ‘provide isolation between adjacent FETs’, each fin and gate line are separated by isolation feature 104, and 104 is connected each left and right end along Y direction of third gate line).
However, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, in particular, the specific requirement of pitch size of gate line, “the third gate line is arranged with the first and second gate lines, adjacent thereto, at a second pitch in the first direction, greater than the first pitch”.
Claims 5-9, 12 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the first fin portion of the first fin structure comprises a first tapered portion in contact with the device isolation pattern, and the first tapered portion has a width in the second direction, increasing toward the device isolation pattern”.
Regarding claim 6. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the first fin portion of the first fin structure comprises a second tapered portion in contact with the device isolation pattern, and the second tapered portion has a width in the second direction decreasing toward the device isolation pattern”.
Regarding claim 7. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the first gate width and the second gate width are equal to each other, and the third gate width is greater than the first and second gate widths”.
Regarding claim 12. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “each of the first, second, and third gate lines comprises a gate insulating film on the active fin, a gate electrode on the gate insulating film, and a gate capping layer on the gate electrode”.
Regarding claim 17. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “each of the first and second gate lines has the same width as each other in the first direction, and the third gate line has a width in the first direction, greater than each width of the first and second gate lines in the first direction”.
Regarding claim 18. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the first gate lines and the second gate lines are arranged at a first distance from each other and a second distance from each other, respectively, and respective distances between the device isolation pattern and the first and second gate lines, adjacent thereto are smaller than the first distance and the second distance, respectively”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812