Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1 – 16) in the reply filed on 2/25/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 5, 7 – 13, 15 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakamoto (US 20160095219).
Regarding claim 1, Sakamoto discloses a wiring substrate, comprising:
an insulating layer (102, 104, 106, 108; Fig. 1); and
a conductor layer (101, 103, 111) formed on a surface of the insulating layer and including a plurality of wiring patterns (101) such that the conductor layer includes an upper layer (101b) comprising a plating film (the electrolytic plating layer 101b) and a lower layer (101a) comprising a seed layer (the seed layer 101a) for the plating film and directly formed on the surface of the insulating layer,
the plurality of wiring patterns has a minimum wiring width of 5 µm or less (paragraph 41) and a minimum inter-wiring distance of 7 µm or less (paragraph 41), and each of the wiring patterns has an aspect ratio in a range of 2.0 to 4.0 (the aspect ratio of the conductor pattern 134, Fig.1, appears to be in a range of 2.0 to 4.0).
Regarding claim 2, Nakamoto discloses the claimed invention as set forth in claim 1.
Nakamoto does not explicitly disclose the conductor layer has a thickness of 15 µm or less.
Nakamoto suggests the size of the conductor in the range of 3 µm or less (paragraph 41).
It would have been obvious to one having skill in the art at the effective filing date of the invention to adjust the size of the conductor in order to fit all the conductors in the limited space of the circuit substrate.
Regarding claim 3, Nakamoto discloses the claimed invention as set forth in claim 1.
Nakamoto does not explicitly disclose the conductor layer is formed such that the lower layer has a thickness of 0.3 pm or less.
Nakamoto suggests the size of the conductor in the range of 3 µm or less (paragraph 41).
It would have been obvious to one having skill in the art at the effective filing date of the invention to adjust the size of the conductor in order to fit all the conductors in the limited space of the circuit substrate.
Regarding claim 4, Nakamoto discloses the claimed invention as set forth in claim 1. Nakamoto further suggests the conductor layer is formed such that the lower layer is a sputtering film (paragraph 26).
Regarding claim 5, Nakamoto discloses the claimed invention as set forth in claim 4. Nakamoto further suggests the conductor layer is formed such that the sputtering film includes a lower film comprising a copper alloy (paragraph 26) formed on the surface of the insulating layer, and an upper film comprising copper (paragraph 26) formed on the lower film.
Regarding claim 7, Sakamoto discloses the claimed invention as set forth in claim 1. Sakamoto further suggests a via conductor (109, 112) integrally formed with the conductor layer (101) such that the via conductor is penetrating through the insulating layer (120) and connecting a conductor (134) on the insulating layer on an opposite side with respect to the conductor layer and has an aspect ratio in a range of 0.5 to 1.0 (the aspect ratio of 112 appears to be around 1).
Regarding claim 8, Sakamoto discloses the claimed invention as set forth in claim 1. Sakamoto further suggests the conductor layer is formed such that the lower layer (101a) has an etched surface (side surface of 101a exposed) exposed on a side surface of each of the wiring patterns.
Regarding claim 9, Sakamoto discloses the claimed invention as set forth in claim 1.
Sakamoto does not explicitly disclose the conductor layer is formed such that the polished surface has an arithmetic mean roughness of 0.3 m or less.
Sakamoto suggests the conductor surface is roughened (claim 3 and paragraph 44).
It would have been obvious to one having skill in the art at the effective filing date of the invention to roughened the surface of the conductor in order to enhance the adhesion of the surfaces (paragraph 44).
Regarding claim 10, Nakamoto discloses the claimed invention as set forth in claim 2.
Nakamoto does not explicitly disclose the conductor layer is formed such that the lower layer has a thickness of 0.3 µm or less.
Nakamoto suggests the size of the conductor in the range of 3 µm or less (paragraph 41).
It would have been obvious to one having skill in the art at the effective filing date of the invention to adjust the size of the conductor in order to fit all the conductors in the limited space of the circuit substrate.
Regarding claim 11, Nakamoto discloses the claimed invention as set forth in claim 1. Nakamoto suggests the conductor layer has a polished surface on an opposite side with respect to the insulating layer (the surface of the conductor is roughened; paragraph 44 and claim 3).
Regarding claim 12, Nakamoto discloses the claimed invention as set forth in claim 2. Nakamoto further suggests the conductor layer is formed such that the lower layer is a sputtering film (paragraph 26).
Regarding claim 13, Nakamoto discloses the claimed invention as set forth in claim 12. Nakamoto further suggests the conductor layer is formed such that the sputtering film includes a lower film comprising a copper alloy (paragraph 26) formed on the surface of the insulating layer, and an upper film comprising copper (paragraph 26) formed on the lower film.
Regarding claim 15, Sakamoto discloses the claimed invention as set forth in claim 2. Sakamoto further suggests a via conductor (109, 112) integrally formed with the conductor layer (101) such that the via conductor is penetrating through the insulating layer (120) and connecting a conductor (134) on the insulating layer on an opposite side with respect to the conductor layer and has an aspect ratio in a range of 0.5 to 1.0 (the aspect ratio of 112 appears to be around 1).
Regarding claim 16, Sakamoto discloses the claimed invention as set forth in claim 2. Sakamoto further suggests the conductor layer is formed such that the lower layer (101a) has an etched surface (side surface of 101a exposed) exposed on a side surface of each of the wiring patterns.
Allowable Subject Matter
Claims 6, 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 6, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1, 4, and 5, a combination of limitations that the conductor layer is formed such that a width of the lower film is smaller than a width of the upper layer and larger than a width of the upper film. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 14, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1, 2, 12, 13, a combination of limitations that the conductor layer is formed such that a width of the lower film is smaller than a width of the upper layer and larger than a width of the upper film. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sakamoto (US 20160105960) discloses a substrate with via holes, Fig. 1.
Sakamoto (US 20160066423) discloses a substrate with via holes, Fig. 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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