Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 12/19/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 8-10, are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20210305809 A1) in view of Wu et al. (US 20220415878 A1).
Regarding claim 1, Hung et al disclose a semiconductor diode structure (500A), comprising:
a silicon remaining layer (521);
a first p-type doping region (504a) disposed on the silicon remaining layer;
a first n-type (504c) doping region disposed on the silicon remaining layer;
and a first channel region (505) disposed on the silicon remaining layer (521) and between the first p-type doping region and the first n-type doping region, wherein the first channel region, the first p-type doping region, and the first n-type doping region are disposed along a first direction (Fig. 5A).
Hung et al. do not disclose the silicon remaining layer has a thickness of 10nm-100nm in a second direction that crosses the first direction.
However, Wu et al. disclose the silicon substrate is between 20 nm and 30 nm (paragraph 56, Fig. 2, in the horizontal direction or second direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung et al. according to Wu et al. such that the silicon layer in the first direction is between 10nm and 100nm. Doing so would decrease resistance, power loss, and device size.
Regarding claim 2, Hung et al. disclose the first channel region includes:
a first stack of silicon nanosheets (505, paragraph 213) disposed on the silicon remaining layer (521) and between the first p-type doping region and the first n-type doping region, wherein the first stack of silicon nanosheets, the first p-type doping region, and the first n-type doping region are disposed along the first direction (Fig. 5A);
and a first metal gate (504b) wrapping around each of the silicon nanosheets of the first stack of silicon nanosheets (Fig. 5A).
Regarding claim 8, Hung et al. disclose a second p-type doping region (530c) disposed on the silicon remaining layer (521); a second n-type doping region (530a) disposed on the silicon remaining layer; a second stack of silicon nanosheets (532) disposed on the silicon remaining layer and between the second n-type doping region and the second p-type doping region; and a second metal gate (530b) wrapping around each of the silicon nanosheets of the second stack of silicon nanosheets (Fig. 5A).
Regarding claim 9, Hung et al. disclose a third stack of a third stack of silicon nanosheets (512) disposed on the silicon remaining layer (521) and between the first n-type doping region (510a) and the second n-type doping region (510c); and a third metal gate (510b) wrapping around each of the silicon nanosheets of the third stack of silicon nanosheets (Fig. 5A).
Regarding claim 10, Hung et al disclose wherein the first p-type doping region, the first n-type doping region and the first channel region are disposed on a front side of the silicon remaining layer (520, Fig. 5A), and a back side interconnect structure disposed on a back side of the silicon remaining layer opposite the front side (544, Fig. 5A).
Claims 3, 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20210305809 A1) in view of Wu et al. (US 20220415878 A1) as applied to claims 1-2 and 8-10 above, in further view of Thomson et al. (US 20220416022 A1).
Regarding claim 3, Hung et al. disclose the semiconductor diode structure of claim 2, further comprising:
a second p-type doping region (530C) disposed on the silicon remaining layer (521);
a second n-type doping region (530A) disposed on the silicon remaining layer;
a second stack of silicon nanosheets (532) disposed on the silicon remaining layer and between the first p-type doping region and the second p-type doping region (Fig. 5A);
a second metal gate (530b) wrapping around each of the silicon nanosheets of the second stack of silicon nanosheets; a third stack of silicon nanosheets (512)
However, Hung et al. do not disclose nanosheets disposed on the silicon remaining layer and between the first n-type doping region and the second n-type doping region; and a third metal gate wrapped around each of the silicon nanosheets of the third stack of silicon nanosheets.
On the other hand, Thomson et al. disclose nanowires (208D) disposed on the silicon layer between the first n-type doping region (218D) and the second n-type doping region (218D, Fig. 2D) and a third metal gate (212D) wrapping around each of the silicon nanowires of the third stack of silicon nanowires (Fig. 2D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung et al. with Thomson et al. such that the semiconductor diode structure has a metal gate and nanosheets between the first and second n-type doped regions. Doing so would enable better gate control, higher drive current, and compact size.
Regarding claim 5, Hung et al. disclose a first undoped region (570b) disposed on the silicon remaining layer (Fig. 5A), wherein the first stack of silicon nanosheets (505) is disposed between the first undoped region and the first p- type doping region; a second undoped region (570c) disposed on the silicon remaining layer (Fig. 5A).
Hung et al. and Wu et al. do not disclose a fourth stack of silicon nanosheets; a fourth metal gate wrapping around each of the silicon nanosheets of the fourth stack of silicon nanosheets; a fifth stack of silicon nanosheets disposed on the silicon remaining layer and between the second undoped region and the first n-type doping region; and a fifth metal gate wrapping around each of the silicon nanosheets of the fifth stack of silicon nanosheets.
Thomson et al. discloses a fourth stack of silicon nanosheets (Fig. 2D); a fourth metal gate (212D) wrapping around each of the silicon nanosheets (208D) of the fourth stack of silicon nanosheets (Fig. 2D); a fifth stack of silicon nanosheets disposed on the silicon remaining layer and between the second undoped region (Hung, 570C) and the first n-type doping region (Fig. 2D); and a fifth metal gate wrapping around each of the silicon nanosheets of the fifth stack of silicon nanosheets (Fig. 2D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung et al. with Thomson et al. such that the plurality or nanosheets, gate structures, p-type, n-type, and undoped regions are described in the claims. Doing so would enable abrupt, high-quality P-N junctions, and precise junction formation.
Regarding claim 6, Hung et al. disclose the first undoped region (570B) and the second undoped region (570C) are shallow trench isolation structures (paragraph 187).
Regarding claim 7, Hung et al. does not disclose the first metal gate, the fourth metal gate and the fifth metal gate are electrically connected.
However, Thomson et al. disclose a first metal gate, fourth metal gate, and fifth metal gate (plurality of 212D, Fig 2D) are electrically connected by p-doped silicon nanowires (208E, paragraph 40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung et al. according to Thomson et al. such that the first, fourth, and fifth metal gates are electrically connected. Doing so would enable adjustable conductivity.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20210305809 A1) in view of Wu et al. (US 20220415878 A1) and Thomson et al. (US 20220416022 A1) as applied to claim 3 above, and further in view of Yeh et al. (US 11626719 B2) and Kumar et al. (US 20170025411 A1).
Regarding claim 4, Hung et al. disclose a first anode terminal (504a) connected to the first p-type doping region (Fig. 5A);
Hung does not disclose a second anode terminal connected to the second p-type doping region, wherein the first and second anode terminals are electrically connected; a first cathode terminal connected to the first n-type doping region; and a second cathode terminal connected to the second n-type doping region, wherein the first and second cathode terminals are electrically connected.
However, Yeh et al. disclose a first cathode terminal (302c) connected to the first n-type doping region; and a second cathode terminal connected to the second n-type doping region (302d), wherein the first and second cathode terminals are electrically connected (390, Fig. 3b).
Kumar discloses a second anode doped region (230), electrically connected to the first anode doped region (216) (paragraph 39, Fig.1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the prior references according to Yeh et al. and Kumar et al. such that the cathode terminals are connected to the n-type doping regions, and the second anode terminal is connected to the first anode terminal. Doing so would enable electrons to flow towards the junction of the semiconductor diode device.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817