Prosecution Insights
Last updated: May 29, 2026
Application No. 18/365,594

METHODS OF CHARGING LOCAL INPUT/OUTPUT LINES OF MEMORY DEVICES, AND RELATED DEVICES AND SYSTEMS

Non-Final OA §102§DOUBLEPATENT§DP
Filed
Aug 04, 2023
Priority
Apr 24, 2020 — divisional of 11/538,510 +1 more
Examiner
LAPPAS, JASON
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lodestar Licensing Group LLC
OA Round
2 (Non-Final)
91%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
382 granted / 420 resolved
+23.0% vs TC avg
Moderate +8% lift
Without
With
+8.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
17 currently pending
Career history
434
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
39.4%
-0.6% vs TC avg
§102
56.7%
+16.7% vs TC avg
§112
1.0%
-39.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 420 resolved cases

Office Action

§102 §DOUBLEPATENT §DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Response to Amendment Applicant’s amendment dated 12/24/2025 in which no claims were amended has been entered of record. Currently, claims 1-20 are pending in light of the amendment. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-6 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9-14 of U.S. Patent No. 11,538,510. Although the claims at issue are not identical, they are not patentably distinct from each other because the applicant’s claim is broader and includes within its scope the subject matter of the allowed claim, the claims are not patentably distinct as the applicants claim represents an obvious variation of the allowed claim. Claims 7-13 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16 and 18 of U.S. Patent No. 11,538,510. Although the claims at issue are not identical, they are not patentably distinct from each other because the applicant’s claim is broader and includes within its scope the subject matter of the allowed claim, the claims are not patentably distinct as the applicants claim represents an obvious variation of the allowed claim. Claims 14-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 19 and 20 of U.S. Patent No. 11,538,510. Although the claims at issue are not identical, they are not patentably distinct from each other because the applicant’s claim is broader and includes within its scope the subject matter of the allowed claim, the claims are not patentably distinct as the applicants claim represents an obvious variation of the allowed claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 6, 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hanzawa (Patent Application Publication 2009/0116309). Claim 1. A method of operating a memory device (DDR SDRAM, Hanzawa Fig 1), comprising: performing, responsive to a read command (Responsive to a read command R0, Fig 11), a read operation via a local input/output (LIO) line of the memory device (selecting data via YS and reading it to local input output lines LIO0T and LIO0B, Hanzawa [0082-0087, 0095-0100], Fig 10-11); and receiving an additional command (R1, Fig 11) without precharging the LIO line after performing the read operation and prior to receiving the additional command (R0 followed by R1 as seen in Fig 11. LIOPCC1 precharge is stopped after activation Fig 10. LIO lines go back to ref voltage when PR is received. Precharge PR is after R1, therefore received an additional command R1 without precharge). Claim 6. The method of claim 1, wherein receiving the additional command without precharging the LIO line comprises receiving the additional command without performing an LIO precharge operation after performing the read operation and prior to receiving the additional command (R1 is after R0. First read responsive to R0 followed by second burst read responsive to R1 [0095-0100, 0107-0109] Fig 11 and 14). Claim 7. A memory device, comprising: a local input/output (LIO) line (LIO0T and LIO0B, Hawanza Fig 10-11); and circuitry configured to (configured to is functional language): perform, via the LIO line, a read operation responsive to a read command (sense amp Fig 10 is configured to perform a read responsive to a read command via LIO0T or LIO0B, Fig 10); and receive an additional command without precharging the LIO line after performance of the read operation and prior to receipt of the additional command (R0 then R1 then PR. LIOPCC1 precharge is stopped during a read and LIO lines are driven to reference voltage when PR is received, [0097-0101, 0107-0110] Fig 11-14). Claim 8. The memory device of claim 7, wherein the circuitry is such that during a duration of time after the performance of the read operation and prior to the receipt of the additional command, the LIO line retains a charge based on a charge of a digit line, the digit line coupled to a memory cell of the memory device (After R0, LIO carries read data and at R1 data on the LIO is amplified and read to the MIO line as seen in Fig 11). Response to Arguments Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection. Applicant’s arguments, filed 12/24/2025, with respect to the rejection(s) of claim(s) s 1-20 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lan U.S. Patent Application 11,538,510. Claims 1-20 are rejected in the nonstatutory double patenting rejection above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON LAPPAS/ Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Aug 04, 2023
Application Filed
Aug 26, 2025
Non-Final Rejection mailed — §102, §DOUBLEPATENT, §DP
Dec 24, 2025
Response Filed
May 06, 2026
Non-Final Rejection mailed — §102, §DOUBLEPATENT, §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12640188
CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICES
1y 10m to grant Granted May 26, 2026
Patent 12641786
MEMORY DEVICE AND METHOD FOR CONTROLLING VERIFICATION VOLTAGE OF MEMORY DEVICE
1y 8m to grant Granted May 26, 2026
Patent 12626752
SENSE AMPLIFIER AND METHOD OF OPERATION THEREOF
1y 7m to grant Granted May 12, 2026
Patent 12620441
MEMORY, OPERATION METHOD OF MEMORY, AND MEMORY SYSTEM
1y 10m to grant Granted May 05, 2026
Patent 12620442
MANAGING PROGRAM DISTURB IN MEMORY DEVICES
1y 9m to grant Granted May 05, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+8.1%)
2y 0m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 420 resolved cases by this examiner. Grant probability derived from career allowance rate.

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