DETAILED ACTION
Allowable Subject Matter
Claims 7-8 & 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Claim 7 recites the details of forming of “conducting metal layer” and the “plug structure”. These details are not found in the prior art.
Claim 8 recites the details of forming of “buffer dielectric layer” and the “plug structure”. These details are not found in the prior art.
Claims 18-19 contain similar limitations and are indicated as allowable subject matter for similar reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over (CN-10-4637968) by Zhao et al (“Zhao”; part of Applicant’s IDS).
Regarding claim 1, Zhao discloses in FIG. 13 and related text, e.g., a method of fabricating a semiconductor device, the method comprising:
providing a substrate (100) defining a pixel area (directly under 115);
forming a trench fill structure (109/110) in the substrate in the pixel area;
covering a buffer dielectric layer (113; anti-reflective layer is a dielectric; and it is a buffer between layers above and below) over a surface of the substrate in the pixel area, the buffer dielectric layer burying the trench fill structure (compare FIGs. 12 & 13; also, see par. 47; 113 is deposited after 109/110; hence, “burying”);
form a first opening (has 114 in it), which exposes at least a portion of the substrate surrounding sidewalls of a top of the trench fill structure (see FIG. 13) and/or at least a portion of the top of the trench fill structure (see FIG. 13); and
forming a metal grid layer (114) on the buffer dielectric layer, wherein the metal grid layer fills the first opening (see FIG. 13) and is electrically connected to the exposed portion of the substrate and/or the exposed portion of the trench fill structure (see FIG. 13; there is direct contact between 114 and substrate 100; hence, “electrically connect”, since one is metal and the other is semiconductor).
Zhao does not explicitly state “etching the buffer dielectric layer to form a first opening”.
Zhao is silent as to how the opening in “buffer dielectric layer” is formed. The opening is formed, and present in FIG. 13. However, how it is formed is not explicitly stated in disclosure.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of making of Zhao with “etching the buffer dielectric layer to form a first opening”, since Zhao teaches etching of various layers throughout his reference (pars. 13, 37, etc.; the word “etch” appears in the reference at least 26 times), and therefore using an “etching” process for “buffer dielectric layer” specifically, would have been obvious to a POSITA, in light of Zhao’s explicit teachings related thereto throughout the reference.
Regarding claim 2, Zhao discloses in FIG. 13 and related text, e.g., wherein forming a trench fill structure in the substrate in the pixel area comprises:
covering a pad oxide layer (FIG. 3, 106) over the surface of the substrate in the pixel area;
forming a first patterned photoresist layer on the pad oxide layer (par. 40; “photoresist layer” is present, just not shown) and etching the pad oxide layer and at least a partial thickness of the substrate with the first patterned photoresist layer serving as a mask (“mask” is the definition of normal use for photoresist; see par. 40 and FIG. 4), thereby forming a trench in the substrate in the pixel area (see FIG. 4);
removing the first patterned photoresist layer (see par. 40);
forming an isolation oxide layer (FIG. 5, 109; see par. 41) over a surface of the trench and a surface of the pad oxide layer; completely filling the trench with a filler material (110; see FIG. 5), which also covers the isolation oxide layer outside the trench (see FIG. 5); and
removing a portion of the filler material, the isolation oxide layer and the pad oxide layer on the surface of the substrate outside the trench by performing an etching or chemical mechanical polishing (CMP) process, thereby forming the trench fill structure in the trench (see par. 41 and FIG. 6).
Regarding claim 3, Zhao discloses in FIG. 13 and related text, e.g., wherein the filler material comprises a first conductive metal layer (110; par. 41), and wherein the first opening exposing at least a portion of a top of the trench fill structure comprises:
the first opening surrounding sidewalls of the top of the trench fill structure and exposing the first conductive metal layer on the sidewalls of the top of the trench fill structure in the first opening (see FIG. 13); and/or, the first opening being located on a top surface of the trench fill structure and exposing an entire or a portion of a top surface of the first conductive metal layer of the trench fill structure in the first opening (see FIG. 13).
Regarding claim 4, Zhao discloses in FIG. 13 and related text, e.g., discloses substantially the entirety of claimed subject matter, including “wherein etching the buffer dielectric layer to form a first opening comprises: etching the buffer dielectric layer (see claim 1), thereby forming the first opening in the buffer dielectric layer above the pixel area, the first opening exposing at least a portion of the substrate surrounding the sidewalls of the top of the trench fill structure and/or at least a portion of the top of the trench fill structure; and removing the second patterned photoresist layer (as was described in claims above).
Zhao does not explicitly state “forming a second patterned photoresist layer on the buffer dielectric layer and etching the buffer dielectric layer with the second patterned photoresist layer serving as a mask”.
More specifically, Zhao shows the result, a buffer dielectric layer with an opening in it. He does not explicitly state “second photoresist layer” and etching it with photoresist layer being used as a “mask”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of making of Zhao with “forming a second patterned photoresist layer on the buffer dielectric layer and etching the buffer dielectric layer with the second patterned photoresist layer serving as a mask”, since Zhao teaches a presence of opening (FIG. 13), teaches use of photoresist layer (in pars. 40, 52, 58) and therefore use of “second patterned photoresist layer” as a “mask” would be obvious to a POSITA, in light of Zhao’s explicit teachings for other layers in the same reference.
Regarding claim 5, Zhao discloses in FIG. 13 and related text, e.g., wherein forming the metal grid layer on the buffer dielectric layer comprises:
forming a second conductive metal layer (114) to cover the buffer dielectric layer, the second conductive metal layer completely filling the first opening (see FIG. 13);
forming the metal grid layer above the pixel area (114; pars. 47-48), the metal grid layer electrically connected to the portion of the substrate and/or the portion of the trench fill structure exposed in the first opening (see FIG. 13 and par. 48).
Zhao does not explicitly state “forming a third patterned photoresist layer on the second conductive metal layer and etching the second conductive metal layer with the third patterned photoresist layer serving as a mask, thereby forming the metal grid layer; and removing the third patterned photoresist layer”.
More specifically, Zhao shows the result, a metal grid layer. He does not explicitly state “third photoresist layer” and etching second conductive metal layer with photoresist layer being used as a “mask”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of making of Zhao with “forming a third patterned photoresist layer on the second conductive metal layer and etching the second conductive metal layer with the third patterned photoresist layer serving as a mask, thereby forming the metal grid layer; and removing the third patterned photoresist layer”, since Zhao teaches a presence of metal grid layer (FIG. 13), teaches use of photoresist layer (in pars. 40, 52, 58) and therefore use of “third patterned photoresist layer” as a “mask” would be obvious to a POSITA, in light of Zhao’s explicit teachings for other layers in the same reference.
Regarding claim 9, Zhao discloses in FIG. 13 and related text, e.g., wherein the metal grid layer is in electrical connected to the exposed portion of the substrate to apply a bias voltage to a backside of the substrate (par. 48).
Regarding claim 10, Zhao discloses in FIG. 13 and related text, e.g., a method of fabricating a semiconductor device, the method comprising:
providing a substrate defining a pixel area (see claim 1);
forming a trench fill structure in the substrate in the pixel area (see claim 1);
covering a buffer dielectric layer over a surface of the substrate in the pixel area, the buffer dielectric layer burying the trench fill structure (see claim 1);
etching the buffer dielectric layer to form a first opening, which at least exposes a portion of the substrate surrounding the trench fill structure (see claim 1); and
forming a metal grid layer on the buffer dielectric layer (see claim 1), wherein the metal grid layer fills the first opening to at least directly contact with and electrically connect to the exposed portion of the substrate (see FIG. 13 and par. 48).
Regarding claim 11, Zhao discloses in FIG. 13 and related text, e.g., wherein the formation of the first opening comprises:
forming a second patterned photoresist layer on the buffer dielectric layer (see claim 4); and
etching the buffer dielectric layer with the second patterned photoresist layer serving as a mask so that the first opening is formed in the buffer dielectric layer above the pixel area (see claim 4), both a portion of the substrate surrounding a top edge of the trench fill structure and an entire top surface of the trench fill structure are exposed in the first opening (see FIG. 13).
Regarding claim 12, Zhao discloses in FIG. 13 and related text, e.g., wherein the formation of the first opening comprises:
forming a second patterned photoresist layer on the buffer dielectric layer (see claim 4); and
etching the buffer dielectric layer with the second patterned photoresist layer serving as a mask so that the first opening is formed in the buffer dielectric layer above the pixel area (see claim 4), part of the top surface of the trench fill structure is exposed in the first opening (see FIG. 13).
Regarding claim 13, Zhao discloses in FIG. 13 and related text, e.g., wherein the formation of the first opening comprises:
forming a second patterned photoresist layer on the buffer dielectric layer (see claim 4); and
etching the buffer dielectric layer with the second patterned photoresist layer serving as a mask so that the first opening is formed in the buffer dielectric layer above the pixel area (see claim 4), only a portion of the substrate surrounding a top edge of the trench fill structure is exposed in the first opening (see FIG. 13; only a portion of the substrate is exposed; entire substrate is not exposed; thus, meeting limitations).
Regarding claim 14, Zhao discloses in FIG. 13 and related text, e.g., wherein the metal grid layer is in direct contact with and electrically connected to the exposed portion of the substrate to apply a bias voltage to a backside of the substrate (see FIG. 13 and par. 48).
Regarding claim 15, Zhao discloses in FIG. 13 and related text, e.g., wherein forming a trench fill structure in the substrate in the pixel area comprises:
covering a pad oxide layer over the surface of the substrate in the pixel area (see claim 2);
forming a first patterned photoresist layer on the pad oxide layer and etching the pad oxide layer and at least a partial thickness of the substrate with the first patterned photoresist layer serving as a mask (see claim 2), thereby forming a trench in the substrate in the pixel area (see claim 2);
removing the first patterned photoresist layer (see claim 2);
forming an isolation oxide layer over a surface of the trench and a surface of the pad oxide layer (see claim 2);
completely filling the trench with a filler material, which also covers the isolation oxide layer outside the trench (see claim 2); and
removing a portion of the filler material, the isolation oxide layer and the pad oxide layer on the surface of the substrate outside the trench by performing an etching or chemical mechanical polishing (CMP) process, thereby forming the trench fill structure in the trench (see claim 2).
Regarding claim 16, Zhao discloses in FIG. 13 and related text, e.g., wherein forming the metal grid layer on the buffer dielectric layer comprises:
forming a second conductive metal layer to cover the buffer dielectric layer, the second conductive metal layer completely filling the first opening (see claim 5);
forming a third patterned photoresist layer on the second conductive metal layer and etching the second conductive metal layer with the third patterned photoresist layer serving as a mask (see claim 5), thereby forming the metal grid layer above the pixel area (see claim 5), the metal grid layer at least being directly contact with and electrically connect to the exposed portion of the substrate (see claim 5, FIG. 13, and par. 48); and
removing the third patterned photoresist layer (see claim 5).
Claims 6 & 17 are rejected under 35 U.S.C. 103 as being unpatentable over (CN-10-4637968) by Zhao et al (“Zhao”) in view of (US-2021/0066225) by Chou et al (“Chou”).
Regarding claim 6, Zhao discloses in FIG. 13 and related text, e.g., substantially the entire claim structure, as recited in above claims, except wherein the substrate further defines a pad area lateral to the pixel area, and wherein a metal interconnect structure and a plug structure above the metal interconnect structure are formed in the substrate in the pad area, the plug structure electrically connected at a bottom thereof to the metal interconnect structure.
Zhao is silent about pad area and related limitations. However, Chou fixes the deficiency.
Chou discloses in FIG. 5 and related text, e.g., wherein the substrate further defines a pad area (FIG. 5) lateral to the pixel area (see FIG. 3; pixel area is shown to the side of pad area), and wherein a metal interconnect structure (108a/108, etc.) and a plug structure (contains 116) above the metal interconnect structure are formed in the substrate in the pad area, the plug structure electrically connected at a bottom thereof to the metal interconnect structure (see FIG. 5; direct physical/electrical connection between the two).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Zhao with “wherein the substrate further defines a pad area lateral to the pixel area, and wherein a metal interconnect structure and a plug structure above the metal interconnect structure are formed in the substrate in the pad area, the plug structure electrically connected at a bottom thereof to the metal interconnect structure”, as taught by Chou, since applying a known technique (technique of Chou exactly how to form bondpads) to a known device ready for improvement (device of Zhao, which does not teach how to form pads; and thus would benefit from having a teaching on how to form outside connections for the chip) to yield predictable results (results are predictable, because both references deal with back side illuminated imagers; results are also predictable because Zhao already has “trenches” with “insulator” and “conductive layer” inside it, between pixels; Chou teaches a similar structure (“trenches” with “insulator” and “conductive layer” inside it) for the pad area; hence, results are predictable) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Regarding claim 17, the combined method of making of Zhao and Chou disclose in cited figures and related text, e.g., wherein the substrate further defines a pad area lateral to the pixel area, and wherein a metal interconnect structure and a plug structure above the metal interconnect structure are formed in the substrate in the pad area, the plug structure electrically connected at a bottom thereof to the metal interconnect structure.
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
01/24/26
/Mounir S Amer/Primary Examiner, Art Unit 2818