DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 2. Claims 2 and 10 are objected to because of the following informalities: 3. Claim 2 recites “solder balls electrically balls each electrically coupled” which should be changed to “solder balls each electrically coupled” 4. Claim 10 recites “the contact pads” which should be changed to “the third contact pads” Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 5. Claim 1-8 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over ee et al. (US 2022/0068853 A1), hereinafter as L1, in view of Lin et al. (US 2010/0246152 A1), hereinafter as L2 6. Regarding Claim 1 , L1 discloses a device (see Figs. 1-14, in particular “Labeled Fig. 2” above, and [0011] “semiconductor device”) , comprising: an integrated circuit die (element 20, see [0025] “semiconductor die 20”) including: core circuitry (see Fig. 1 element 21 and [0031] “The one or more integrated devices may correspond to the integrated device 21 discussed with reference to FIG. 1. The one or more integrated devices may include a memory circuit, a logic circuit, an electrostatic discharge (ESD) protection circuit, or a combination thereof”) implemented in one or more layers of semiconductor material (element 100, see [0031] “semiconductor substrate 100” and Fig. 3 having transistor elements TR) ; a first cluster (labeled element “First Cluster” of elements DP1, see [0029] “first die pads DP1”) of first contact pads (elements DP1 of labeled element “First Cluster”) formed of a top metal layer (see Fig. 3 conductive material layer on element 120, and [0051] “the conductive material may include copper (Cu) or tungsten (W)”) of the integrated circuit die and coupled to the core circuitry (see Fig. 3 and [0043] “The first die pads DP1 may be connected through the first, second, third, fourth, and fifth redistribution layers 112, 114, 116, 118, and 120 to the integrated devices of the semiconductor substrate 100”) ; a second cluster (labeled element “Second Cluster” of elements DP1) of second contact pads formed of the top metal layer and coupled to the core circuitry (same as the elements DP1 of the labeled element “First Cluster” but in a different location) ; a first ESD protection line (element L1 between labeled element “First Cluster” and “Second Cluster” and see [0043] “an electrostatic discharge (ESD) protection circuit may be constituted by the transistors TR connected to the first die pads DP1 … the first die pads DP1 may be connected through the second wiring line L2” and [0048] “the first die pads DP1 may be coupled through the first wiring lines L1 to the grouping pattern GP”) formed of the top metal layer extending between an area of the first cluster and an area of the second cluster (see “Labeled Fig. 2” above and Fig. 3) ; and ESD protection circuitry in the one or more layers of semiconductor material coupling each of the first contact pads and each of the second contact pads to the first ESD protection line by ESD protection circuitry (see [0043] “an electrostatic discharge (ESD) protection circuit may be constituted by the transistors TR connected to the first die pads DP1”) . L1 does not explicitly disclose a passivation layer on the integrated circuit die; and a second ESD protection line on the passivation layer formed of a redistribution metal layer and shorting a portion of the first ESD protection line. L2 discloses (see Fig. 10) a passivation layer (element 5, see [0351] “passivation layer 5”) on the integrated circuit die (elements below element 5 and see [0290] “semiconductor chip”) ; and a second ESD protection line (element 831, see [0290] “course metal traces 83, 831, 832, and 83r over the passivation layer 5”) on the passivation layer formed of a redistribution metal layer and shorting a portion of the first ESD protection line (see Fig. 10A on the first ESD protection line element 638 in direct contact with element 831 and see [0293] “ESD circuit 43” connected to element 638, 831 through element 6391 and 69) . The passivation layer and second ESD protection line as taught by L2 is incorporated as a passivation layer and second ESD protection line of L1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L2 with L1 because the combination allows for thicker conductor connection to the top of the chip to communicate with an external circuit (see L2 [0292-0293]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known external connection wiring for another in a similar device for another to obtain predictable results (see L2 Fig. 10A). 7. Regarding Claim 2 , L1, L2 disclose the device of claim 1, comprising solder balls electrically balls each electrically coupled to one of the first contact pads or the second contact pads (see L1 Figs. 2-3 elements 130, see [0042] “connection terminals 130 may include a micro-bump”) . 8. Regarding Claim 3 , L1, L2 disclose the device of claim 1, comprising a third ESD protection line (see L1 “Labeled Fig. 2” above, the combined third ESD protection line over element L1 between labeled element “Third Cluster” and element GP) formed of the redistribution metal layer (same material as the second ESD protection line, see L2 [0290]) , wherein the integrated circuit die includes: a third cluster (see L1 “Labeled Fig. 2” above, labeled element “Third Cluster”) of third contact pads (third elements DP1) formed of the top metal layer (see L1 Figs. 2-3) ; and an ESD connection line (element L1 between element “Third Cluster” and element GP) formed of the top metal layer and electrically coupling the third ESD protection line to the second ESD protection line (see Figs. 2-3 and “Labeled Fig. 2” above) , wherein the third ESD protection line is coupled to each of the third contact pads by the ESD protection circuitry (see each of the elements DP1 of labeled element “Third Cluster” connected through element GP and L1 [0049] “the grouping pattern GP may mutually connect ground circuits or electrostatic discharge (ESD) protection circuits of the integrated devices formed on the semiconductor substrate 100 and may supply uniform ground voltages to the ground circuits or the ESD protection circuits”) . 9. Regarding Claim 4 , L1, L2 disclose the device of claim 1. L1, L2 as previously combined does not disclose wherein the ESD protection circuitry includes diodes . L2 further discloses wherein the ESD protection circuitry includes diodes (see [0294]) . The type of ESD protection circuitry as taught by L2 is incorporated as the type of ESD protection circuitry of L1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L2 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known specific ESD protection circuitry for another in a similar device to obtain predictable results (see L2 [0294]). 10. Regarding Claim 5 , L1, L2 disclose the device of claim 1, wherein the first ESD protection line is coupled to ground (see L1 [0049] “the grouping pattern GP may mutually connect ground circuits or electrostatic discharge (ESD) protection circuits of the integrated devices formed on the semiconductor substrate 100 and may supply uniform ground voltages to the ground circuits or the ESD protection circuits”) . 11. Regarding Claim 6 , L1, L2 disclose the device of claim 1, wherein the second ESD protection line is coupled to the first ESD protection line at a first location by a first opening in the passivation layer and at a second location via a second opening in the passivation layer (see in particular L2 Fig. 10H plurality of openings for element 831 to connect through passivation layer element 5 to the first ESD protection line as combined in L1 – see “Labeled Fig. 2” above a second opening would be electrically coupled; note, the manner in which the claim is currently recited does not require physical coupling) . 12. Regarding Claim 7 , L1, L2 disclose the device of claim 1, wherein the second ESD protection line has lower resistance between the first cluster and the second cluster than does the first ESD protection line (see L2 the first ESD protection line element 6390 material [0219] “contact pads 6390, principally made of aluminum or copper” selected as aluminum, and see [0188] “the seed layer may be formed by a suitable process or processes, e.g., by sputtering a copper layer … Thereafter, the metal layer 8112 may be formed by a suitable process or processes, e.g., by electroplating a copper layer”) . 13. Regarding Claim 8 , L1, L2 disclose the device of claim 1, wherein the top metal layer includes aluminum (see L2 the first ESD protection line element 6390 material [0219] “contact pads 6390, principally made of aluminum or copper” selected as aluminum) and the redistribution metal layer includes copper (see L2 [0188] “the seed layer may be formed by a suitable process or processes, e.g., by sputtering a copper layer … Thereafter, the metal layer 8112 may be formed by a suitable process or processes, e.g., by electroplating a copper layer”) . 14. Regarding Claim 11 , L1, L2 disclose the device of claim 1, wherein the core circuitry includes transistors (see L1 elements TR) . 15. Regarding Claim 12 , L1 discloses a method (see Figs. 1-14, in particular “Labeled Fig. 2” above, and [0011] “semiconductor device”) , comprising: forming a plurality of metal layers (see Fig. 3 metal layers above element 112, see [0038] “CP1 to CP4 may include metal” and [0051] “the conductive material may include copper (Cu) or tungsten (W)”) of an integrated circuit die (element 20, see [0025] “semiconductor die 20”) above a semiconductor substrate (element 100, see [0031] “semiconductor substrate 100”) of the integrated circuit die, the plurality of layers including a top metal layer (top metal layer above element 120, see [0051] “the conductive material may include copper (Cu) or tungsten (W)”) ; forming, from the top metal layer, a first cluster (labeled element “First Cluster” of elements DP1, see [0029] “first die pads DP1”) of first contact pads (labeled element “First Cluster” of elements DP1, see [0029] “first die pads DP1”) , a second cluster (labeled element “Second Cluster” of elements DP1) of second contact pads (same as the elements DP1 of the labeled element “First Cluster” but in a different location) , and a first ESD protection line (element L1 between labeled element “First Cluster” and “Second Cluster” and see [0043] “an electrostatic discharge (ESD) protection circuit may be constituted by the transistors TR connected to the first die pads DP1 … the first die pads DP1 may be connected through the second wiring line L2” and [0048] “the first die pads DP1 may be coupled through the first wiring lines L1 to the grouping pattern GP”) coupled to each of the first and second contact pads via ESD protection circuitry (see [0043] “an electrostatic discharge (ESD) protection circuit may be constituted by the transistors TR connected to the first die pads DP1”). L1 does not explicitly disclose forming a passivation layer on the first ESD protection line; and forming, from a redistribution metal layer on the passivation layer, a second ESD protection line electrically coupled to the first ESD protection line via a first opening in the passivation layer adjacent to the first cluster and via a second opening in the passivation layer adjacent to the second cluster. L2 discloses (see Fig. 10) forming a passivation layer (element 5, see [0351] “passivation layer 5”) on the first ESD protection line (element 638 which is in direct contact with element 831, see [0293] “ESD circuit 43”) ; and forming, from a redistribution metal layer (element 831, see [0290] “course metal traces 83, 831, 832, and 83r over the passivation layer 5”) on the passivation layer, a second ESD protection line (element 831) electrically coupled to the first ESD protection line via a first opening in the passivation layer adjacent to the first cluster and via a second opening in the passivation layer adjacent to the second cluster (see in particular L2 Fig. 10H plurality of openings for element 831 to connect through passivation layer element 5 to the first ESD protection line as combined in L1 – see “Labeled Fig. 2” above a second opening would be electrically coupled; note, the manner in which the claim is currently recited does not require physical coupling) . The passivation layer and second ESD protection line as taught by L2 is incorporated as a passivation layer and second ESD protection line of L1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L2 with L1 because the combination allows for thicker conductor connection to the top of the chip to communicate with an external circuit (see L2 [0292-0293]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known external connection wiring for another in a similar device for another to obtain predictable results (see L2 Fig. 10A). 16. Regarding Claim 13 , L1, L2 disclose the method of claim 12, comprising forming the top metal layer during a wafer processing stage (the top metal layer formation can be included as part of what is being considered as the wafer processing stage – the manner in which the claim is currently recited does not provide a specific wafer processing step to have a relationship with the formation of the top metal layer) . 17. Regarding Claim 14 , L1, L2 disclose the method of claim 13, comprising forming the redistribution metal layer during a packaging stage (the redistribution metal layer formation can be included as part of what is being considered as the packaging stage – the manner in which the claim is currently recited does not provide a packaging processing step to have a relationship with the formation of the redistribution metal layer) . 18. Regarding Claim 15 , L1, L2 disclose the method of claim 12, comprising: forming, from the top metal layer, an ESD connection line (element L1 between element “Third Cluster” and element GP) ; and forming, from the redistribution metal layer, a third ESD protection line (see L1 “Labeled Fig. 2” above, the combined third ESD protection line over element L1 between labeled element “Third Cluster” and element GP; same material as the second ESD protection line, see L2 [0290]) electrically coupled to the second ESD protection line by the ESD connection line (see L1 Figs. 2-3 and “Labeled Fig. 2” above) . 19. Regarding Claim 16 , L1, L2 disclose the method of claim 12, wherein the first ESD protection line has a higher resistance between the first and second clusters than does the second ESD protection line (see L2 the first ESD protection line element 6390 material [0219] “contact pads 6390, principally made of aluminum or copper” selected as aluminum, and see [0188] “the seed layer may be formed by a suitable process or processes, e.g., by sputtering a copper layer … Thereafter, the metal layer 8112 may be formed by a suitable process or processes, e.g., by electroplating a copper layer”) . 20. Regarding Claim 17 , L1, L2 disclose the method of claim 16, wherein the first top metal layer includes aluminum (see L2 the first ESD protection line element 6390 material [0219] “contact pads 6390, principally made of aluminum or copper” selected as aluminum) and the redistribution metal layer includes copper (see L2 [0188] “the seed layer may be formed by a suitable process or processes, e.g., by sputtering a copper layer … Thereafter, the metal layer 8112 may be formed by a suitable process or processes, e.g., by electroplating a copper layer”) . 21. Regarding Claim 18 , L1 discloses a method (see Figs. 1-14, in particular “Labeled Fig. 2” above, and [0011] “semiconductor device”) , comprising: forming, from a top metal layer (top metal layer above element 120, see [0051] “the conductive material may include copper (Cu) or tungsten (W)”) of an integrated circuit die (element 20, see [0025] “semiconductor die 20”) : a first cluster (labeled element “First Cluster” of elements DP1, see [0029] “first die pads DP1”) of first interior contact pads adjacent to each other (see “Labeled Fig. 2” above) ; a second cluster (labeled element “Second Cluster” of elements DP1) of second interior contact pads adjacent to each other (see “Labeled Fig. 2” above) ; a plurality of peripheral contact pads (see L1 “Labeled Fig. 2” above, labeled element “Third Cluster”) adjacent to an edge of the integrated circuit die (see “Labeled Fig. 2” above) ; a first ESD protection line (element L1 between labeled element “First Cluster” and “Second Cluster” and see [0043] “an electrostatic discharge (ESD) protection circuit may be constituted by the transistors TR connected to the first die pads DP1 … the first die pads DP1 may be connected through the second wiring line L2” and [0048] “the first die pads DP1 may be coupled through the first wiring lines L1 to the grouping pattern GP”) extending between the first cluster and the second cluster and electrically coupled to each of the first and second interior contact pads by ESD protection circuitry (see [0043] “an electrostatic discharge (ESD) protection circuit may be constituted by the transistors TR connected to the first die pads DP1”) ; and forming a plurality of solder connection structures (see L1 Figs. 2-3 elements 130 which are electrically connected to the respective elements DP1 of elements “First Cluster”, element “Second Cluster”, and “Third Cluster”, see [0042] “connection terminals 130 may include a micro-bump”) each coupled to a respective first interior contact pad, a second interior contact pad, or a peripheral contact pad. L2 discloses (see Fig. 10) forming, from a redistribution metal layer (element 831, see [0290] “course metal traces 83, 831, 832, and 83r over the passivation layer 5”) over the top metal layer (element 6390, 638 layer, see [0219] “pads 6390, principally made of aluminum or copper”) , a second ESD protection line (element 831 in direct contact with the element 6390, 638 element which connects to the ESD circuit element 43, see [0293] “ESD circuit 43” connected to element 638, 831 through element 6391 and 69) shorting out at least a portion of the first ESD protection line (see Fig. 10) . The passivation layer and second ESD protection line as taught by L2 is incorporated as a passivation layer and second ESD protection line of L1, wherein the combination further discloses solder connection structures each coupled to the respective first interior contact pad, a second interior contact pad, or a peripheral contact pad by portions of the redistribution metal layer (The combination provides the redistribution metal layer also in electrical contact with the solder connection structures and respective pads). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L2 with L1 because the combination allows for thicker conductor connection to the top of the chip to communicate with an external circuit (see L2 [0292-0293]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known external connection wiring for another in a similar device for another to obtain predictable results (see L2 Fig. 10A). 22. Regarding Claim 19 , L1, L2 disclose the method of claim 18, wherein the first ESD protection line has a higher resistance between the first and second clusters than does the second ESD protection line (see L2 the first ESD protection line element 6390 material [0219] “contact pads 6390, principally made of aluminum or copper” selected as aluminum, and see [0188] “the seed layer may be formed by a suitable process or processes, e.g., by sputtering a copper layer … Thereafter, the metal layer 8112 may be formed by a suitable process or processes, e.g., by electroplating a copper layer”) . 23. Regarding Claim 20 , L1, L2 disclose the method of claim 19, wherein the first top metal layer includes aluminum (see L2 the first ESD protection line element 6390 material [0219] “contact pads 6390, principally made of aluminum or copper” selected as aluminum) and the redistribution metal layer includes copper (see L2 [0188] “the seed layer may be formed by a suitable process or processes, e.g., by sputtering a copper layer … Thereafter, the metal layer 8112 may be formed by a suitable process or processes, e.g., by electroplating a copper layer”) . 24. Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over ee et al. (US 2022/0068853 A1), hereinafter as L1, in view of Lin et al. (US 2010/0246152 A1), hereinafter as L2, in view of Bhatkar et al. (US 10,121,755 B1), hereinafter as B1 25. Regarding Claim 9 , L1, L2 disclose the device of claim 1, wherein the integrated circuit includes (see L1) : a plurality of third contact pads (third elements DP1 of labeled element “Third Cluster”) formed of the top metal layer (see Figs. 2-3) and positioned adjacent to an edge of the integrated circuit die (see “labeled Fig. 2” above) ; and a ground ring (see each of the elements DP1 of labeled element “Third Cluster” connected through element GP and L1 [0049] “the grouping pattern GP may mutually connect ground circuits or electrostatic discharge (ESD) protection circuits of the integrated devices formed on the semiconductor substrate 100 and may supply uniform ground voltages to the ground circuits or the ESD protection circuits”). L1, L2 do not explicitly disclose the ground ring is below the third contact pads. B1 discloses the ground ring is below the contact pad (see Column 3 lines 61-63 “The seal ring may also provide a low resistance path to ground for protection against a surge current caused by electrostatic discharge (ESD)” and Fig. 3a the seal ring extends from the substrate to below a top metal layer level of contact pad element 358). The ground ring location with respect to the contact pad as taught by B1 is incorporated as a ground ring location with respect to the third contact pads of L1, L2. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of B1 with L1, L2 because the combination provides crack stop and electrostatic discharge protection (see Column 3 lines 51-63); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known specific ground circuitry to provide ESD protection for another in a similar device to obtain predictable results (see B1 Fig. 3a and Column 3 lines 51-63). 26. Regarding Claim 10 , L1, L2, B1 disclose the device of claim 9, wherein the first and second clusters are further from the edge than are the contact pads (see “Labeled Fig. 2” above) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT SAMUEL PARK whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (303)297-4277 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m. . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Steven H. Loke can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1657 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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