DETAILED ACTION
This Office action is in response to the filing of this application on 06 August 2023. Claims 1-20 are pending in the application.
This application is a divisional of application Serial No. 17/124,017, filed on 16 December 2020, now US Patent 12,266,572.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 18 is rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Hsu et al., US 2018/0166532, cited by Applicant on the Information Disclosure Statement (IDS) submitted on 06 August 2023.
With respect to claim 18, Hsu et al. disclose a device, shown in Fig. 5, comprising:
a semiconductor fin 12;
a gate stack 14 on the semiconductor fin 12; and
a source/drain region 30/34 on a side of the semiconductor fin 20, wherein the source/drain region comprises an embedded stressor, and
the embedded stressor 34 comprises: a V-shaped bottom surface, wherein a top end of the V-shaped bottom surface 32 is at a same level as a top surface of the semiconductor fin 12; and a V-shaped top surface, wherein a first portion of the V-shaped top surface is higher than the top surface of the semiconductor fin 12, and a second portion of the V-shaped top surface is lower than the top surface of the semiconductor fin 12, as shown in Fig. 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al., US 2018/0166532, as applied to claim 18 above, in view of Zhu et al., US 2008/0057710.
With respect to claim 19, the device of Hsu et al. further comprises a semiconductor layer 30 underlying the embedded stressor 34, however, Hsu et al. lack anticipation of the semiconductor layer 30 comprising a facet on a (111) surface plane of the semiconductor layer. In the same field of endeavor, Zhu et al. disclose source/drain recesses 15 having sidewall surfaces 17B oriented along the (111) surface plane to improve the stress profile created in the channel region of the MOSFET, as shown in Fig. 7 of Zhu et al. In light of the teaching of Zhu et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the trench 26 having slanted sidewalls on a (111) plane so that the semiconductor layer 30 in the known method of Hsu et al. comprises a facet on a (111) surface plane (see Fig. 2 of Hsu et al.), thereby improving the stress profile in the channel region of the transistor of Hsu et al.
With respect to claim 20, in the combination of Hsu et al. and Zhu et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the facet on the (111) surface plane would extend to join a top corner of the semiconductor fin, since the slanted sidewall of the trench 15, shown in Fig. 7 of Zhu et al., joins the top surface of fin 17.
Claims 9-11, 14, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., US 2018/0175172, in view of Kuang et al., US 2015/0372142, both cited by Applicant on the Information Disclosure Statement (IDS) filed on 06 August 2023.
With respect to claim 9, Chang et al. disclose a device comprising:
a semiconductor substrate 50, as shown in Fig. 6A;
isolation regions 62 extending into the semiconductor substrate 50, as shown in Fig. 6A;
a semiconductor fin 64 protruding higher than top surfaces of the isolation regions 62, as shown in Fig. 6A;
a gate stack 66/68 on a top surface and sidewalls of the semiconductor fin 64, as shown in Fig. 6A; and
a source/drain region 80/86/88 on a side of the semiconductor fin, as shown in Fig. 13.
Chang et al. lack anticipation only of the source/drain region comprising: a first semiconductor layer having a first dopant concentration; and an embedded stressor over and contacting the first semiconductor layer, wherein the embedded stressor has a second dopant concentration higher than the first dopant concentration, and wherein the embedded stressor has an upper portion higher than the top surface of the semiconductor fin, and a lower portion lower than the top surface of the semiconductor fin. Kuang et al. disclose a source/drain region of a transistor having raised source/drain regions which comprise: a first semiconductor layer 54 having a first dopant concentration; and an embedded stressor 55 over and contacting the first semiconductor layer 54, wherein the embedded stressor 55 has a second dopant concentration higher than the first dopant concentration (see paragraph [0026]: “The third epitaxial-grown doped layer 55 includes a dopant concentration higher than these of the first and second epitaxial-grown doped layer (52, 54).”), and
wherein the embedded stressor 55 has an upper portion higher than the top surface of the semiconductor fin 20, and a lower portion lower than the top surface of the semiconductor fin 20, as shown in Fig. 1. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the source/drain region taught by Kuang et al. in the known transistor of Chang et al., since the stressor of Kuang et al. maintains stress in the channel region of the transistor, thereby obtaining higher drive currents and switching speeds.
With respect to claim 10, the combination of Chang et al. and Kuang et al. further comprises a gate spacer 34 on a sidewall of the gate stack 32/33 (shown in Fig. 1 of Kuang et al.), wherein the upper portion of the embedded stressor 55 contacts the gate spacer 34 to form a vertical interface, and wherein a bottom surface of the embedded stressor 55 is slanted, and joins to a point where a bottom of an outer surface of the gate spacer 34 joins a top end of a sidewall of the semiconductor fin 20, as shown in annotated Fig. 1 of Kuang et al.
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With respect to claim 11, as shown in Fig. 1 of Kuang et al., the embedded stressor 55 has a V-shaped bottom surface, see annotated Fig. 1 above.
With respect to claim 14, Kuang et al. teaches that the device further comprises further comprising a second semiconductor layer 52 under the first semiconductor layer 54, wherein the second semiconductor layer 52 has a lower dopant concentration than the first semiconductor layer, see paragraph [0026].
With respect to claim 15, as shown in Fig. 1 of Kuang et al., the first semiconductor layer 52 has a first facet having a first top end, the second semiconductor layer 54 has a second facet having a second top end, and wherein the first top end joins the second top end, and further joins a top corner of the semiconductor fin 20, as shown in Fig. 1 of Kuang et al..
With respect to claim 17, in the device of Kuang et al., as shown in Fig. 1, the embedded stressor 55 comprises a V-shaped bottom surface, with a topmost point of the V-shaped bottom surface being at a same level as the top surface of the semiconductor fin 20, as shown in Fig. 1.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., US 2018/0175172, in view of Kuang et al., US 2015/0372142, as applied to claim 15 above, further in view of Zhu et al., US 2008/0057710.
With respect to claim 16, although Kuang et al. disclose that the first semiconductor layer 52 has a first facet and the second semiconductor layer 54 has a second facet, Kuang et al. fail to teach or suggest one of the first facet and one of the second facet is on a (111) surface plane of the source/drain region. In the same field of endeavor, Zhu et al. disclose source/drain recesses 15 having slanted sidewall surfaces 17B oriented along the (111) surface plane, as shown in Fig. 7 of Zhu et al. In light of the teaching of Zhu et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first and second facets of the first and second semiconductor layers would be on a (111) surface plane of the source/drain region.
.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., US 2018/0175172, in view of Kuang et al., US 2015/0372142, as applied to claim 9 above, further in view of Shin et al., US 9,240,323.
With respect to claim 12, Kuang et al. further teach a source/drain silicide region 40 over and contacting the embedded stressor 55, however, Kuang et al. discloses the silicide region 40 being U-shaped in a cross-sectional view, as shown in Fig. 1. Therefore, Kuang et al. lack anticipation of the source/drain silicide region 40 having a V-shape in a cross-sectional view. Shin et al. disclose a transistor having a raised source/drain region in which the source/drain silicide region 151 is V-shaped in a cross-sectional view, as shown in Figs. 1 and 6A, to promote the flow of current (see column 6, lines 51-65). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the source/drain silicide region 40 in the known device of Kuang et al. have a V-shape in a cross-sectional view in order to promote the flow of current.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., US 2018/0175172, in view of Kuang et al., US 2015/0372142, as applied to claim 9 above, further in view of Kuang et al., US 2016/0013316, hereinafter Kuang et al. ‘316cited by Applicant on the Information Disclosure Statement submitted on 06 August 2023.
With respect to claim 13, Kuang et al. teach the embedded stressor comprises silicon phosphorous (see paragraphs [0023] and [0026], and the device further comprises a capping layer 56 over the embedded stressor 55, and wherein the capping layer 56 comprises silicon and phosphorous, see paragraphs [0023] and [0026]. However, Kuang et al. do not teach that the capping layer 56 also comprises germanium. However, in the same field of endeavor, Kuang et al. ‘316 discloses a capping layer 230 can comprise silicon or SiGe, see paragraph [0036]. In light of the teaching of Kuang et al. ‘316, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the capping layer 56 in the known device of Kuang et al. could comprise germanium, since Kuang et al. ‘316 teach the functional equivalence of silicon and silicon germanium capping layers.
Allowable Subject Matter
Claims 1-8 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: None of the references of record teach or suggest a device comprising a semiconductor fin; a gate stack on the semiconductor fin; a gate spacer on a sidewall of the gate stack; and a source/drain region aside of the gate spacer and comprising: a first semiconductor layer contacting a sidewall of the semiconductor fin, wherein the first semiconductor layer has a first phosphorous concentration; a second semiconductor layer over and contacting the first semiconductor layer, wherein a first topmost tip of a first top portion of the second semiconductor layer is joined to a top corner of the semiconductor fin, and one of a top surface and a bottom surface of the first top portion has a (111) lattice plane, and the second semiconductor layer has a second phosphorous concentration higher than the first phosphorous concentration; and an embedded stressor over and contacting the second semiconductor layer, wherein the embedded stressor has a third phosphorous concentration higher than the second phosphorous concentration, and the embedded stressor comprises: an upper portion contacting the gate spacer to form a vertical interface; and a lower portion lower than the top corner of the semiconductor fin, as recited in independent claim 1
Claims 2-8 are allowable because of their dependence on independent claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose various devices having epitaxial source/drain regions.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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