Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Invention I, claims 1-11, have been elected without traverse. The non-elected claims 12-20 have been withdrawn from further consideration.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4, 8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Pub. No. US 2024/0105615 A1, herein Lee) in view of Chiang et al. (Pub. No. US 2024/0047273 A1, herein Chiang).
Regarding claim 1, Lee discloses a semiconductor structure, comprising: a front-end-of-line level including a plurality of field effect transistors (Lee: Figs. 36A-36D and paragraph [0059]), each field effect transistor including a source/drain region “SD1/SD2/SD4” disposed on opposite sides of the field effect transistor (Lee: Figs. 36A-36D and paragraphs [0094]-[0097]); a metal contact region “CA1/V0/M1/M2/CA2/V1” disposed above and in contact with a first surface of two adjacent source/drain regions, each of the two laterally adjacent source/drain regions corresponding to a field effect transistor (Lee: Figs. 36A-36D and paragraphs [0123]-[0130]); and a backside isolation region “116/180” cutting through the metal contact region from a backside of the plurality of field effect transistors, the backside isolation region electrically isolating the two adjacent source/drain regions (Lee: Figs. 36A-36D and paragraphs [0115]-[0119]).
Lee does not specifically show wherein opposite sides of the backside isolation region are in direct contact with the metal contact region.
However, in the same field of endeavor, Chiang teaches a semiconductor structure, comprising: a plurality of field effect transistors (Chiang: paragraph [0016]), each field effect transistor including a source/drain region 208 (Chiang: paragraph [0022]) disposed on opposite sides of the field effect transistor (Figs. 16A-B); a metal contact region 214/210a-d (Chiang: paragraph [0025]) disposed above a first surface of two adjacent source/drain regions, each of the two laterally adjacent source/drain regions corresponding to a field effect transistor (Chiang: paragraph [0022]); and a backside isolation region 244-230 (Chiang: paragraphs [0031], [0038]) cutting through the metal contact region from a backside of the plurality of field effect transistors, the backside isolation region electrically isolating the two adjacent source/drain regions, wherein opposite sides 230a-230b of the backside isolation region are in direct contact with the metal contact region (Chiang: paragraph [0031] and Figs. 16A-B) to divide active regions into segments, improve density of devices, and achieve desired scaling effect while maintaining the devices' proper functions (e.g., avoiding electrical shorting), such that the separation distance between adjacent devices may be reduced or minimized without compromising device performance (Chiang: paragraph [0017]).
Therefore, given the teachings of Chiang, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lee in view of Chiang by employing the backside isolation region.
Regarding claim 2, Lee in view of Chiang teaches the semiconductor structure of claim 1, further comprising: an interlevel dielectric layer “172/173/174” deposited above the field effect transistors; and a backside interlevel dielectric “177/176/175/171” dispose below the field effect transistors, the backside interlevel dielectric being in contact with a second surface of the two adjacent source/drain regions, the second surface of the two adjacent source/drain regions opposing the first surface of the two adjacent source/drain regions (Lee: Figs. 36A-36D and paragraphs [0100]-[0101], [0142]).
Regarding claim 4, Lee in view of Chiang teaches the semiconductor structure of claim 1, wherein the backside isolation region comprises a reverse tapered profile (Lee: Figs. 36A-36D and paragraphs [0115]-[0119]).
Regarding claim 8, Lee in view of Chiang teaches the semiconductor structure of claim 1, wherein the metal contact region electrically connects a first side of the two adjacent source/drain regions to a back-end-of-line level (Lee: Figs. 36A-36D, Abstract and paragraph [0131]).
Regarding claim 10, Lee in view of Chiang teaches the semiconductor structure of claim 8, further comprising: a carrier wafer located above the back-end-of-line level (Lee: Figs. 36A-36D, paragraphs [0131]-[0133]).
Regarding claim 11, Lee in view of Chiang teaches the semiconductor structure of claim 1, wherein each of the field effect transistors further comprises: a gate structure “G1-G6” located above and surrounding a plurality of channel layers “CH1-CH6” (Lee: Figs. 36A-36D, paragraphs [0114]-[0115]).
Claims 3, 7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chiang, as applied above, and further in view of Ju et al. (Pub. No. US 2022/0216346 A1, herein Ju).
Regarding claim 3, the previous combination does not specifically show dielectric spacers disposed on opposite sides of the backside interlevel dielectric.
However, in the same field of endeavor, Ju teaches a back-side power rail device, wherein dielectric spacers 118 disposed on opposite sides of the backside interlevel dielectric 126 (Ju: Figs. 1, 6C and paragraph [0027]) to control stress, electric fields, leakage, and process damage, therefore improving device performance, reliability and manufacturability.
Therefore, given the teachings of Ju, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lee in view of Ju by employing the dielectric spacers on opposite sides of the backside interlevel dielectric.
Regarding claim 7, Lee in view of Chiang and further in view of Ju teaches the semiconductor structure of claim 3, further comprising: a shallow trench isolation region 116 located between a bottom portion of the interlevel dielectric and upper surfaces of the dielectric spacers and the backside isolation region (Lee: Figs. 36A-36C and paragraph [0062], and Ju: Figs. 1, 6C and paragraph [0027]).
Regarding claim 9, Lee in view of Chiang and further in view of Ju teaches the semiconductor structure of claim 3, further comprising: a backside metal contact “BCA1” within the backside interlevel dielectric layer, the backside metal contact electrically connecting a second side of at least another source/drain region without a metal contact region to a backside interconnect “BPR”, wherein a first side of the at least another source/drain region is in contact with the interlevel dielectric layer and the backside metal contact is abutted by the dielectric spacers (Lee: Figs. 36A-36C and paragraphs [0158]-[0161], and Ju: Figs. 1, 6C and paragraph [0027]).
Allowable Subject Matter
Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 5, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, wherein the backside isolation region having the reverse tapered profile comprises: a top portion of the backside isolation region embedded within the metal contact region having a first critical dimension, the top portion of the backside isolation region partially extending into the interlevel dielectric layer and occupying, at least in part, an area between adjacent conductive vias; and a bottom portion of the backside isolation region located between the dielectric spacers having a second critical dimension, wherein the second critical dimension is larger than the first critical dimension.
With respect to claim 6, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, wherein portions of the backside isolation region are located between the dielectric spacers with a bottom surface of the backside isolation region being flushed with a bottom surface of the dielectric spacers and a bottom surface of the backside interlevel dielectric.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1-4 and 7-11 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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July 7, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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