DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 3/27/26.
Applicant’s amendment to claims 1-3, 6, 8, 12 and 17 is acknowledged.
Applicant’s cancellation of claims 4, 5, 10, 11 and 16 is acknowledged.
Applicant’s addition of new claims 21 and 22 is acknowledged.
Claims 1-3, 6-9, 12-15 and 17-22 are pending and claims 6-8 and 15 are withdrawn.
Claims 1-3, 9, 12-14 and 17-22 are subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Allowable Subject Matter
Claim 20 is allowed.
Claims 2 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 3, the limitation “wherein diameters of the first core through electrodes are 1.5 times or less the diameters of the second core through electrodes” is indefinite because claim 1 requires “diameters of the first core through electrodes are greater than diameters of the second core through electrodes”
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 9 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends
Claim 9 depends from withdrawn claim 8.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 12-14, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suwada, US Publication No. 2016/0020268 A1 (of record) in view of Nagamatsu et al., US Publication No. 2006/0146135 A1 (of record) and Aiba et al., KR 20060092800 A.
Regarding claim 1:
In the embodiment shown in fig. 6, Suwada does not teach a package substrate. However, it would have been obvious to one of ordinary skill in the art to stack the device in fig. 6 on a package substrate, because Suwada teaches a package substrate in the embodiment in fig. 13.
Thus, Suwada teaches:
1. A semiconductor package comprising (see figs. 6 and 13):
a package substrate (410 in fig.13); and
a silicon-free interposer (90 in fig. 6) on the package substrate, wherein
the package substrate (410) includes a first core layer (e.g. substrate material of PCB 410), first core through electrodes (414 narrow) passing through the first core layer, and second core through electrodes (414 wide) passing through the first core layer,
the first core through electrodes (414 narrow) are configured to be applied with a signal (e.g. 414 narrow is connected to signals NEG, POS),
the second core through electrodes (414 wide) are configured to be applied with power (e.g. 414 wide is connected to Vcc),
the silicon-free interposer (90) includes a second core layer (114), first interposer through electrodes (111b) passing through the second core layer, and second interposer through electrodes (112b or 113b) passing through the second core layer,
the first interposer through electrodes are connected to the first core through electrodes (e.g. Fig. 13 teaches coupling between the package substrate 410 comprising the core through electrodes and interposer 420 comprising the interposer through electrodes. Also, all the elements of the package are either electrically connected to each other; or directly connected to each other; or indirectly connected to each other through intervening layers to form the overall package.),
the second interposer through electrodes are connected to the second core through electrodes (e.g. Fig. 13 teaches coupling between the package substrate 410 comprising the core through electrodes and interposer 420 comprising the interposer through electrodes. Also, all the elements of the package are either electrically connected to each other; or directly connected to each other; or indirectly connected to each other through intervening layers to form the overall package.)... See Suwada at para. [0001] – [0183], figs. 1-19.
Regarding claim 1,
Suwada is silent the signal is a high-speed signal.
In an analogous art, Nagamatsu teaches “In recent years, a number of specifications of high speed interfaces in which a high speed signal of some hundreds MHz, GHz band or 10 GHz in the future passes through outside of a semiconductor chip such as a package, a board or the like is increased…”, para. [0005].
Suwada does not expressly teach:
diameters of the first core through electrodes are greater than diameters of the second core through electrodes.
In an analogous art, Aiba teaches (see fig. 9 annotated below) first core through electrodes (81) for high frequency signals. See Aiba at page 10, “On the other hand, the through via 81 is arranged in correspondence with the position where the high frequency external connection terminals of the high frequency semiconductor element 110 are arranged.”
Aiba further teaches (see figs. 5 and 9) second core through electrodes connected to a power supply. See Aiba at page 12, “The electrode pad 112 is an electrode pad used when transmitting a high frequency signal, while the electrode pad 113 is an electrode pad connected to a power supply line, a ground (ground) line, or a wiring that handles a relatively low frequency signal.”
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Thus, Aiba teaches:
diameters of the first core through electrodes (81, e.g. carrying high frequency signals) are greater than diameters of the second core through electrodes (e.g. smaller diameter through electrodes carrying power).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Suwada with the teachings of Aiba because adjusting the diameter of the first core though electrodes (e.g. carrying high frequency signals) correspondingly adjusts the pitch of the terminals on the semiconductor chip. This enables high frequency signals to be transmitted with good accuracy between the semiconductor chip and the mounting board and reduce transmission loss. See Aiba at pages 17-18.
Regarding claim 3:
Suwada teaches:
3. The semiconductor package of claim 1, wherein diameters of the first core through electrodes (414 narrow) are 1.5 times or less the diameters of the second core through electrodes (414 wide), fig. 13. Also see the 35 USC 112 rejection above.
Furthermore, Suwada teaches the diameters of the through electrodes is a result effective variable to achieve satisfactory power integrity, para. [0040], [0052], fig. 16.
It would have been obvious to one having ordinary skill in the art to form “wherein diameters of the first core through electrodes are 1.5 times or less the diameters of the second core through electrodes”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Regarding claim 12:
In the embodiment shown in fig. 6, Suwada does not teach a package substrate. However, it would have been obvious to one of ordinary skill in the art to stack the device in fig. 6 on a package substrate, because Suwada teaches a package substrate in the embodiment in fig. 13.
Thus, Suwada teaches:
12. A semiconductor package comprising (see figs. 6 and 13):
a package substrate (410 in fig. 13);
a silicon-free interposer (90 in fig. 6) on the package substrate; and
a first semiconductor chip (430 in fig. 13)and a second semiconductor chip (440 in fig. 13) on the silicon-free interposer (e.g. In fig. 6, one chip 60 is shown. However, it would have been obvious to one of ordinary skill in the art to form two chips on the interposer because Suwada teaches two chips 430, 440 in fig. 13.), wherein
the package substrate (410) includes a first core layer (e.g. substrate material of PCB 410), first core through electrodes (414 narrow) passing through the first core layer, and second core through electrodes (414 wide) passing through the first core layer,
the silicon-free interposer (90) includes a second core layer (114), first interposer through electrodes (112b or 113b) passing through the second core layer, and second interposer through electrodes (111b) passing through the second core layer,
the first interposer through electrodes are connected to the first core through electrodes (e.g. Fig. 13 teaches coupling between the package substrate 410 comprising the core through electrodes and interposer 420 comprising the interposer through electrodes. Also, all the elements of the package are either electrically connected to each other; or directly connected to each other; or indirectly connected to each other through intervening layers to form the overall package.),
the second interposer through electrodes are connected to the second core through electrodes (e.g. Fig. 13 teaches coupling between the package substrate 410 comprising the core through electrodes and interposer 420 comprising the interposer through electrodes. Also, all the elements of the package are either electrically connected to each other; or directly connected to each other; or indirectly connected to each other through intervening layers to form the overall package.),
the semiconductor package is configured to output a signal (NEG, POS in fig. 13) from the first semiconductor chip (430) and the second semiconductor chip (440) to an outside region through the first interposer through electrodes (e.g. In fig. 13, interposer 420 comprises through electrodes 423 that corresponds to interposer through electrodes of fig. 6) and the first core through electrodes (414 narrow), and …See Suwada at para. [0001] – [0183], figs. 1-19.
Further regarding claim 12,
Suwada is silent the signal is a high-speed signal.
In an analogous art, Nagamatsu teaches “In recent years, a number of specifications of high speed interfaces in which a high speed signal of some hundreds MHz, GHz band or 10 GHz in the future passes through outside of a semiconductor chip such as a package, a board or the like is increased…”, para. [0005].
Suwada does not expressly teach:
diameters of the first core through electrodes are greater than diameters of the second core through electrodes.
Aiba teaches this limitation as applied to claim 1 above.
Regarding claim 13:
Aiba further teaches:
13. The semiconductor package of claim 12, wherein a frequency of the high-speed signal is 1 GHz or more, page 2.
Nagamatsu also teaches:
13. The semiconductor package of claim 12, wherein a frequency of the high-speed signal is 1 GHz or more, para. [0005].
Regarding claim 14:
Suwada teaches the diameters of the through electrodes is a result effective variable to achieve satisfactory power integrity, para. [0040], [0052], fig. 16.
It would have been obvious to one having ordinary skill in the art to form “wherein the diameters of the first interposer through electrodes are in a range of 30 μm to 80 μm”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Regarding claim 18:
Aiba teaches the diameters of the through electrodes is a result effective variable to enable high frequency signals to be transmitted with good accuracy between the semiconductor chip and the mounting board and reduce transmission loss. See Aiba at pages 17-18.
It would have been obvious to one having ordinary skill in the art to form “wherein the diameters of the first core through electrodes are in a range of 75 μm to 190 μm.”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Regarding claim 19:
Aiba teaches the diameters of the through electrodes is a result effective variable to enable high frequency signals to be transmitted with good accuracy between the semiconductor chip and the mounting board and reduce transmission loss. See Aiba at pages 17-18.
It would have been obvious to one having ordinary skill in the art to form “wherein a diameter of each of the second core through electrodes is in a range of 75 μm to 125 μm”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Suwada with the teachings of Nagamatsu because in recent years specifications have increased for high speed signals with high operation frequency. See Nagamatsu at para. [0005].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Suwada with the teachings of Aiba because “Thus, by increasing the diameter of the through via 81 provided in the support substrate 71, the high frequency external connection terminal 121 is not changed without changing the arrangement pitch P1 of the external connection terminal in the high frequency semiconductor element 110…Thereby, the high frequency signal can be transmitted between the high frequency external connection terminal 121 and the external connection terminal 98 with good accuracy without impairing the high frequency characteristics of the high frequency semiconductor element 110… By connecting the high frequency external connection terminal 121…the transmission loss of the high frequency signal transmitted between the external connection terminal 98 can be reduced.” See Aiba at pages 17-18.
Claim(s) 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suwada in view of Nagamatsu and Aiba, as applied to claims 1 and 12 above, in further view of Kheng, US Publication No. 2003/0164543 A1.
Regarding claims 21 and 22:
Suwada teaches all the limitations of claims 1 and 12 above, and further teaches the interposer comprises a substrate (110) made of silicon, silicon germanium (SiGe), silicon carbide (SiC) or gallium nitride (GaN) at para. [0089].
Suwada does not expressly teach the silicon-free interposer does not include a semiconductor substrate.
In an analogous art, Kheng teaches “A substrate of the interposer may be formed from a variety of different, typically electrically insulative or insulator-coated materials, including flexible materials, such as polymer (e.g., polyimide) films or tapes, and rigid materials, such as silicon, glass, ceramic, or organic materials (e.g., FR-4 resin).” See Kheng at para. [0006].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Suwada with the teachings of Kheng because one of ordinary skill in the art would be motivated to look for alternative materials for the interposer substrate and Kheng teaches polymers or ceramics are known materials suitable as a substrate in an interposer. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose: “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle. 325 U.S. at 335, 65 USPQ at 301.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818 20 May 2026
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