DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of species A, figs. 1 and 5, claims 1-3, 8, 9, 12-14, 16, 17 and 18-20 in the reply filed on10/7/25 is acknowledged.
Claims, 4-7, 10, 11, 15 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/7/25.
Per 37 CFR 1.121, claim 16 should have a status of “original”.
Allowable Subject Matter
Claim 20 is allowed.
Claims 2-3 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, 9, 12-14, 16, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suwada, US Publication No. 2016/0020268 A1 in view of Nagamatsu et al., US Publication No. 2006/0146135 A1.
Regarding claim 1:
In the embodiment shown in fig. 6, Suwada does not teach a package substrate. However, it would have been obvious to one of ordinary skill in the art to stack the device in fig. 6 on a package substrate, because Suwada teaches a package substrate in the embodiment in fig. 13.
Thus, Suwada teaches:
1. A semiconductor package comprising (see figs. 6 and 13):
a package substrate (410 in fig.13); and
a silicon-free interposer (90 in fig. 6) on the package substrate, wherein
the package substrate (410) includes a first core layer (e.g. substrate material of PCB 410), first core through electrodes (414 narrow) passing through the first core layer, and second core through electrodes (414 wide) passing through the first core layer,
the first core through electrodes (414 narrow) are configured to be applied with a signal (e.g. 414 narrow is connected to signals NEG, POS),
the second core through electrodes (414 wide) are configured to be applied with power (e.g. 414 wide is connected to Vcc),
the silicon-free interposer (90) includes a second core layer (114), first interposer through electrodes (111b) passing through the second core layer, and second interposer through electrodes (112b or 113b) passing through the second core layer,
the first interposer through electrodes are connected to the first core through electrodes (e.g. Fig. 13 teaches coupling between the package substrate 410 comprising the core through electrodes and interposer 420 comprising the interposer through electrodes. Also, all the elements of the package are either electrically connected to each other; or directly connected to each other; or indirectly connected to each other through intervening layers to form the overall package.),
the second interposer through electrodes are connected to the second core through electrodes (e.g. Fig. 13 teaches coupling between the package substrate 410 comprising the core through electrodes and interposer 420 comprising the interposer through electrodes. Also, all the elements of the package are either electrically connected to each other; or directly connected to each other; or indirectly connected to each other through intervening layers to form the overall package.),
diameters of the first core through electrodes (414 narrow) are different from diameters of the second core through electrodes (414 wide), and
diameters of the first interposer through electrodes (111b) are different from diameters of the second interposer through electrodes (112b or 113b). See Suwada at para. [0001] – [0183], figs. 1-19.
Further regarding claim 1,
Suwada is silent the signal is a high-speed signal.
In an analogous art, Nagamatsu teaches “In recent years, a number of specifications of high speed interfaces in which a high speed signal of some hundreds MHz, GHz band or 10 GHz in the future passes through outside of a semiconductor chip such as a package, a board or the like is increased…”, para. [0005].
Suwada further teaches:
8. The semiconductor package of claim 1, wherein the diameters of the first interposer through electrodes (111b) are less than the diameters of the second interposer through electrodes (112b or 113b), fig. 6.
9. The semiconductor package of claim 8, wherein the diameters of the first interposer through electrodes (111b) are 0.5 times or more the diameters of the second interposer through electrodes (112b), fig. 6.
Regarding claim 9:
MPEP § 2125, Drawings as Prior Art, indicates:
” Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972)…When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). See MPEP § 2121.04 for more information on prior art drawings as “enabled disclosures.”
Suwada teaches the diameters of the through electrodes is a result effective variable to achieve satisfactory power integrity, para. [0040], [0052], fig. 16.
It would have been obvious to one having ordinary skill in the art to form “wherein the diameters of the first interposer through electrodes are 0.5 times or more the diameters of the second interposer through electrodes”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Regarding claim 12:
In the embodiment shown in fig. 6, Suwada does not teach a package substrate. However, it would have been obvious to one of ordinary skill in the art to stack the device in fig. 6 on a package substrate, because Suwada teaches a package substrate in the embodiment in fig. 13.
Thus, Suwada teaches:
12. A semiconductor package comprising (see figs. 6 and 13):
a package substrate (410 in fig. 13);
a silicon-free interposer (90 in fig. 6) on the package substrate; and
a first semiconductor chip (430 in fig. 13)and a second semiconductor chip (440 in fig. 13) on the silicon-free interposer (e.g. In fig. 6, one chip 60 is shown. However, it would have been obvious to one of ordinary skill in the art to form two chips on the interposer because Suwada teaches two chips 430, 440 in fig. 13.), wherein
the package substrate (410) includes a first core layer (e.g. substrate material of PCB 410), first core through electrodes (414 narrow) passing through the first core layer, and second core through electrodes (414 wide) passing through the first core layer,
the silicon-free interposer (90) includes a second core layer (114), first interposer through electrodes (112b or 113b) passing through the second core layer, and second interposer through electrodes (111b) passing through the second core layer,
the first interposer through electrodes are connected to the first core through electrodes (e.g. Fig. 13 teaches coupling between the package substrate 410 comprising the core through electrodes and interposer 420 comprising the interposer through electrodes. Also, all the elements of the package are either electrically connected to each other; or directly connected to each other; or indirectly connected to each other through intervening layers to form the overall package.),
the second interposer through electrodes are connected to the second core through electrodes (e.g. Fig. 13 teaches coupling between the package substrate 410 comprising the core through electrodes and interposer 420 comprising the interposer through electrodes. Also, all the elements of the package are either electrically connected to each other; or directly connected to each other; or indirectly connected to each other through intervening layers to form the overall package.),
the semiconductor package is configured to output a signal (NEG, POS in fig. 13) from the first semiconductor chip (430) and the second semiconductor chip (440) to an outside region through the first interposer through electrodes (e.g. In fig. 13, interposer 420 comprises through electrodes 423 that corresponds to interposer through electrodes of fig. 6) and the first core through electrodes (414 narrow), and
diameters of the first interposer through electrodes (112b or 113b) are greater than diameters of the second interposer through electrodes (111b). See Suwada at para. [0001] – [0183], figs. 1-19.
Further regarding claim 12,
Suwada is silent the signal is a high-speed signal.
In an analogous art, Nagamatsu teaches “In recent years, a number of specifications of high speed interfaces in which a high speed signal of some hundreds MHz, GHz band or 10 GHz in the future passes through outside of a semiconductor chip such as a package, a board or the like is increased…”, para. [0005].
Regarding claim 13:
Nagamatsu further teaches:
13. The semiconductor package of claim 12, wherein a frequency of the high-speed signal is 1 GHz or more, para. [0005].
Regarding claim 14:
Suwada teaches the diameters of the through electrodes is a result effective variable to achieve satisfactory power integrity, para. [0040], [0052], fig. 16.
It would have been obvious to one having ordinary skill in the art to form “wherein the diameters of the first interposer through electrodes are in a range of 30 μm to 80 μm”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Regarding claim 16:
Suwada further teaches:
16. The semiconductor package of claim 12, wherein the diameters of the first core through electrodes (141 narrow) are different from the diameters of the second core through electrodes (414 wide), fig. 13.
Regarding claim 18:
Suwada teaches the diameters of the through electrodes is a result effective variable to achieve satisfactory power integrity, para. [0040], [0052], fig. 16.
It would have been obvious to one having ordinary skill in the art to form “wherein the diameters of the first core through electrodes are in a range of 75 μm to 190 μm.”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Regarding claim 19:
Suwada teaches the diameters of the through electrodes is a result effective variable to achieve satisfactory power integrity, para. [0040], [0052], fig. 16.
It would have been obvious to one having ordinary skill in the art to form “wherein a diameter of each of the second core through electrodes is in a range of 75 μm to 125 μm”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Suwada with the teachings of Nagamatsu because in recent years specifications have increased for high speed signals with high operation frequency. See Nagamatsu at para. [0005].
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
18 December 2025