Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/6/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 8 is objected to because of the following informalities: “and each the first circuit layer” in lines 4-5. For the sake of compact prosecution, claim 8 is interpreted in the instant Office action as follows: “and each the first circuit layer” is found to be a typographical error and is believed to be equivalent to “and each of the first circuit layers” based on line 3; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 8 is objected to because of the following informalities: “the first circuit layer” in line 6. For the sake of compact prosecution, claim 8 is interpreted in the instant Office action as follows: “the first circuit layer” is found to be a typographical error and is believed to be equivalent to “the first circuit layers” based on line 3; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 9 is objected to because of the following informalities: “a first connection one of the substrate conductive pillars” in line 9. For the sake of compact prosecution, claim 9 is interpreted in the instant Office action as follows: “a first connection one of the substrate conductive pillars” is found to be a typographical error and is believed to be equivalent to “a first connection of one of the substrate conductive pillars”; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 9 is objected to because of the following informalities: “a second connection one of the substrate conductive pillars” in lines 10-11. For the sake of compact prosecution, claim 9 is interpreted in the instant Office action as follows: “a second connection one of the substrate conductive pillars” is found to be a typographical error and is believed to be equivalent to “a second connection of one of the substrate conductive pillars”; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 10 is objected to because of the following informalities: “the first connection one of the substrate conductive pillars” in line 7. For the sake of compact prosecution, claim 10 is interpreted in the instant Office action as follows: “the first connection one of the substrate conductive pillars” is found to be a typographical error and is believed to be equivalent to “the first connection of one of the substrate conductive pillars”; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 20 is objected to because of the following informalities: “and each the first circuit layer” in lines 4-5. For the sake of compact prosecution, claim 20 is interpreted in the instant Office action as follows: “and each the first circuit layer” is found to be a typographical error and is believed to be equivalent to “and each of the first circuit layers” based on line 3; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 20 is objected to because of the following informalities: “the first circuit layer” in line 6. For the sake of compact prosecution, claim 20 is interpreted in the instant Office action as follows: “the first circuit layer” is found to be a typographical error and is believed to be equivalent to “the first circuit layers” based on line 3; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 13 (and dependent claim 14 dependent therefrom) are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 5, “the first” in line 2 is unclear what feature is being referred to, i.e., “the first chip”, “the first substrate”, or some other first feature. For the sake of compact prosecution, claim 5 is interpreted in the instant Office action as follows: “the first” in line 2 is equivalent to “the first chip” based on Fig. 3. This interpretation is to be confirmed by applicant in next office action.
Regarding claim 13, “the first” in line 2 is unclear what feature is being referred to, i.e., “the first chip”, “the first substrate”, or some other first feature. For the sake of compact prosecution, claim 13 is interpreted in the instant Office action as follows: “the first” in line 2 is equivalent to “the first chip” based on Fig. 3. This interpretation is to be confirmed by applicant in next office action.
Regarding claim 13, “the lower surface” in line 3 is unclear which surface is being referred to. For the sake of compact prosecution, claim 13 is interpreted in the instant Office action as follows: “the lower surface” in line 3 is equivalent to “the upper surface” based on Fig. 3 and [0042] describing an interval in relation to similar surfaces consistent with the claim. This interpretation is to be confirmed by applicant in next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-14, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20210183817 A1).
Regarding claim 1, Lee discloses a semiconductor device (Fig. 1), comprising:
a first substrate (550);
a first chip (420) disposed on the first substrate (vertically on) and having a first lateral surface (See annotated figure);
and a second chip (320) disposed on the first chip and comprising a first protrusion (See annotated figure) protruding with respect to the first lateral surface (horizontally protruding);
a first substrate conductive pillar (310) connecting the first protrusion with the first substrate.
Illustrated below is a marked and annotated figure of Fig. 1 of Lee.
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Regarding claim 2, Lee discloses the semiconductor device according to claim 1 (Fig. 1), wherein the second chip has a second lateral surface (See annotated figure) and the semiconductor device comprises:
a third chip (220) disposed on the second chip (vertically on) and comprising a second protrusion (See annotated figure) protruding with respect to the second lateral surface (horizontally protruding);
and a second substrate conductive pillar (211) connecting the second protrusion with the first substrate.
Regarding claim 3, Lee discloses the semiconductor device according to claim 2 (Fig. 1), wherein the first substrate conductive pillar and the second substrate conductive pillar are different in height (different vertical heights).
Regarding claim 4, Lee discloses the semiconductor device according to claim 1 (Fig. 1), wherein the first chip comprises a dummy pad (See annotated figure), the second chip comprises a dummy bump (341D; [0041]: “dummy bump”), and the dummy bump is connected to the dummy pad (directly connected).
Regarding claim 5 as noted in the 112(b) rejection, Lee discloses the semiconductor device according to claim 1 (Fig. 1), wherein the second chip has a lower surface (320S1), the first has an upper surface (420S2), there is an interval (See annotated figure) between the lower surface and the upper surface (vertically between), and the semiconductor device further comprises: a molding compound (330) filling the interval.
Regarding claim 6, Lee discloses the semiconductor device according to claim 1 (Fig. 1), further comprising:
an interposer module (101), comprising: a second substrate ([0024]: “a core material”);
and a plurality of interposer conductive pillars (111D/112D) formed on the second substrate (vertically on), wherein each interposer conductive pillar has an end surface (See annotated figure), and the end surfaces of the interposer conductive pillars are different in height (different vertical heights);
wherein one of the interposer conductive pillars (112D) is connected to one of the first substrate, the first chip and the second chip (pillar 112D is connected to the first chip 420), and another of the interposer conductive pillars (111D) is connected to another of the first substrate, the first chip and the second chip (pillar 111D is connected to the second chip 320).
Regarding claim 8, Lee discloses the semiconductor device according to claim 1 (Fig. 1), further comprising:
an interposer module (101), comprising: a plurality of first circuit layers (one layer of a plurality; [0025]: “a plurality of wiring layers buried in the insulating layers”. Note: “a plurality of first circuit layers” is interpreted here as including both the wiring path and the insulative material burying the wiring. This interpretation is consistent with the number and arrangement of layers shown in Fig. 3 of Applicant’s disclosure);
a second circuit layer (another layer of a plurality; [0025]: “a plurality of wiring layers buried in the insulating layers”. Note: “a plurality of first circuit layers” is interpreted here as including both the wiring path and the insulative material burying the wiring. This interpretation is consistent with the number and arrangement of layers shown in Fig. 3 of Applicant’s disclosure),
wherein the second circuit layer and each the first circuit layer are respectively located in different heights (the circuit layers are described in plurality and therefore must be separate and distinct layers. These layers must be at different heights with respect to one another in at least some direction);
a plurality of conductive vias ([0025]: “a plurality of wiring via layers”) connecting the first circuit layer with the second circuit layer ([0025]: “electrically connecting the plurality of wiring layers to one another”);
and a plurality of interposer conductive pillars (111D/112D), wherein one of the interposer conductive pillars (112D) is connected with one of the first circuit layers (at least indirectly connected), and another of the interposer conductive pillars (111D) is connected with another of the first circuit layers (at least indirectly connected).
Regarding independent claim 9, Lee discloses a semiconductor device (Fig. 1), comprising:
a substrate module (a collection of subsequently cited features), comprising:
a first substrate (550);
a plurality of substrate conductive pillars (310/211) formed on the first substrate (vertically on), wherein each substrate conductive pillar has an end surface (See annotated figure), and the end surfaces of the substrate conductive pillars are different in height (different vertical heights);
a chip module (the collection of 420/320/220) having a plurality of lower surfaces (420S1/320S1/220S1), wherein the lower surfaces of the chip module are different in height (different vertical heights);
wherein a first connection one of the substrate conductive pillars (an electrical path using 310) is connected to a first one of the lower surfaces of the chip module (connected to 320S1), and a second connection one of the substrate conductive pillars (an electrical path using 211) is connected to a second one of the lower surfaces of the chip module (connected to 220S1).
Regarding claim 10, Lee discloses the semiconductor device according to claim 9 (Fig. 1), wherein the chip module comprising: a first chip (420) having a first lateral surface (See annotated figure);
a second chip (320) comprising a first protrusion (See annotated figure) protruding with respect to the first lateral surface (horizontally protruding), wherein the first protrusion has the first one of the lower surfaces (the protrusion of 320 includes a portion of surface 320S1);
wherein the first connection one of the substrate conductive pillars connects the first protrusion with the first substrate (the cited first connection uses pillar 310 to connect the protrusion of 320 to substrate 550).
Regarding claim 11, Lee discloses the semiconductor device according to claim 10 (Fig. 1), wherein the second chip has a second lateral surface (See annotated figure) and further comprises:
a third chip (220) disposed on the second chip (vertically on) and comprising a second protrusion (See annotated figure) protruding with respect to the second lateral surface (horizontally protruding), wherein the second protrusion has the second one of the lower surfaces (the protrusion of 220 includes a portion of surface 220S1);
wherein the second one of the substrate conductive pillars connects the second protrusion with the first substrate (the cited second connection uses pillar 211 to connect the protrusion of 220 to substrate 550).
Regarding claim 12, Lee discloses the memory device according to claim 10 (Fig. 1), wherein the first chip comprises a dummy pad (See annotated figure), the second chip comprises a dummy bump (341D; [0041]: “dummy bump”), and the dummy bump is connected to the dummy pad (directly connected).
Regarding claim 13 as noted in the 112(b) rejection, Lee discloses the semiconductor device according to claim 10 (Fig. 1), wherein the second chip has the first one of the lower surfaces (chip 320 has lower surface 320S1), the first chip has an upper surface (chip 420 has upper surface 420S2), there is an interval (See annotated figure) between the upper surface and the first one of the lower surfaces of the second chip (vertically between), and the semiconductor device further comprises: a molding compound (330) filling the interval.
Regarding claim 14, Lee discloses the semiconductor device according to claim 13 (Fig. 1), further comprising:
an interposer module (101), comprising: a second substrate ([0024]: “a core material”);
and a plurality of interposer conductive pillars (111D/112D) formed on the second substrate (vertically on), wherein each interposer conductive pillar has an end surface (See annotated figure), and the end surfaces of the interposer conductive pillars are different in height (different vertical heights);
wherein one of the interposer conductive pillars (112D) is connected to one of the first substrate, the first chip and the second chip (pillar 112D is connected to the first chip 420), and another of the interposer conductive pillars (111D) is connected to another of the first substrate, the first chip and the second chip (pillar 111D is connected to the second chip 320).
Regarding independent claim 16, Lee discloses a semiconductor device (Fig. 1), comprising:
a first substrate (550);
a chip module (a collection of chips 420/320/220) disposed on the first substrate (vertically on) and having a plurality of upper surfaces (420S2/320S2/220S2), wherein the surfaces of the chip module are different in height (different vertical heights);
an interposer module (101), comprising: a second substrate ([0024]: “a core material”);
and a plurality of interposer conductive pillars (111D/112D/113D) formed on the second substrate (vertically on), wherein each interposer conductive pillar has an end surface (See annotated figure), and the end surfaces of the interposer conductive pillars are different in height (different vertical heights);
wherein a first one of the interposer conductive pillars (113D) is connected to the first substrate (directly connected), and a second one of the interposer conductive pillars (112D) is connected to one of the upper surfaces of the chip module (pillar 112D is connected to upper surface 420S2).
Regarding claim 17, Lee discloses the semiconductor device according to claim 16 (Fig. 1), wherein the chip module comprising:
a first chip (420) comprising a protrusion (See annotated figure); a second chip (320) having a lateral surface (See annotated figure); wherein the protrusion of the first chip protrudes with respect to the lateral surface of the second chip (horizontally protruding), and the second one of the interposer conductive pillars is connected to the protrusion (pillar 112D is connected to the protrusion of chip 420).
Regarding claim 18, Lee discloses the semiconductor device according to claim 17 (Fig. 1), further comprising: a first substrate conductive pillar (441) connecting the first chip with the first substrate.
Regarding claim 19, Lee discloses the semiconductor device according to claim 16 (Fig. 1), further comprising: a molding compound (430/330/230/130) formed on the first substrate and encapsulating the chip module and the interposer module.
Regarding claim 20, Lee discloses the semiconductor device according to claim 16 (Fig. 1), wherein the interposer module further comprises:
a plurality of first circuit layers (one layer of a plurality; [0025]: “a plurality of wiring layers buried in the insulating layers”. Note: “a plurality of first circuit layers” is interpreted here as including both the wiring path and the insulative material burying the wiring. This interpretation is consistent with the number and arrangement of layers shown in Fig. 3 of Applicant’s disclosure);
a second circuit layer (another layer of a plurality; [0025]: “a plurality of wiring layers buried in the insulating layers”. Note: “a plurality of first circuit layers” is interpreted here as including both the wiring path and the insulative material burying the wiring. This interpretation is consistent with the number and arrangement of layers shown in Fig. 3 of Applicant’s disclosure),
wherein the second circuit layer and each the first circuit layer are respectively located in different heights (the circuit layers are described in plurality and therefore must be separate and distinct layers. These layers must be at different heights with respect to one another in at least some direction);
a plurality of conductive vias ([0025]: “a plurality of wiring via layers”) connecting the first circuit layer with the second circuit layer ([0025]: “electrically connecting the plurality of wiring layers to one another”);
wherein one of the interposer conductive pillars (112D) is connected with one of the first circuit layers (at least indirectly connected), and another of the interposer conductive pillars (111D) is connected with another of the first circuit layers (at least indirectly connected).
Claims 1, 7, 9, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoo (US 20190067248 A1).
Regarding claim 1, Yoo discloses a semiconductor device (Fig. 3A), comprising:
a first substrate (330);
a first chip (310) disposed on the first substrate (vertically on) and having a first lateral surface (See annotated figure);
and a second chip (320) disposed on the first chip (vertically on) and comprising a first protrusion (324) protruding with respect to the first lateral surface (horizontally protruding);
a first substrate conductive pillar (306) connecting the first protrusion with the first substrate.
Illustrated below is a marked and annotated figure of Fig. 3A of Yoo.
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Regarding claim 7, Yoo discloses the semiconductor device according to claim 1 (Fig. 3A), further comprising: a metal wire (304) connecting the first substrate with the first chip.
Regarding independent claim 9, Yoo discloses a semiconductor device (Fig. 3A), comprising:
a substrate module (a collection of subsequently cited features), comprising:
a first substrate (330);
a plurality of substrate conductive pillars (306/376) formed on the first substrate (vertically on), wherein each substrate conductive pillar has an end surface (See annotated figure), and the end surfaces of the substrate conductive pillars are different in height (different vertical heights);
a chip module (the collection of 310/320/360/370) having a plurality of lower surfaces (313b/323b/363b/373b), wherein the lower surfaces of the chip module are different in height (different vertical heights);
wherein a first connection one of the substrate conductive pillars (the connection of pillar 306) is connected to a first one of the lower surfaces of the chip module (pillar 306 is connected to lower surface 323b), and a second connection one of the substrate conductive pillars (the connection of pillar 376) is connected to a second one of the lower surfaces of the chip module (pillar 376 is connected to lower surface 373b).
Regarding claim 15, Yoo discloses the semiconductor device according to claim 9 (Fig. 3A), further comprising: a metal wire (304) connecting the first substrate with the first chip.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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