Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the invent or or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 18, “ wherein the first substrate conductive pillar connects the first chip with the substrate ” in line s 1-3 is unclear . More specifically, claim 16 establishes this pillar is configured with the second chip (Claim 16: line 15: “a second chip disposed on the first chip, comprising a first protrusion”; and line 20: “a first substrate conductive pillar connecting the first protrusion with the first substrate”) . It is unclear how this pillar can simultaneously connect to 1) the first protrusion of the second chip, 2) the first substrate, and 3) the first chip. For the sake of compact prosecution, claim 18 is interpreted in the instant Office action consistent with the original disclosure, as follows: “ wherein the first substrate conductive pillar connects the first chip with the substrate ” in lines 1-3 is equivalent to “wherein the first substrate conductive pillar connects the second chip with the substrate” . This interpretation is to be confirmed by applicant in next office action. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1 , 3-5 , 9-1 3 , 21 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Oh ( US 20200075551 A1 ). Regarding claim 1, Oh discloses a semiconductor device (Fig. 22) , comprising: a first substrate (1) ; a first chip ( 3, See annotated figure ) disposed on the first substrate and having a first lateral surface ( See annotated figure ) ; a second chip ( 3, See annotated figure ) disposed on the first chip, comprising a first protrusion ( See annotated figure ) protruding with respect to the first lateral surface ( protruding in the D2 direction ) and having a second lateral surface ( See annotated figure ) ; a third chip ( 3, See annotated figure ) disposed on the second chip and comprising a second protrusion ( See annotated figure ) protruding with respect to the second lateral surface ( protruding in the D2 direction ) ; a first substrate conductive pillar ( 51´ ) connecting the first protrusion with the first substrate ( electrically connecting ) ; a second substrate conductive pillar ( 52´ ) connecting the second protrusion with the first substrate ( electrically connecting ) ; and a single molding compound ( 7 ) encapsulating the first substrate ( encapsulating the D1 surface ) , the second chip ( fully encapsulating ) , the third chip ( fully encapsulating ) , the first substrate conductive pillar ( fully encapsulating ) and the second substrate conductive pillar ( fully encapsulating ) ; wherein the second substrate conductive pillar is a single pillar ( the pillar is shown as a single piece ) which continuously extends to the first substrate from the third chip ( there are no interruptions in the pillar, thus it “continuously extends” ) . Illustrated below is a marked and annotated figure of Fig. 22 of Oh. Regarding claim 3, Oh discloses the semiconductor device according to claim 1 ( Fig. 22 ) , wherein the first substrate conductive pillar and the second substrate conductive pillar are different in height ( different total D1 heights are shown ) . Regarding claim 4, Oh discloses the semiconductor device according to claim 1 (Fig. 22) , wherein the first chip comprises a dummy pad ( a point of direct contact, thus a “pad” ; [0072]: “ need not serve to electrically connect the second semiconductor chip 32 to the substrate ”, thus a dummy pad; See annotated figure ) , the second chip comprises a dummy bump ( 323a, similarly shown in Fig. 8 ) , and the dummy bump is connected to the dummy pad ( directly connected ) . Regarding claim 5, Oh discloses the semiconductor device according to claim 1 ( Fig. 22 ) , wherein the second chip has a lower surface ( See annotated figure ) , the first chip has an upper surface ( See annotated figure ) , there is an interval ( See annotated figure ) between the lower surface and the upper surface ( between in the D1 direction ) , and the single molding compound fills the interval ( completely fills ) . Illustrated below is a marked and annotated figure of Fig. 22 of Oh. Regarding claim 21, Oh discloses the semiconductor device according to claim 1 (Fig. 22) , wherein the semiconductor device further comprises: an adhesive layer ( 9, similarly shown in Fig. 8 ) entirely disposed between an overlap region of the first chip and the second chip ( overlap in the D1 direction ) . Regarding independent claim 9, Oh discloses a semiconductor device (Fig. 22) , comprising: a substrate module ( a collection further cited below ) , comprising: a first substrate (1) ; a plurality of substrate conductive pillars ( 50 ) formed on the first substrate ([0116]: “extension conductor formation step S″ ″ 12” ) , wherein each substrate conductive pillar has an end surface ( See annotated figure ) , and the end surfaces of the substrate conductive pillars are different in height ( different total D1 heights are shown ) ; a chip module ( a collection of chips 3 ) having a plurality of lower surfaces ( See annotated figure ) , wherein the lower surfaces of the chip module are different in height ( different D1 heights are shown ) ; and a single molding compound ( 7 ) encapsulating the chip module ( fully encapsulating ) and the substrate conductive pillars ( fully encapsulating ) ; wherein a first connection of one of the substrate conductive pillars ( 51´ ) is connected ( electrically connected ) to a first one of the lower surfaces of the chip module ( lower surface of the 2 nd chip ) , and a second connection of one of the substrate conductive pillars ( 52´ ) is connected ( electrically connected ) to a second one of the lower surfaces of the chip module ( lower surface of the 3 rd chip ) ; wherein each of the substrate conductive pillars is single pillar ( the pillars are shown as a single piece ) which continuously extends to the first substrate from the chip module ( there are no interruptions in the pillars, thus each “continuously extends” ) . Regarding claim 10, Oh discloses the semiconductor device according to claim 9 (Fig. 22) , wherein the chip module comprising: a first chip ( 3, See annotated figure ) having a first lateral surface ( 3, See annotated figure ) ; a second chip ( 3, See annotated figure ) comprising a first protrusion ( 3, See annotated figure ) protruding with respect to the first lateral surface ( protruding in the D2 direction ) , wherein the first protrusion has the first one of the lower surfaces ( a portion of the lower surface ) ; wherein the first connection of one of the substrate conductive pillars connects the first protrusion with the first substrate ( electrically connects ) . Regarding claim 11, Oh discloses the semiconductor device according to claim 10 (Fig. 22) , wherein the second chip has a second lateral surface ( See annotated figure ) and further comprises: a third chip ( 3, See annotated figure ) disposed on the second chip and comprising a second protrusion ( See annotated figure ) protruding with respect to the second lateral surface ( protruding in the D2 direction ) , wherein the second protrusion has the second one of the lower surfaces ( a portion of the lower surface ) ; wherein the second one of the substrate conductive pillars connects the second protrusion with the first substrate ( electrically connects ) . Regarding claim 12, Oh discloses the memory device according to claim 10 (Fig. 22) , wherein the first chip comprises a dummy pad ( a point of direct contact, thus a “pad” ; [0072]: “ need not serve to electrically connect the second semiconductor chip 32 to the substrate ”, thus a dummy pad; See annotated figure ) , the second chip comprises a dummy bump ( 323a, similarly shown in Fig. 8 ) , and the dummy bump is connected to the dummy pad ( directly connected ) . Regarding claim 13, Oh discloses the semiconductor device according to claim 10 (Fig. 22) , wherein the second chip has the first one of the lower surfaces ( See annotated figure ) , the first chip has an upper surface ( See annotated figure ) , there is an interval ( See annotated figure ) between the upper surface and the first one of the lower surfaces ( between in the D1 direction ) , and the molding compound fills the interval ( completely fills ) . Claim s 1 , 7 , 9, and 15 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yoo ( US 20190067248 A1 ). Regarding claim 1, Yoo discloses a semiconductor device ( Fig. 3A ) , comprising: a first substrate ( 330 ) ; a first chip ( 310 ) disposed on the first substrate ( vertically on ) and having a first lateral surface ( See annotated figure ) ; a second chip ( 320 ) disposed on the first chip ( vertically on ) , comprising a first protrusion ( See annotated figure ) protruding with respect to the first lateral surface ( protruding horizontally ) and having a second lateral surface ( See annotated figure ) ; a third chip ( 370 ) disposed on the second chip ( vertically on ) and comprising a second protrusion ( See annotated figure ) protruding with respect to the second lateral surface ( protruding horizontally ) ; a first substrate conductive pillar ( 306 ) connecting the first protrusion with the first substrate ( electrically connecting ) ; a second substrate conductive pillar ( 376 ) connecting the second protrusion with the first substrate ( electrically connecting ) ; and a single molding compound ( 346 ) encapsulating the first substrate ( encapsulating the vertically facing surface ) , the second chip ( fully encapsulating ) , the third chip ( horizontally encapsulating ) , the first substrate conductive pillar ( fully encapsulating ) and the second substrate conductive pillar ( fully encapsulating ) ; wherein the second substrate conductive pillar is a single pillar ( the pillar is shown as a single piece ) which continuously extends to the first substrate from the third chip ( there are no interruptions in the pillar, thus it “continuously extends” ) . Illustrated below is a marked and annotated figure of Fig. 3A of Yoo. Regarding claim 7, Yoo discloses the semiconductor device according to claim 1 (Fig. 3A) , further comprising: a metal wire ( 304 ) connecting the first substrate with the first chip (electrically connecting) . Regarding independent claim 9, Yoo discloses a semiconductor device (Fig. 3A ) , comprising: a substrate module ( a collection further cited below ) , comprising: a first substrate ( 330 ) ; a plurality of substrate conductive pillars formed on the first substrate ( 306, 376 ) , wherein each substrate conductive pillar has an end surface ( See annotated figure ) , and the end surfaces of the substrate conductive pillars are different in height ( different total vertical heights are shown ) ; a chip module ( a collection of chips 310, 320, 370 ) havi ng a plurality of lower surfaces (313b, 323b, 373b) , wh erein the lower surfaces of the chip module are different in height ( different vertical heights are shown ) ; and a single molding compound ( 346 ) encapsulating the chip module ( at least partially encapsulating ) and the substrate conductive pillars ( fully encapsulating ) ; wherein a first connection of one of the substrate conductive pillars ( 306 ) is connected ( electrically connected ) to a first one of the lower surfaces of the chip module ( 323b at 322 ) , and a second connection of one of the substrate conductive pillars ( 376 ) is connected ( electrically connected ) to a second one of the lower surfaces of the chip module ( 373b at 372 ) ; wherein each of the substrate conductive pillars is single pillar ( the pillars are shown as a single piece ) which continuously extends to the first substrate from the chip module ( there are no interruptions in the pillars, thus each “continuously extends” ) . Regarding claim 15, Yoo discloses the semiconductor device according to claim 9 (Fig. 3A) , further comprising: a metal wire ( 304 ) connecting the first substrate with the first chip (electrically connecting) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s). Claim s 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Oh as applied to claim 1 above, and further in view of Lee ( US 20210183817 A1 ) . Regarding claim 6, Oh discloses the semiconductor device according to claim 1 (Fig. 22) , but fails to teach it “further comprising: an interposer module , comprising: a second substrate; and a plurality of interposer conductive pillars formed on the second substrate, wherein each of the interposer conductive pillars has an end surface, and the end surfaces of the interposer conductive pillars are different in height; wherein one of the interposer conductive pillars is connected to one of the first substrate, the first chip and the second chip, and another of the interposer conductive pillars is connected to another of the first substrate, the first chip and the second chip” . Lee discloses a semiconductor device ( Fig. 1 ) further comprising: an interposer module (101) , comprising: a second substrate ([0024]: “a core material”) ; and a plurality of interposer conductive pillars (110) formed on the second substrate, wherein each of the interposer conductive pillars has an end surface ( See annotated figure) , and the end surfaces of the interposer conductive pillars are different in height (different in the vertical direction) ; wherein one of the interposer conductive pillars is connected to one of the first substrate (connected to first substrate 550, See “end surfaces” in annotated figure) , the first chip and the second chip, and another of the interposer conductive pillars is connected to another of the first substrate, the first chip and the second chip (connected to second chip 320, See “end surfaces” in annotated figure) . Modifying the semiconductor device of Oh by including the interposer module of Lee would arrive at the claimed device configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, pillars and chips are connected to a substate in the same spatial orientation ( Oh: Fig. 22: pillars 50 and chips 3; Lee: Fig. 1: pillars 110 and chips 420/320/220 ) . Lee provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the interposer module in that it would increase strength of the device ( [0026]: “ may improve stiffness of the semiconductor package ” ) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed interposer module because it would increase strength of the device. MPEP 2143 (I)(G). Illustrated below is a marked and annotated figure of Fig. 1 of Lee. Regarding claim 8, Oh discloses the semiconductor device according to claim 1 (Fig. 22) , but fails to teach it “further comprising: an interposer module , comprising: a plurality of first circuit layers; a second circuit layer, wherein the second circuit layer and each of the first circuit layers are respectively located in different heights; a plurality of conductive vias connecting the first circuit layers with the second circuit layer; and a plurality of interposer conductive pillars, wherein one of the interposer conductive pillars is connected with one of the first circuit layers, and another of the interposer conductive pillars is connected with another of the first circuit layers” . Lee discloses a semiconductor device (Fig. 1) , further comprising: an interposer module (101) , comprising: a plurality of first circuit layers ( some of this plurality, [0025]: “ a plurality of wiring layers buried in the insulating layers ”. Note: Lee does not teach a specific number of wiring layers, but the examiner finds “a plurality” reasonably includes at least 3 wiring layers ) ; a second circuit layer ( another of this plurality, [0025]: “ a plurality of wiring layers buried in the insulating layers ”. Note: Lee does not teach a specific number of wiring layers, but the examiner finds “a plurality” reasonably includes at least 3 wiring layers ) , wherein the second circuit layer and each of the first circuit layers are respectively located in different heights ( Lee teaches these as separate layers, thus they must have different heights as measured in whatever direction they were formed ) ; a plurality of conductive vias ( [0025]: “ a plurality of wiring via layers ” ) connecting the first circuit layers with the second circuit layer ( [0025]: “ electrically connecting the plurality of wiring layers to one another ” ) ; and a plurality of interposer conductive pillars ( 110 ) , wherein one of the interposer conductive pillars is connected with one of the first circuit layers ( at least indirectly connected ) , and another of the interposer conductive pillars is connected with another of the first circuit layers ( at least indirectly connected ) . Modifying the semiconductor device of Oh by including the interposer module of Lee would arrive at the claimed device configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, pillars and chips are connected to a substate in the same spatial orientation (Oh: Fig. 22: pillars 50 and chips 3; Lee: Fig. 1: pillars 110 and chips 420/320/220) . Lee provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the interposer module in that it would increase strength of the device ([0026]: “may improve stiffness of the semiconductor package”) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed interposer module because it would increase strength of the device. MPEP 2143 (I)(G). Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Oh as applied to claim 13 above, and further in view of Lee . Regarding claim 14, Oh discloses the semiconductor device according to claim 13 ( Fig. 22 ) , but fails to teach it “further com prising: an interposer module , comprising: a second substrate; and a plurality of interposer conductive pillars formed on the second substrate, wherein each interposer conductive pillar has an end surface, and the end surfaces of the interposer conductive pillars are different in height; wherein one of the interposer conductive pillars is connected to one of the first substrate, the first chip and the second chip, and another of the interposer conductive pillars is connected to another of the first substrate, the first chip and the second chip ” . Lee discloses a semiconductor device ( Fig. 1 ) , further comprising: an interposer module (101) , comprising: a second substrate ([0024]: “a core material”) ; and a plurality of interposer conductive pillars (110) formed on the second substrate, wherein each interposer conductive pillar has an end surface ( See annotated figure) , and the end surfaces of the interposer conductive pillars are different in height (different in the vertical direction) ; wherein one of the interposer conductive pillars is connected to one of the first substrate (connected to first substrate 550, See “end surfaces” in annotated figure) , the first chip and the second chip, and another of the interposer conductive pillars is connected to another of the first substrate, the first chip and the second chip (connected to second chip 320, See “end surfaces” in annotated figure) . Modifying the semiconductor device of Oh by including the interposer module of Lee would arrive at the claimed device configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, pillars and chips are connected to a substate in the same spatial orientation (Oh: Fig. 22: pillars 50 and chips 3; Lee: Fig. 1: pillars 110 and chips 420/320/220) . Lee provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the interposer module in that it would increase strength of the device ([0026]: “may improve stiffness of the semiconductor package”) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed interposer module because it would increase strength of the device. MPEP 2143 (I)(G). Claim s 16 and 18- 20 are rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Lee . Regarding independent claim 16, Oh discloses a semiconductor device (Fig. 22) , comprising: a first substrate (1) ; a chip module (a collection of chips 3) disposed on the first substrate and having a plurality of upper surfaces ( See annotated figure) , wherein the surfaces of the chip module are different in height (different D1 heights are shown) ; an interposer module, comprising: a second substrate; and a plurality of interposer conductive pillars formed on the second substrate, wherein each interposer conductive pillar has an end surface, and the end surfaces of the interposer conductive pillars are different in height; wherein a first one of the interposer conductive pillars is connected to the first substrate, and a second one of the interposer conductive pillars is connected to one of the upper surfaces of the chip module; wherein the chip module comprises: a first chip ( 3, See annotated figure ) disposed on the first substrate and having a first lateral surface ( See annotated figure ) ; a second chip ( 3, See annotated figure ) disposed on the first chip, comprising a first protrusion ( See annotated figure ) protruding with respect to the first lateral surface ( protruding in the D2 direction ) and having a second lateral surface ( See annotated figure ) ; and a third chip ( 3, See annotated figure ) disposed on the second chip and comprising a second protrusion ( See annotated figure ) protruding with respect to the second lateral surface ( protruding in the D2 direction ) ; wherein the semiconductor device further comprises: a first substrate conductive pillar ( 51´ ) connecting the first protrusion with the first substrate ( electrically connecting ) ; a second substrate conductive pillar ( 52´ ) connecting the second protrusion with the first substrate ( electrically connecting ) ; and a single molding compound ( 7 ) encapsulating the first substrate ( encapsulating the D1 surface ) , the second chip ( fully encapsulating ) , the third chip ( fully encapsulating ) , the first substrate conductive pillar ( fully encapsulating ) , the second substrate conductive pillar ( fully encapsulating ) and the interposer module ; wherein a prominent part of the first chip protrudes with respect to a side of the second chip ( protrudes in the opposite D2 direction ) , and the second one of the interposer conductive pillars is connected to the prominent part ; wherein the second substrate conductive pillar is a single pillar ( the pillar is shown as a single piece ) which continuously extends to the first substrate from the third chip ( there are no interruptions in the pillar, thus it “continuously extends” ) . Oh teaches a chip module, substrate conductive pillars, and a single molding compound, but fails to teach including an interposer module. Thus, Oh fails to teach “ an interposer module , comprising: a second substrate ; and a plurality of interposer conductive pillars formed on the second substrate, wherein each interposer conductive pillar has an end surface , and the end surfaces of the interposer conductive pillars are different in height ; wherein a first one of the interposer conductive pillars is connected to the first substrate, and a second one of the interposer conductive pillars is connected to one of the upper surfaces of the chip module; wherein the chip module comprises: a first chip disposed on the first substrate and having a first lateral surface; a second chip disposed on the first chip, comprising a first protrusion protruding with respect to the first lateral surface and having a second lateral surface; and a third chip disposed on the second chip and comprising a second protrusion protruding with respect to the second lateral surface; wherein the semiconductor device further comprises: a first substrate conductive pillar connecting the first protrusion with the first substrate; a second substrate conductive pillar connecting the second protrusion with the first substrate; and a single molding compound encapsulating the first substrate, the second chip, the third chip, the first substrate conductive pillar, the second substrate conductive pillar and the interposer module ; wherein a prominent part of the first chip protrudes with respect to a side of the second chip, and the second one of the interposer conductive pillars is connected to the prominent part ” . Lee teaches a semiconductor device (Fig. 1) , comprising: an interposer module (101) , comprising: a second substrate ([0024]: “a core material”) ; and a plurality of interposer conductive pillars (110 , includes 112D ) formed on the second substrate, wherein each interposer conductive pillar has an end surface ( See annotated figure) , and the end surfaces of the interposer conductive pillars are different in height (different in the vertical direction) ; wherein a first one of the interposer conductive pillars is connected to the first substrate (connected to first substrate 550, See “end surfaces” in annotated figure) , and a second one of the interposer conductive pillars ( 112D, the one selected in the annotated figure ) is connected to one of the upper surfaces of the chip module (connected to first chip 4 20, See “end surfaces” in annotated figure) ; wherein the chip module comprises: a first chip ( 420 ) disposed on the first substrate and having a first lateral surface; a second chip ( 320 ) disposed on the first chip, comprising a first protrusion protruding with respect to the first lateral surface and having a second lateral surface; and a third chip (220) disposed on the second chip and comprising a second protrusion protruding with respect to the second lateral surface; wherein the semiconductor device further comprises: a first substrate conductive pillar ( 310 ) connecting the first protrusion with the first substrate; a second substrate conductive pillar ( 211 ) connecting the second protrusion with the first substrate; and a single molding compound encapsulating the first substrate, the second chip, the third chip, the first substrate conductive pillar, the second substrate conductive pillar and the interposer module ; wherein a prominent part of the first chip ( See annotated figure ) protrudes with respect to a side of the second chip ( protrudes in the horizontal direction ) , and the second one of the interposer conductive pillars is connected to the prominent part ( at least physically connected ) . Modifying the semiconductor device of Oh by including the interposer module of Lee would arrive at the claimed device configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, pillars and chips are connected to a substate in the same spatial orientation (Oh: Fig. 22: pillars 50 and chips 3; Lee: Fig. 1: pillars 110 and chips 420/320/220) . Lee provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the interposer module in that it would increase strength of the device ([0026]: “may improve stiffness of the semiconductor package”) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed interposer module because it would increase strength of the device. MPEP 2143 (I)(G). Regarding claim 18 as noted in the 112(b) rejection, Oh in view of Lee discloses the semiconductor device according to claim 16 ( Oh: Fig. 22 ) , wherein the first substrate conductive pillar connects the second chip with the first substrate ( electrically connects ) . Regarding claim 19, Oh in view of Lee discloses the semiconductor device according to claim 16 ( Oh: Fig. 22 ) , wherein the molding compound is formed on the first substrate ( directly on ) and encapsulates the chip module ( horizontally and vertically encapsulates ) and the interposer module ( the single molding compound configuration of Oh is incorporated in the same way to the combination of Oh with Lee ) . Regarding claim 20, Oh in view of Lee discloses the semiconductor device according to claim 16 ( Lee: Fig. 1 ) , wherein the interposer module further comprises: a plurality of first circuit layers ( some of this plurality, [0025]: “ a plurality of wiring layers buried in the insulating layers ”. Note: Lee does not teach a specific number of wiring layers, but the examiner finds “a plurality” reasonably includes at least 3 wiring layers ) ; a second circuit layer ( another of this plurality, [0025]: “ a plurality of wiring layers buried in the insulating layers ”. Note: Lee does not teach a specific number of wiring layers, but the examiner finds “a plurality” reasonably includes at least 3 wiring layers ) , wherein the second circuit layer and each of the first circuit layers are respectively located in different heights ( Lee teaches these as separate layers, thus they must have different heights as measured in whatever direction they were formed ) ; a plurality of conductive vias ( [0025]: “ a plurality of wiring via layers ” ) connecting the first circuit layers with the second circuit layer ( [0025]: “ electrically connecting the plurality of wiring layers to one another ” ) ; wherein one of the interposer conductive pillars is connected with one of the first circuit layers ( at least indirectly connected ) , and another of the interposer conductive pillars is connected with another of the first circuit layers ( at least indirectly connected ) . Response to Arguments Applicant's arguments filed 2/19/2026 have been fully considered but they are not persuasive. Applicant argues: Applicant argues with respect to amended claim 1 that “Lee does not discloses “single molding compound encapsulating the first substrate, the second chip, the third chip, the first substrate conductive pillar and the second substrate conductive pillar”, as recited in amended claim 1” . Remarks at pg. 12. Examiner’s reply: Applicant’s arguments with respect to claim (s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendments change the scope of the claims, thus necessitating the new grounds of rejection raised in the instant Office action. Applicant argues: Applicant argues with respect to amended claim 1 that “ Lee does not disclose that “the second substrate conductive pillar is a single pillar which continuously extends to the first substrate from the third chip”, as recited in amended claim 1 ” . Remarks at pg. 13. Examiner’s reply: Applicant’s arguments with respect to claim (s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendments change the scope of the claims, thus necessitating the new grounds of rejection raised in the instant Office action. Applicant argues: Applicant argues “The amendment of claim 9 is similar to that of amended claim 1, and the remarks are similar to that of amended claim 1. Accordingly, claim 9 (and its dependent claims) should be allowed for the same reasons as claim 1” . Remarks at pg. 14 Examiner’s reply: Applicant’s arguments with respect to claim (s) 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendments change the scope of the claims, thus necessitating the new grounds of rejection raised in the instant Office action. Applicant argues: Applicant argues “ The amendment of claim 16 is similar to that of amended claim 1, and the remarks are similar to that of amended claim 1. Accordingly, claim 17 (and its dependent claims) should be allowed for the same reasons as claim 1 ” . Remarks at pg. 14 Examiner’s reply: Applicant’s arguments with respect to claim (s) 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendments change the scope of the claims, thus necessitating the new grounds of rejection raised in the instant Office action. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT WILLIAM H ANDERSON whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-2534 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday, 8:00-5:00 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Kretelia Graham can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-5055 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM H ANDERSON/ Examiner, Art Unit 2817 /Kretelia Graham/ Supervisory Patent Examiner, Art Unit 2817 March 9, 2026