DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-6, 8-15 & 17-20 in the reply filed on 12/17/2025 is acknowledged.
Claim Objections
Claim 20 is objected to because of the following informalities: claim 20 recites “a second platform means providing a second set of elevated electrical contacts …” in line 8. There appears to be a typographical error as the term “for” between “means” and “providing” is missing. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim 20:
a semiconductor device package comprising:
a substrate means for providing electrical interconnections between electrical components coupled to the substrate means;
a first platform means for providing a first set of elevated electrical contacts spaced away from the substrate means, the first platform means include a first conduction means extending through the first platform means for electrically connecting the first set of elevated electrical contacts to the substrate means;
a second platform means providing a second set of elevated electrical contacts spaced away from the substrate means, the second platform means including a second conduction means extending through the second platform means for electrically connecting the second set of elevated contacts to the substrate means; and
a stack of storage means each for storing an amount of data, the stack of storage means positioned on the substrate means between the first platform means and the second platform means, the stack of storage means including a first storage means electrically connected to the first set of elevated electrical contacts, and a second storage means electrically connected to the second set of elevated electrical contacts (note bolded portions).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim terms like substrate, platform, connection and storage, are generic in the art to provide sufficient structure, material, or acts for performing the claimed function. There is insufficient support for the limitations “a substrate means for providing the electrical interconnections”, “a first platform means for providing a first set of elevated electrical contacts”, “a first conduction means for electrically connecting the first set of elevated electrical contacts”, “a second platform means [for] providing a second set of elevated electrical contacts”, “a second conduction means….. for electrically connecting the second set of elevated contacts”, and “a stack of storage means.. for storing an amount of data in the specification to ascertain the equivalent structures for means plus function claim interpretation.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitations “a substrate means for providing the electrical interconnections”, “a first platform means for providing a first set of elevated electrical contacts”, “a first conduction means for electrically connecting the first set of elevated electrical contacts”, “a second platform means [for] providing a second set of elevated electrical contacts”, “a second conduction means….. for electrically connecting the second set of elevated contacts”, “a stack of storage means.. for storing an amount of data”,. Said limitations are indefinite as the metes and bounds of the claim are unclear. In other words, said limitations raises ambiguity as applicants have failed to describe what structural features they refer to. Correction/clarification is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8-13, 14-15, 17 & 19 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Boo et al. (US Pub. 2023/0069476).
Regarding claim 1, Boo teaches a semiconductor device package comprising:
a substrate 102 (Fig. 6);
a stack of semiconductor dies 110 positioned on the substrate 102 and including a first semiconductor die and a second semiconductor die (see Fig. 6);
a first platform (620a or 620b) positioned on the substrate 102 (Fig. 6);
a second platform (620b or 620a) positioned on the substrate 102 opposite the first platform 620a such that the stack of semiconductor dies 110 is positioned between the first and second platforms (see Fig. 6);
a first through-via (one of the vias in 620b passing through the multiple elevations, see Fig. 5-7) electrically connected to the substrate 102 and extending through the first platform 620a;
a second through-via (one of the vias in 620a passing through the multiple elevations, see Fig. 5-7) electrically connected to the substrate 102 and extending through the second platform 620b;
a first bond wire (bond wire on the left) electrically connecting the first through-via to the first semiconductor die; and
a second bond wire (bond wire on the right) electrically connecting the second through-via to the second semiconductor die (see Fig. 6 and respective text, also see Fig. 5 & Fig. 7).
Regarding claim 2, Boo teaches the semiconductor device package of claim 1, wherein the first platform 620b includes a first stepped surface E2, a second stepped surface E3 vertically offset from the first stepped surface, and a first bond pad exposed at the first stepped surface and electrically connected to the first through-via, and wherein the first through-via extends through the first platform 620b from the first bond pad to the substrate 102 (Fig. 6, also see Fig. 4A-4C & Fig. 5 and note the pad formations on the stepped surfaces).
Regarding claim 3, Boo teaches the semiconductor device package of claim 2, wherein the first platform 620b includes a second bond pad exposed at the second stepped surface E2, and a third through-via electrically connected to the substrate 102 and the second bond pad, and wherein the third through-via extends through the first platform 620b from the second bond pad to the substrate 102 (Fig. 4C & Fig. 5-6 and respective texts).
Regarding claim 4, Boo teaches the semiconductor device package of claim 3 further comprising: a third semiconductor die included in the stack of semiconductor dies 110, the third semiconductor die positioned above the first and second semiconductor dies; and a third bond wire electrically connecting the third semiconductor die to the third through-via (see Fig. 6).
Regarding claim 5, Boo teaches the semiconductor device package of claim 4, wherein at least a portion of the third bond wire is positioned vertically above the first bond wire and does not directly contact the first bond wire (Fig. 5 7 Fig. 6).
Regarding claim 6, Boo teaches the semiconductor device package of claim 1, wherein the first and second platforms (620a & 620b) include a series of sections stacked one on top of another, each section comprising a conductive layer and a dielectric layer (Fig. 6 & Fig. 4A-4C and respective texts).
Regarding claim 8, Boo teaches the semiconductor device package of claim 1, wherein the first platform 620a has a total height that is greater than the second platform 620b (Fig. 6).
Regarding claim 9, Boo teaches the semiconductor device package of claim 1, wherein the first platform 620a and second platform 620b are comprised of a material the same as the substrate (package substrates are understood to comprise organic laminate and Boo teaches organic laminate for the first and second platforms in Para [0041], also see Fig. 1A & Fig. 6)Fig. 6).
Regarding claim 10, Boo teaches the semiconductor device package of claim 1, wherein the stack of semiconductor dies 110 comprise memory dies (Fig. 6 & Para [0026]).
Regarding claim 11, Boo teaches the semiconductor device package of claim 1, further comprising: a substrate bond pad electrically connected to the substrate 102 and positioned between the stack of semiconductor dies 110 and the first platform; and a bond wire electrically connecting the substrate bond pad to a bottom most semiconductor die included in the stack of semiconductor dies (e.g. see Fig. 1A).
Regarding claim 12, Boo teaches the semiconductor device package of claim 1, wherein the first bond wire is electrically connected to the first semiconductor die and another semiconductor die adjacent to the first semiconductor die (Fig. 6).
Regarding claim 13, Boo teaches the semiconductor device package of claim 1, wherein the first bond wire is electrically connected to the first semiconductor die and at least two adjacent semiconductor dies (Fig. 6).
Regarding claim 14, Boo teaches a semiconductor memory package comprising:
a substrate 102 including a top surface and a bond pad exposed at the top surface (Fig. 6 & Fig. 1A);
a stack of semiconductor dies 110 positioned on the top surface of the substrate 102 (Fig. 6);
a first platform 620a/120b positioned on the top surface of the substrate 102, the first platform including a plurality of through-vias (note the unlabeled vias in 620a and/or through vias 426 in Fig. 4A-4B) electrically connected to the substrate 102 and extending through the first platform 620a/120b (Fig. 6 & Fig. 1A);
a second platform 620b/120a positioned on the top surface of the substrate 102 opposite the first platform such that the stack of semiconductor dies 110 is positioned between the first and second platforms, the second platform including a plurality of through-vias (note the unlabeled vias in 620b and/or through vias 426 in Fig. 4A-4B)electrically connected to the substrate and extending through the second platform 620b/120a (Fig. 6 & Fig. 1A); and
a first bond wire connecting a first semiconductor die of the stack to the at least one through- via of the first platform 620a/b or 120a/b, and a second bond wire connecting a second semiconductor die of the stack to the at least one through-via of the second platform 620b/120a (Fig. 6 & Fig. 1A).
Regarding claim 15, Boo teaches the semiconductor device package of claim 14, wherein the first platform 620a/120b includes at least two stepped surfaces vertically offset from one another (note the two elevations), each of the stepped surfaces including a bond pad electrically connected to one or more of the plurality of through-vias of the first platform 620a/120b (Fig. 6 & Fig. 1A).
Regarding claim 17, Boo teaches the semiconductor device package of claim 14, wherein the first and second platforms (620a/120b & 620b/120a) include a series of sections stacked one on top of another, each section comprising a conductive layer and a dielectric layer (Fig. 6, 1A and Fig. 4A-4C and respective texts).
Regarding claim 19, Boo teaches the semiconductor device package of claim 14, wherein the first platform and second platform are comprised of a material the same as the substrate (package substrates are understood to comprise organic laminate and Boo teaches organic laminate for the first and second platforms in Para [0041], also see Fig. 1A & Fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Boo as applied to claim 14 above and in further view of YEE et al. (US Pub. 2014/0339706).
Regarding claim 18, Boo is silent on the semiconductor device package of claim 14, wherein each through-via of the plurality of through-vias has a diameter of about 10 microns. However, YEE discloses in Para [0027] a semiconductor device comprising a plurality of through-vias, wherein each via of the plurality of through-vias has a diameter of about 10 microns. This claim dimension would have been obvious to one of the ordinary skill in the art in view of Boo and YEE. One of the ordinary skill in the art is motivated to form device features as small as possible with large enough thickness to allow proper device operation, in order to save on material and processing costs. As such, it would have been obvious to use a diameter of about 10 um for the through-via.
The claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955)(selection of optimum ranges within prior art general conditions is obvious).
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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