DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8-13, 14-15, 17 & 19 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Boo et al. (US Pub. 2023/0069476).
Regarding claim 1, Boo teaches a semiconductor device package comprising:
a substrate 102 (Fig. 6);
a stack of semiconductor dies 110 positioned on the substrate 102 and including a first semiconductor die and a second semiconductor die (see Fig. 6);
a first platform (620a or 620b) positioned on the substrate 102 (Fig. 6);
a second platform (620b or 620a) positioned on the substrate 102 opposite the first platform 620a such that the stack of semiconductor dies 110 is positioned between the first and second platforms (see Fig. 6);
a first through-via (one of the vias in 620b passing through the multiple elevations, see Fig. 5-7) electrically connected to the substrate 102 and extending through the first platform 620a (Fig. 6);
a second through-via (one of the vias in 620a passing through the multiple elevations, see Fig. 5-7) electrically connected to the substrate 102 and extending through the second platform 620b (Fig. 6);
a first bond wire (bond wire on the left) electrically connecting the first through-via to the first semiconductor die; and
a second bond wire (bond wire on the right) electrically connecting the second through-via to the second semiconductor die (see Fig. 6 and respective text, also see Fig. 5 & Fig. 7),
wherein the first platform and second platform are each comprised of one or more sections (e.g. note the various tiers in the first and second platforms in Fig. 5-7), stacked one on top of another, each section comprising a conductive layer (e.g. the thin unlabeled layer housing the pads 127 and/or the pads 127 as shown in Fig. 5-7) and a dielectric layer (base material that are of dielectric material, Fig. 4A-5 & Fig. 6-7 and associated text), and
wherein, for the one or more sections of each of the first platform and the second platform (Fig. 5-7), there is an uppermost conductive layer at which one or more bond pads 127 are positioned and exposed therethrough (Fig. 1A & 4A-4C & Fig. 5-7), the one or more bond pads 127 being electrically connected to a respective one of the first through-via and the second through-via (Fig. 5-7).
Regarding claim 2, Boo teaches the semiconductor device package of claim 1, wherein the first platform 620b includes a first stepped surface E2, a second stepped surface E3 vertically offset from the first stepped surface, and a first bond pad of the one or more bond pads 127 exposed at the first stepped surface (Fig. 5-7), and wherein the first through-via extends through the first platform 620b from the first bond pad to the substrate 102 (Fig. 6, also see Fig. 4A-4C & Fig. 5-7 and note the pad formations on the stepped surfaces).
Regarding claim 3, Boo teaches the semiconductor device package of claim 2, wherein the first platform 620b includes a second bond pad exposed at the second stepped surface E2, and a third through-via electrically connected to the substrate 102 and the second bond pad, and wherein the third through-via extends through the first platform 620b from the second bond pad to the substrate 102 (Fig. 4C & Fig. 5-6 and respective texts).
Regarding claim 4, Boo teaches the semiconductor device package of claim 3 further comprising: a third semiconductor die included in the stack of semiconductor dies 110, the third semiconductor die positioned above the first and second semiconductor dies; and a third bond wire electrically connecting the third semiconductor die to the third through-via (see Fig. 6-7).
Regarding claim 5, Boo teaches the semiconductor device package of claim 4, wherein at least a portion of the third bond wire is positioned vertically above the first bond wire and does not directly contact the first bond wire (Fig. 5 7 Fig. 6).
Regarding claim 8, Boo teaches the semiconductor device package of claim 1, wherein the first platform 620a has a total height that is greater than the second platform 620b (Fig. 6).
Regarding claim 9, Boo teaches the semiconductor device package of claim 1, wherein the first platform 620a and second platform 620b are comprised of a material the same as the substrate (package substrates are understood to comprise organic laminate and Boo teaches organic laminate for the first and second platforms in Para [0041], also see Fig. 1A & Fig. 6- Fig. 7).
Regarding claim 10, Boo teaches the semiconductor device package of claim 1, wherein the stack of semiconductor dies 110 comprise memory dies (Fig. 6 & Para [0026]).
Regarding claim 11, Boo teaches the semiconductor device package of claim 1, further comprising: a substrate bond pad electrically connected to the substrate 102 and positioned between the stack of semiconductor dies 110 and the first platform; and a bond wire electrically connecting the substrate bond pad to a bottom most semiconductor die included in the stack of semiconductor dies (e.g. see Fig. 1A).
Regarding claim 12, Boo teaches the semiconductor device package of claim 1, wherein the first bond wire is electrically connected to the first semiconductor die and another semiconductor die adjacent to the first semiconductor die (Fig. 6).
Regarding claim 13, Boo teaches the semiconductor device package of claim 1, wherein the first bond wire is electrically connected to the first semiconductor die and at least two adjacent semiconductor dies (Fig. 6).
Regarding claim 14, Boo teaches a semiconductor memory package comprising:
a substrate 102 including a top surface and a bond pad exposed at the top surface (Fig. 6 & Fig. 1A);
a stack of semiconductor dies 110 positioned on the top surface of the substrate 102 (Fig. 6);
a first platform 620a/120b positioned on the top surface of the substrate 102, the first platform including a plurality of through-vias (note the unlabeled vias in 620a and/or through vias 426 in Fig. 4A-4B) electrically connected to the substrate 102 and extending through the first platform 620a/120b (Fig. 6 & Fig. 1A);
a second platform 620b/120a positioned on the top surface of the substrate 102 opposite the first platform such that the stack of semiconductor dies 110 is positioned between the first and second platforms, the second platform including a plurality of through-vias (note the unlabeled vias in 620b and/or through vias 426 in Fig. 4A-4B)electrically connected to the substrate and extending through the second platform 620b/120a (Fig. 6 & Fig. 1A); and
a first bond wire connecting a first semiconductor die of the stack to the at least one through- via of the first platform 620a/b or 120a/b, and a second bond wire connecting a second semiconductor die of the stack to the at least one through-via of the second platform 620b/120a (Fig. 6 & Fig. 1A),
wherein the first platform and second platform are each comprised of one or more sections (e.g. note the various tiers in the first and second platforms in Fig. 5-7), stacked one on top of another, each section comprising a conductive layer (e.g. the thin unlabeled layer housing the pads 127 and/or pads 127 as shown in Fig. 5-7) and a dielectric layer (base material that are of dielectric material, Fig. 4A-5 & Fig. 6-7 and associated text), and
wherein, for the one or more sections of each of the first platform and the second platform (Fig. 5-7), there is an uppermost conductive layer at which one or more bond pads 127 are positioned and exposed therethrough (Fig. 1A & 4A-4C & Fig. 5-7), the one or more bond pads 127 being electrically connected to a respective one of the first through-via and the second through-via (Fig. 5-7).
Regarding claim 15, Boo teaches the semiconductor device package of claim 14, wherein the first platform 620a/120b includes at least two stepped surfaces vertically offset from one another (note the two elevations), each of the stepped surfaces including a bond pad of the plurality of bond pads 127 electrically connected to one or more of the plurality of through-vias of the first platform 620a/120b (Fig. 5-7 & Fig. 1A).
Regarding claim 17, Boo teaches the semiconductor device package of claim 14, wherein the first and second platforms (620a/120b & 620b/120a) include a series of sections stacked one on top of another, each section comprising a conductive layer and a dielectric layer, such that each of the first and second platforms are formed of an alternating series of conductive layers 127 and dielectric layers (base material layers) with a conductive layer disposed between adjacent dielectric layers (Fig. 5-7 and associated texts).
Regarding claim 19, Boo teaches the semiconductor device package of claim 14, wherein the first platform and second platform are comprised of a material the same as the substrate (package substrates are understood to comprise organic laminate and Boo teaches organic laminate for the first and second platforms in Para [0041], also see Fig. 1A & Fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Boo as applied to claim 14 above and in further view of YEE et al. (US Pub. 2014/0339706).
Regarding claim 18, Boo is silent on the semiconductor device package of claim 14, wherein each through-via of the plurality of through-vias has a diameter of about 10 microns. However, YEE discloses in Para [0027] a semiconductor device comprising a plurality of through-vias, wherein each via of the plurality of through-vias has a diameter of about 10 microns. This claim dimension would have been obvious to one of the ordinary skill in the art in view of Boo and YEE. One of the ordinary skill in the art is motivated to form device features as small as possible with large enough thickness to allow proper device operation, in order to save on material and processing costs. As such, it would have been obvious to use a diameter of about 10 um for the through-via.
The claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955)(selection of optimum ranges within prior art general conditions is obvious).
Allowable Subject Matter
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 07/09/2026 have been fully considered but they are not persuasive. The Examiner maintains that the Boo continues to teach the amended claim features as addressed in the rejection above (note item by item matching). Therefore, the argument is not found to be persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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