DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Invention I (semiconductor device) and Species #3, as shown in FIG. 5, in the reply filed on April 29, 2026 is acknowledged.
Applicant identified claims 1, 8 and 10 are readable on the elected Species #3.
Claims 1-20 are pending. Non-Elected Invention and/or Species, Claims 2-7, 9 and 11-20 have been withdrawn from consideration.
Claim 8 recites: the IC device of claim 6, in which …
Since claim 6 is non-elected, claim 8 depends on withdrawn claim 6, is effectively withdrawn from consideration.
Action on merits of the Elected Invention and Species, claims 1 and 10 follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 08, 2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
LATTERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) TRANSISTOR HAVING A NON-UNIFORMLY DOPED LAYER IN AN N-TYPE BURIED LAYER APPROXIMATE A SUBSTRATE REGION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TAN et al. (US. Pub. No. 2022/0069122) of record.
With respect to claim 1, TAN teaches an integrated circuit (IC) device, comprising:
a P-type substrate (110);
an N-type buried layer (120) on the substrate (110) and including a non-uniformly doped layer (121) in the N-type buried layer (120), the non-uniformly doped layer (121) being proximate a first substrate region; and
a first laterally diffused metal oxide semiconductor (LDMOS) transistor on the first substrate region. (See FIG. 2).
With respect to claim 10, in which the first LDMOS transistor of TAN comprises a high voltage NLDMOS transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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