Prosecution Insights
Last updated: October 02, 2026
Application No. 18/366,441

LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) TRANSISTOR INTEGRATION IN INTEGRATED CIRCUIT (IC) PLATFORM

Final Rejection §102
Filed
Aug 07, 2023
Examiner
MAI, ANH D
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
2 (Final)
38%
Grant Probability
At Risk
3-4
OA Rounds
6m
Est. Remaining
47%
With Interview

Examiner Intelligence

Grants only 38% of cases
38%
Career Allowance Rate
267 granted / 709 resolved
-30.3% vs TC avg
Moderate +10% lift
Without
With
+9.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
39 currently pending
Career history
765
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
21.8%
-18.2% vs TC avg
§112
30.0%
-10.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 709 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Claims Applicant’s election without traverse of Invention I (semiconductor device) and Species #3, as shown in FIG. 5, in the reply filed on April 29, 2026 is acknowledged. Applicant identified claims 1, 8 and 10 are readable on the elected Species #3. Claims 1-20 are pending. Non-Elected Invention and/or Species, Claims 2-7, 9 and 11-20 have been withdrawn from consideration. Claim 8 recites: the IC device of claim 6, in which … Since claim 6 is non-elected, claim 8 depends on withdrawn claim 6, is effectively withdrawn from consideration. Action on merits of the Elected Invention and Species, claims 1 and 10 follows. Information Disclosure Statement The information disclosure statement (IDS) submitted on November 08, 2024 has been considered by the examiner. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: LATTERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) TRANSISTOR HAVING A NON-UNIFORMLY DOPED LAYER IN AN N-TYPE BURIED LAYER APPROXIMATE A SUBSTRATE REGION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TAN et al. (US. Pub. No. 2022/0069122) of record. With respect to claim 1, TAN teaches an integrated circuit (IC) device, comprising: a P-type substrate (110); an N-type buried layer (120) on the substrate (110) and including a non-uniformly doped layer (121) in the N-type buried layer (120), the non-uniformly doped layer (121) being proximate a first substrate region; and a first laterally diffused metal oxide semiconductor (LDMOS) transistor on the first substrate region. (See FIG. 2). With respect to claim 10, in which the first LDMOS transistor of TAN comprises a high voltage NLDMOS transistor. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH D MAI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Aug 07, 2023
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102
Jul 21, 2026
Examiner Interview Summary
Jul 21, 2026
Applicant Interview (Telephonic)
Jul 24, 2026
Response Filed
Sep 29, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12727194
SEMICONDUCTOR DIE HAVING A DRIFT REGION WITH A CHARGE COMPENSATION REGION FORMED THEREIN WHERE THE CHARGE COMPENSATION REGION HAS A PLURALITY OF GUARD RINGS FORMED IN FIRST AND SECOND OPPOSITE DOPING TYPE PORTIONS
6y 6m to grant Granted Sep 01, 2026
Patent 12707792
A DISPLAY DEVICE HAVING A LIGHT TRANSMITTING LAYER FORMED BETWEEN A WAVELENGTH CONVERSION LAYER AND COLOR FILTER LAYER
4y 2m to grant Granted Aug 11, 2026
Patent 12701753
SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE HAVING TRENCH GATE STRUCTURES FORMED ON STACKED LAYERS OF PARALLEL PN JUNCTIONS THAT EXTENDED IN DIFFERENT DIRECTIONS AND A METHOD THEREOF
6y 6m to grant Granted Aug 04, 2026
Patent 12685026
METHOD FOR FORMING A MAMR STRUCTURE BASED ON A TMR - SPIN TORQUE OSCILLATOR (STO) HAVING SEED LAYER AND CAPPING LAYER OF METAL OXIDE
1y 11m to grant Granted Jul 14, 2026
Patent 12615863
IMAGE SENSOR HAVING AN ACTIVE PATTERN OF METAL OXIDE SEMICONDUCTOR DOPED WITH NITROGEN DISPOSED ON A HYDROGEN BLOCKING LAYER
4y 3m to grant Granted Apr 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
38%
Grant Probability
47%
With Interview (+9.6%)
3y 8m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 709 resolved cases by this examiner. Grant probability derived from career allowance rate.

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