DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election without traverse of Species II, claims 16-25 in the reply filed on 7/27/2026 is acknowledged.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Objections
3. The claims are objected because of the following reasons:
Re claims 21-25: are objected because claim 20 is missing, they should be renumbered or changed to claims 20-24.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 16, 19 and 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Endoh et al. (US 2013/0119452).
Re claim 16, Endoh teaches, under BRI, in view of Figs. 1, 2, 5, 14, 15 and/or 17, [0007, 0034, 0166, 0171, 0179, 0180, 0189, 0193], a 3D stackable memory cell structure, comprising:
-a first material (pillar 2);
-an insulating layer (8, indicated) that surrounds a first portion of the first material (2);
-a first floating body semiconductor material (5, indicated) that surrounds a second portion of the first material (2) and is located above the insulating layer (8);
-a second floating body semiconductor material (5, indicated) that surrounds a third portion of the first material (2) and is located below the insulating layer (8);
-a second material (of insulating layer 8 or of control gate 4) that surrounds the first floating body semiconductor material (5, indicated);
-a third material (of insulating layer 8 or of control gate 4) that surrounds the second floating body semiconductor material (5, indicated);
-a front gate material (USG 12);
-a first dielectric layer (layer 8 around 12) located between the front gate material (12) and the first floating body semiconductor material (5, indicated);
-a back gate material (LSG 11); and
-a second dielectric layer (layer 8 around 11) located between the back gate material (11) and the second floating body semiconductor material (5, indicated).
PNG
media_image1.png
518
475
media_image1.png
Greyscale
PNG
media_image2.png
523
547
media_image2.png
Greyscale
Re claim 19, Endoh teaches wherein the first material (2) comprises one of semiconductor (semiconductor pillar 2, [0166]) or conductor material, the second material (consider material control gate 4. [0034]) comprises one of semiconductor or conductor material, and the third material (consider material of 4, [0034]) comprises one of semiconductor or conductor material.
Re claim 21, Endoh teaches, Figs. 1 & 2, wherein the insulating layer (8) directly connects to the first portion of the first material (2).
Re claim 22, Endoh teaches, Figs. 1 & 2, wherein the first floating body semiconductor material (5, indicated) directly connects to the second portion of the first material (2) and the insulting layer (indicated) (in straight line).
Note: under BRI, directly connects = connects in straight line # physically connects/contacts.
Re claim 23, Endoh teaches, Figs. 1 & 2, wherein the second floating body semiconductor material (5, indicated) directly connects to the third portion of the first material (2) and the insulting layer (indicated) (in straight line).
Re claim 24, Endoh teaches, Figs. 1 & 2, wherein the first dielectric layer (layer 8 around 12) directly connects to the front gate (12) and the first floating body semiconductor material (5, indicated).
Note: under BRI, directly connects = connects in straight line # physically connects/contacts.
Re claim 25, Endoh teaches, Figs. 1 & 2, wherein the second dielectric layer (layer 8 around 11) directly connects to the back gate (11) and the second floating body semiconductor material (5, indicated).
Re claim 16, Endoh teaches, alternatively, under BRI, in view of Figs. 21-22A, [0257-0258], a 3D stackable memory cell structure, comprising:
-a first material (pillar 52);
-an insulating layer (57, indicated) that surrounds a first portion of the first material (52);
-a first floating body semiconductor material (55, indicated) that surrounds a second portion of the first material (52) and is located above the insulating layer (57);
-a second floating body semiconductor material (55, indicated) that surrounds a third portion of the first material (52) and is located below the insulating layer (57);
-a second material (of insulating layer 58 or of control gate 53) that surrounds the first floating body semiconductor material (5, indicated);
-a third material (of insulating layer 58 or of control gate 53) that surrounds the second floating body semiconductor material (55, indicated);
-a front gate material (62);
-a first dielectric layer (layer 57 around 62) located between the front gate material (62) and the first floating body semiconductor material (55, indicated);
-a back gate material (61); and
-a second dielectric layer (layer 57 around 61) located between the back gate material (161 and the second floating body semiconductor material (55, indicated).
PNG
media_image3.png
653
467
media_image3.png
Greyscale
PNG
media_image4.png
652
465
media_image4.png
Greyscale
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Endoh.
The teachings of Endoh have been discussed above.
Re claim 18, Endoh teaches, Fig. 1, wherein the insulating layer (8) forms a continuous layer, but does not explicitly teach the insulating layer comprises an oxide material or a nitride material.
Endoh does teach “forming another SiO.sub.2 insulating layer 17 on the floating gate 5” [0194] & the use of SiO2 [0185].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Endoh to obtain oxide material as claimed, because SiO2 is known and widely used in the art. it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Allowable Subject Matter
6. Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Alsmeier et al. (US 2012/0001249, Figs. 1A-2A) discloses a 3D NAND strings including semiconductor channels and a plurality of control gate electrodes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 9/8/26
Prosecution Insights