DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant's arguments filed 2/13/2026 have been fully considered but they are not persuasive. Regarding claims 1 and 11, the applicant argues the prior art does not teach the amended limitations, i.e. “wherein a protective area is disposed at the blank area and surrounds the product area… and the protective area comprises a plurality of concaves or vias arranged around a perimeter of the protective area.”
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Referring to Figs 15C – 15F of Wu, Sung-Yueh et al. (Pub No. US 20230387039 A1) (hereinafter, Wu), in the broadest reasonable interpretation of the claims, the openings (160) and vias (116) located in the protective area, in the plan view, do surround the product area, and are arranged around a perimeter of the protective area, although not the entire perimeter or every side of the product/protective area. (See MPEP § 2111)
Further, referring to Fig 15B of Wu below in the cross-sectional view, the vias (116) located in the protective area do completely surround the circuit die (50).
PNG
media_image1.png
415
652
media_image1.png
Greyscale
6. Applicant's arguments filed 2/13/2026 have been fully considered but they are not persuasive.
Regarding claim 7, in response to applicant's argument that Suzuki, Yoshihiro et al. (Pub No. JP 7380681 B2) (hereinafter, Suzuki) teaches a second frame (12) which is not equivalent to the through vias (116) of Wu, which are formed within the package component (100) and remain in the final product… [and] Suzuki’s frame body (12) is made of a resin or glass material, which is different from the through vias (116) of Wu, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
7. Applicant’s arguments, see Discussion of Claim Rejections under 35 U.S.C. 112, filed 2/13/2026, with respect to the rejection of claim 9 under 35 U.S.C. § 112 (b) have been fully considered and are persuasive. The rejection of claim 9 has been withdrawn.
8. Applicant’s arguments, see Discussion of the Specification, filed 2/13/2026, with respect to objection of the Specification have been fully considered and are persuasive. The objection of the Specification has been withdrawn.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1-6 and 8-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wu, Sung-Yueh et al. (Pub No. US 20230387039 A1) (hereinafter, Wu).
Wu, Figs 15C-15F: Plan view of packaging substrate with product and blank areas
PNG
media_image2.png
382
448
media_image2.png
Greyscale
Re Claim 1, (Currently Amended) Wu teaches a core-substrate for a manufacture of a semiconductor packaging substrate (Figs 2 - 15T; ¶[0020]),
wherein the core-substrate (Carrier substrate and integrated circuit die; 102/50; Figs 2/8; ¶[0021]) is distinguished into a product area (Area comprising integrated circuit die 50; Figs 15C-15F; ¶[0011]) and a blank area (Area comprising encapsulant above carrier substrate; 120; Figs 15C-15F; ¶[0031]; Note: Carrier substrate is not shown in Figs 15C-15F, however, the carrier substrate is disposed under encapsulant according to Figs 2 - 15T),
where the product area is an area (Area of carrier substrate underneath die 50) that a product utilized as a substrate (Semiconductor substrate; 52; Fig 1; ¶[0012]) of an individual semiconductor (Integrated circuit die; 50; Figs 1/15C-15F; ¶[0011]) is disposed; and the blank area is an area (Area outside of 50; Figs 15C-15F) excepting for the product area,
wherein a protective area (Area within blank area 120 comprising through vias 116 and openings 160; Figs 15C-15F; ¶[0044]) is disposed at the blank area and surrounds (Protective area comprising vias 116 and openings 160 surrounds product area, i.e. under die 50, in the cross-section view and on outer portion; Figs 15B/15C) the product area,
and the protective area comprises a plurality of concaves or vias arranged around a perimeter of the protective area (Through vias or openings; 116/160; Figs 15C-15F; ¶[0044]; Note: The through vias/openings are arranged around a perimeter, or outside portion, of the protective area).
Wu, Fig 12: Cross-section of packaging substrate with rewiring layers
PNG
media_image3.png
318
569
media_image3.png
Greyscale
Re Claim 2, (Original) Wu teaches the core-substrate of claim 1, wherein the core-substrate (Carrier substrate and integrated circuit die; 102/50; Fig 12; ¶[0021]) is a substrate selected from the group consisting of a silicon-based ceramic substrate, a glass-based ceramic substrate, a glass substrate, and combinations thereof (Glass substrate; ¶[0021]).
Re Claim 3, (Original) Wu teaches the core-substrate of claim 1, wherein the product area (Area comprising integrated circuit die 50; Figs 15C-15F; ¶[0011]) is an area where one, two, or more individual packaging substrates (Integrated circuit die; 50; Figs 15C-15F; ¶[001]) are disposed.
Re Claim 4, (Currently Amended) Wu teaches the core-substrate of claim 1, wherein the via or the concave (Through vias or openings; 116/160; Figs 15C-15F; ¶[0044]) is arranged in a row (Rows extending downwards surrounding 50; Fig 15F; ¶[0044]) surrounding at least some of the edges (Left and right edges; Fig 15F) of the product area.
Re Claim 5, (Currently Amended) Wu teaches the core-substrate of claim 1, wherein the concaves or the vias (Through vias or openings; 116/160; Figs 15C-15F; ¶[0044]) have the shape of an oval or a quadrangle (May be round or rectangular; Figs 15C-15F; ¶[0051]) having a length of 20 % to 150 % (160 has a length 100% of 50; Fig 15F) of one side of the edge (Sides in between 50; Fig 15F) of the product area.
Re Claim 6, (Currently Amended) Wu teaches the core-substrate of claim 1, wherein the inside of the concaves or the vias (Through vias or openings; 116/160; Figs 15C-15F; ¶[0044]) are disposed an electrically conductive material (Through-vias 116 comprise copper, titanium, tungsten, aluminum; ¶[0028]), an insulating material, or both of them (Opening 160 may contain encapsulant 120, i.e. Epoxy; Fig 15R; ¶[0031]).
Re Claim 8, (Original) Wu teaches the core-substrate of claim 1,
wherein the protective area (Area within blank area 120 comprising through vias 116 and openings 160; Figs 15C-15F; ¶[0044]) protects the product area (Area comprising integrated circuit die 50; Figs 15C-15F; ¶[0011]) from damage (Conductive component (via) extending into encapsulant 120 has high thermal conductivity and EMI shielding; ¶[0112]), which from the edge (Edge of 120; Figs 15C - 15F) of the core-substrate (Carrier substrate; 102; Fig 2; ¶[0021]) goes into the internal (Inner area of 120; Figs 15C-15F) of the core-substrate.
Re Claim 9, (Currently Amended) Wu teaches a substrate (Figs 2 – 15T) applied to a manufacture of a semiconductor packaging substrate, comprising: a core-substrate (Carrier substrate and integrated circuit die; 102/50; Figs 2/8; ¶[0021]) according to claim 1,
wherein the core-substrate comprises one side (Upper surface of 50; Fig 12) and the other side (Lower surface of 50; Fig 12) facing each other, and the core-substrate comprises an upper rewiring layer (Front-side redistribution structure; 122; Fig 12; ¶[0033]) disposed on one side thereof a lower rewiring layer (Backside redistribution structure; 106; Fig 12; ¶[0023]) disposed under the other side thereof,
wherein the upper rewiring layer comprises an upper insulating layer (Dielectric layer; 136; Fig 12; ¶[0033]) and an upper electronically conductive layer (Metallization pattern; 134; Fig 12; ¶[0033]) disposed in the upper insulating layer, and the lower rewiring layer comprises a lower insulating layer (Dielectric layer; 112; Fig 12; ¶[0023]) and a lower electronically conductive layer (Metallization pattern; 110; Fig 12; ¶[0025]) disposed in the lower insulating layer.
Re Claim 10, (Currently Amended) Wu teaches the substrate of claim 9,
wherein the concaves or the vias (Through vias or openings; 116/160; Figs 15C-15F; ¶[0044]) are removed parts (Openings 160 or openings 114; Figs 3/15C-15F; ¶[0028]) of the core-substrate (Carrier substrate and integrated circuit die; 102/50; Figs 2/8; ¶[0021]), and
the removed parts are filled with a filling material (Conductive material for vias 116 and encapsulant 120 in opening 160; Fig 15B; ¶¶[0028, 0031]).
Re Claim 11, (Currently Amended) Wu teaches a substrate utilized in semiconductor packaging,
wherein the substrate (Figs 2 - 15T) comprises a core-substrate (Carrier substrate and integrated circuit die; 102/50; Figs 2/8; ¶[0021]),
wherein the core-substrate is distinguished into a product area (Area comprising integrated circuit die 50; Figs 15C-15F; ¶[0011]) where a product utilized as a substrate (Semiconductor substrate; 52; Fig 1; ¶[0012]) of an individual semiconductor (Integrated circuit die; 50; Figs 1/15C-15F; ¶[0011]) is disposed; and a blank area (Area comprising encapsulant above carrier substrate; 120; Figs 15C-15F; ¶[0031]; Note: Carrier substrate is not shown in Figs 15C-15F, however, the carrier substrate is disposed under encapsulant according to Figs 2 - 15T) excepting for the product area,
wherein the blank area comprises a protective area (Area within blank area 120 comprising through vias 116 and openings 160; Figs 15C-15F; ¶[0044]) disposed to surround (Protective area comprising vias 116 and openings 160 surrounds product area, i.e. under die 50, in the cross-section view and on outer portion; Figs 15B/15C) the product area, and
and the protective area comprises a plurality of concaves or vias arranged around a perimeter of the protective area (Through vias or openings; 116/160; Figs 15C-15F; ¶[0044]; Note: The through vias/openings are arranged around a perimeter, or outside portion, of the protective area).
the protective area substantially suppresses damage (Conductive component (via) extending into encapsulant 120 has high thermal conductivity and EMI shielding; ¶[0112]), which occurs in the direction substantially perpendicular to the thickness direction (Horizontal direction) from the edge (Left and right edges of carrier substrate/integrated circuit die 102/50; Figs 15C-15F) of the core-substrate, not to go into the product area.
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wu, Sung-Yueh et al. (Pub No. US 20230387039 A1) (hereinafter, Wu) as applied to claim 4 above, and further in view of Suzuki, Yoshihiro et al. (Pub No. JP 7380681 B2) (hereinafter, Suzuki).
Wu, Fig 15J: Plan-view of packaging substrate with two rows of vias/openings
PNG
media_image4.png
177
198
media_image4.png
Greyscale
Re Claim 7, (Original) Wu teaches the core-substrate of claim 4, wherein the protective area (Area within blank area 120 comprising through vias 116 and openings 160; Figs 15C-15F; ¶[0044]) comprises two or more rows (Vertical rows of 160 and 116 surrounding 50; Fig 15J) respectively having different distances (160 is further than 116 from 50; Fig 15J) from the edges of the product area (Area comprising integrated circuit die 50; Figs 15C-15F; ¶[0011]), and
wherein the two or more rows comprise a first row and a second row arranged side by side (Rows of 160 and 116 are side by side; Fig 15J).
However, Wu does not teach a via of the first row and a via of the second row are staggered with each other.
In the same field of endeavor, Suzuki teaches a via of the first row (Second frames of inner vertical row; 12; Figs 1/2; ¶[0020]) and a via of the second row (Second frames of outer vertical row; 12; Figs 1/2; ¶[0020]) are staggered (Arranged in a staggered pattern; Fig 2) with each other.
Suzuki, Fig 2: Plan-view of protective area with staggered vias surrounding product area
PNG
media_image5.png
348
316
media_image5.png
Greyscale
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a via of the first row and a via of the second row are staggered with each other, as taught by Suzuki, with the core-substrate as taught by Wu. One would have been motivated to do this with a reasonable expectation of success because a discontinuous arrangement of the vias prevents warping which could affect the surrounding regions such as the product area, as suggested by Suzuki (¶[0022]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Tsai; Po-Hao et al. (Pub No. US 20200006307 A1) discloses a substrate with a product area and blank area comprising of protective and conductive vias disposed within said substrate in a row-pattern surrounding product area on every side of the perimeter.
[2] Chen, Han-Wen et al. (Pub No. CN118043957A) discloses a core-substrate surrounded by rewiring layers and comprises of a protective area of through vias penetrating through the core-substrate.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights