DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: COMPONENT CARRIER WITH MOUNTING REGION HAVING A MOUNTING RECESS FOR MOUNTING A COMPONENT HAVING A MOUNTING PROTRUSION
Election/Restrictions
Applicant’s election without traverse of claims 1-18 corresponding to Group I, Species II the reply filed on 11/21/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Base claim 1 recites “a mounting region arranged at the stack, configured for mounting a component thereon, and comprising: at least one mounting protrusion for insertion of the component in at least one mounting recess”. It is not clear if the “mounting protrusion” is part of the “mounting region” or is the “mounting protrusion” part of the “component”. For the purposes of this office action, the above recitation will be considered equivalent of “a mounting region arranged at the stack, configured for mounting a component thereon, wherein the component comprises at least one mounting recess and comprising: the mounting region comprising at least one mounting protrusion, the at least one mounting protrusion for insertion into the of the component in at least one mounting recess”.
Claims 17 and 18 recites “and/or” and it is not clear what that means in the context of claims. For the purposes of this office action, above recitation in any claim will be assumed that either “and” OR “or” reads on the claim. Thus, only showing the case where condition of “or” is met reads on the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10 and 18 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hiroshi (JP2001244333A), hereinafter Hiroshi. A full English machine translation of Hiroshi reference is included with this office action and all reference to Hiroshi is with respect to this included full English machine translation.
Regarding claim 1, Hiroshi (JP2001244333A) (refer to markup of Figure 6i below; also refer to other Figures as outlined below) teaches component carrier, comprising:
a stack comprising at least one electrically conductive layer structure (25, 26, 27 – described as “first wiring” in [0027], especially see page 12, last 2 paragraphs} and at least one electrically insulating layer structure {19 and 28, described as “insulating film 28” and “insulating film 19” in [0027], especially see page 11, last paragraph and page 12, last sentence}; and
a mounting region (region of 19 on which 2 is mounted) arranged at the stack, configured for mounting a component {2, described as “first semiconductor chip 2” in [0024]; also see Figure 2c} thereon, and comprising:
at least one mounting protrusion (formed by 3, described as “second semiconductor chip 3” in para 24; also see Figure 2d) for insertion of the component in at least one mounting recess (10, best seen in Figure 2c, also see markup of Figure 6i; and described as “groove 10” on the “first semiconductor chip 2” in para 26-27) – also see 35 USC 112, 2nd paragraph rejection above.
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Regarding claim 2, Hiroshi (refer to markup of Figure 6i above) teaches the component carrier according to claim 1, further comprising: the component (2) having the at least one mounting recess (10) and being mounted at the mounting region, wherein the at least one mounting protrusion (formed by 3) is at least partially inserted into the at least one mounting recess (10).
Regarding claim 3, Hiroshi (refer to markup of Figure 6i above) teaches the component carrier according to claim 2, wherein the component (2) is an electronic component {2 is described as “first semiconductor chip 2” in [0024]}, or a thermally conductive block.
Regarding claim 4, Hiroshi (refer to markup of Figure 6i above) teaches the component carrier according to claim 2, wherein the at least one mounting protrusion (3) is configured for dissipating heat (as 3 is described as “second semiconductor chip 3” in para 24, and given that all semiconductor chips must necessarily dissipate heat – note no specific magnitude of heat dissipated is required), when the component (2) is mounted at the mounting region with the at least one mounting protrusion (3) inserted in the at least one mounting recess.
Regarding claim 10, Hiroshi (refer to markup of Figure 6i above) teaches the component carrier according to claim 1, wherein the mounting region (region of 19 on which 2 is mounted) is at least partially located at an exterior main surface (i.e. peripheral surface of 19) of the stack.
Regarding claim 18, Hiroshi teaches component carrier according to claim 1, wherein the at least one mounting protrusion (3) is shaped as a pillar protruding beyond a planar surrounding of the mounting region (best seen in markup of Figure 6i), wherein the at least one mounting recess or the at least one mounting protrusion has substantially straight sidewalls (best seen in markup of Figure 6i).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hiroshi.
Regarding claim 5, Hiroshi (refer to markup of Figure 6i above) teaches the component carrier according to claim 2, but does not teach wherein the mounting region comprises “at least two mounting protrusions” wherein the component comprises “at least two mounting recesses, and wherein each mounting protrusion is at least partially inserted into an associated mounting recess”. However, the above recitation simply duplicates the structure recited in claim 1; i.e. from at least one mounting protrusion to substantially similar but at least two mounting protrusions, and corresponding substantially similar “at least two mounting recesses”. It would have been obvious to one of ordinary skill in the art at the time of the effective filing of the claimed invention to modify Hiroshi to include the limitations recited in claim 5 because such structure is considered to be a duplication of parts that has no patentable significance unless a new unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), MPEP 2144.04.
Claim 6-9 and 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshi in view of Kaeding (US 2020/0126917), hereinafter Kaeding.
Regarding claim 6, Hiroshi (refer to markup of Figure 6i above) teaches the component carrier according to claim 1, but does not teach it further comprises “a cavity in the stack, wherein the mounting region is at least partially located in the cavity”. Kaeding (US 2020/0126917) (refer to Figure 7) teaches a component carrier comprising a stack (732, 770 and 736, see para 51; also see para 50 which describes 736 as “mold material 736”) with a mounting region (surface of mold material 736 that contacts lowermost surface of 780 in Figure 7, see para 780) arranged at the stack, the mounting substrate being configured for mounting a component (780, para 49) thereon, wherein the component carrier further comprises a cavity (cavity in mold material 736 in which 780 is accommodated) in the stack, wherein the mounting region (i.e. surface of mold material 736 that contacts lowermost surface of 780 in Figure 7) is at least partially located in the cavity (noting that cavity is substantially the same size as the component). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Hiroshi so that it further comprises “a cavity in the stack, wherein the mounting region is at least partially located in the cavity”. The ordinary artisan would have been motivated to modify Hiroshi for at least the purpose of using a component carrier in which component(s) are encapsulated in a mold material and the component is placed in a cavity in the mold material, thus protecting the component from external contaminants and improving reliability.
Regarding claim 7, Hiroshi, as modified in view of Kaeding above for claim 6 to include the cavity that is substantially the same size as the component, teaches that the mounting protrusion is arranged at the bottom of the component, and hence at bottom of the cavity.
Regarding claim 8, Hiroshi, as modified in view of Kaeding above for claim 6 to include the cavity that is substantially the same size as the component, teaches that the the mounting protrusion extends within the volume of the component, and hence within the volume of the cavity (as the cavity that is substantially the same size as the component), and as such, the extension of the mounting protrusion is restricted by the volume of the cavity.
Regarding claim 9, Hiroshi teaches the component carrier according to claim 1, but does not teach wherein the mounting protrusion comprises “at least one vertical through connection”. However, Hiroshi’s mounting protrusion is a semiconductor chip (as the mounting protrusion is formed by 3, which is described as “second semiconductor chip 3” in para 24). Kaeding (refer to Figure 7) teaches the semiconductor components may have vertical through connections (such as through-silicon vias or TSVs, described in para 23 and 47) to connect to other components of the circuit. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Hiroshi so that the mounting protrusion (3) includes TSVs that comprise “at least one vertical through connection”. The ordinary artisan would have been motivated to modify Hiroshi for at least the purpose of using through-silicon vias for making electrical connections to other components (such as in Figure 7 of Kaeding) of the component carrier.
Regarding claims 11-13, Hiroshi teaches the component carrier according to claim 1, but does not teach wherein the at least one mounting protrusion comprises “at least one electric contact for electrically contacting at least one electrically conductive structure of the component when the at least one mounting protrusion is inserted in the at least one mounting recess”; and as such, also does not teach limitations of claims 12-13; i.e. “the electric contact is an electrically conductive structure and/or an electrical pad” (as recited in claim 12); OR wherein (as recited in claim 13) “the electric contact is arranged on a top of the mounting protrusion”. However, Hiroshi’s mounting protrusion is a semiconductor chip (as the mounting protrusion is formed by 3, which is described as “second semiconductor chip 3” in para 24). Kaeding (refer to Figure 7) teaches the semiconductor components may have at least one electric contact for electrically contacting at least one electrically conductive structure of the component (such as through-silicon vias or TSVs, described in para 23 and 47) to connect to other components of the circuit. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Hiroshi so that the at least one mounting protrusion comprises TSVs; i.e. at least one electric contact for electrically contacting other components that are proximate, such as at least one electrically conductive structure of the component when the at least one mounting protrusion is inserted in the at least one mounting recess. From the above, it also follows that the electric contact is an electrically conductive structure (as required by claim 12); OR wherein the electric contact is arranged on a top of the mounting protrusion (because TSVs extend through the entire depth; i.e. from top to bottom of the protrusion. The ordinary artisan would have been motivated to modify Hiroshi for at least the purpose of using through-silicon vias for making electrical connections to other components (such as in Figure 7 of Kaeding) of the component carrier.
Regarding claims 14-15, Hiroshi teaches the component carrier according to claim 2, but does not teach wherein the component comprises “at least one further electrically conductive structure being electrically connected with at least one further electric contact provided at the mounting region apart from the at least one mounting protrusion” (as required by claim 14), wherein (as required by claim 15) “the further electrically conductive structure is one of a slanted connection, a via, a pillar, and a bump”. However, Hiroshi’s mounting protrusion is a semiconductor chip (as the mounting protrusion is formed by 3, which is described as “second semiconductor chip 3” in para 24). Kaeding (refer to Figure 7) teaches the semiconductor components may have at least one further electrically conductive structure (such as through-silicon vias or TSVs, described in para 23 and 47) being electrically connected with at least one further electric contact (such as with TSVs of additional stacked components in Figure 7 or to pads/bumps of the mounting region) provided at the mounting region apart from the at least one mounting protrusion (as required by claim 14), wherein (as required by claim 15) the further electrically conductive structure is one of a via, a pillar, and a bump (as explained above).
It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Hiroshi to include the missing limitations of claims 14-15 identified above. The ordinary artisan would have been motivated to modify Hiroshi for at least the purpose of using through-silicon vias and corresponding bumps/pads for making electrical connections to other components (such as in Figure 7 of Kaeding) of the component carrier.
Regarding claim 16, Hiroshi teaches the component carrier according to claim 2, but does not teach wherein the stack (which is a mounting substrate) is electrically connected with the component “by a redistribution layer”. Kaeding (refer to Figure 7) teaches a component carrier wherein a substrate (232) may include a redistribution layer (para 34) It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Hiroshi so that the stack includes a redistribution layer and as such the stack is electrically connected with the component by the redistribution layer. The ordinary artisan would have been motivated to modify Hiroshi for at least the purpose of using a known technique for redistributing electrical connections efficiently in a dedicated redistribution layer, thus improving connectivity between various parts of the circuit while still keeping the device compact.
Regarding claim 17, Hiroshi teaches the component carrier according to claim 2, but does not teach wherein the at least one mounting protrusion is configured for “contributing to a transmission of an electrical signal between the component and the stack”. However, this requirement is substantially similar to use of TSVs for electrical connections through the mounting protrusion, and as such, the rejection is substantially similar to that of claim 11 in view of Kaeding.
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892