DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendment to Claim 14 addressing the claim’s rejection under 35 U.S.C. 112(b) in the reply filed 22 May 2026 is acknowledged. This rejection has been overcome by the amendment of said claim, and the associated rejection is withdrawn.
Applicant’s amendment to Claim 14 addressing the drawing objection under 37 CFR 1.83(a) in the reply filed 22 May 2026 is acknowledged. This objection has been overcome by the amendment of said claim, and the associated objection is withdrawn.
Applicant’s amendment to the title of the invention addressing the specification objection in the reply filed 22 May 2026 is acknowledged. This objection has been overcome by the amendment of said title, and the associated objection is withdrawn.
Applicant’s remarks filed 22 May 2026 are not entirely consistent with Applicant’s most recent set of claims filed 22 May 2026, regarding the status of the claims. Specifically, in the remarks, Applicant states Claims 7 & 13 are cancelled. However, in the claims, Applicant presents Claims 7 & 13 as withdrawn. Further, Applicant states in the remarks that Claims 17 – 20 are withdrawn. However, in the claims, Applicant presents Claims 17 – 19 as withdrawn but Claim 20 as currently amended. For the purposes of examination, the status of the claims will be treated as the claims are presented. Specifically, Claim 20 will be treated as currently amended, and Claims 1 – 20 will be treated as pending. Applicant is advised to clarify the status of the claims in the response to this Office Action.
Regarding the prior art rejection of the claims set forth in the previous Office Action filed 25 February 2026, on page 10 of the previous reply filed 22 May 2026, Applicant asserts:
The dielectric structure 130 of Guler is NOT a gate cut pattern.
In support of this assertion, Applicant argues:
The dielectric structure 130 of Guler is "referred to as a fin-trim isolation structure (paragraph [0037] of Guler)," and a "gate cut" of Guler is located "between the gate structure 110/112 and the dielectric structure 130 (paragraph [0040] of Guler."
Applicant’s arguments have been fully considered but are not found persuasive, as the mere nomenclature provided in the specification of GULER does not preclude a broadest reasonable interpretation of the claimed “gate cut insulating pattern” from including the combination of parts 122 and 130 of GULER as presented in the prior art rejection of the claims. Therefore, 130/122s of GULER is deemed to be a proper broadest reasonable interpretation of the claimed “gate cut insulating pattern”.
Regarding the rejection of Claims 14 & 20 under 35 U.S.C. 102(a)(2) and 35 U.S.C. 103, respectively, as set forth in the previous Office Action filed 25 February 2026, on page 10 of the previous reply filed 22 May 2026, Applicant asserts:
Guler fails to teach [the amended limitation “a width of the gate cut insulating pattern between the plurality of first gate lines and the plurality of second gate lines is same with a width of a top surface of the dummy active fin”].
In support of this assertion, Applicant argues:
The width of 130/122s of Guler…between the plurality of first gate lines and the plurality of second gate lines is either the width of the dielectric gate cut plug 122 of Guler or the width of two 122s and 130 combined. Neither width is same with the width of a top surface of the dummy active fin.
Applicant’s arguments have been fully considered but are not found persuasive, as the Examiner is able to provide a different and proper interpretation of GULER, as provided in the prior art rejection to follow, which satisfies the amended limitation. Therefore, amending Claims 14 & 20 as provided by Applicant in the aforementioned reply is not deemed to patentably distinguish Applicant’s claimed invention from the known invention of the prior art of record.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 14 & 20 are objected to because of the following informalities:
Regarding Claim 14,
Lin. 20 – 22 recite the limitation “a width of the gate cut insulating pattern between the plurality of first gate lines and the plurality of second gate lines is same with a width of a top surface of the dummy active fin” which reduces to “a width of X is same with a width of Y”. This sentence structure appears to be missing an article and a preposition, making the meaning unclear. That is, the reduced structure appears to be complete without changing meaning when written as “a width of X is the same as the same as
Regarding Claim 20,
Lin. 26 – 28 recite the limitation “a width of the gate cut insulating pattern between the plurality of first gate lines and the plurality of second gate lines is same with a width of a top surface of the dummy active fin” which reduces to “a width of X is same with a width of Y”. This sentence structure appears to be missing an article and a preposition, making the meaning unclear. That is, the reduced structure appears to be complete without changing meaning when written as “a width of X is the same as the same as .
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 20 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claim 20,
Lin. 26 recites the limitation “the plurality of first gate lines” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “the first gate line”.
Lin. 27 recites the limitation “the plurality of second gate lines” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “the second gate line”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 14 – 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by GULER (US 20240105804 A1).
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Regarding Claim 14,
GULER discloses:
An integrated circuit device (Annotated Fig. 1E) comprising:
a plurality of fin-type active regions (Annotated Fig. 1E: 104s) protruding in a vertical direction from a substrate (Annotated Fig. 1E: 104s protrude in DV; Further, Par. 32 teaches the 104s “may be extending from a substrate” where “protrude from” and “extend from” are synonymous in this context) and extending parallel to each other in a first horizontal direction (Annotated Fig. 1E: 104s extend parallel to each other in D1), the plurality of fin-type active regions being spaced apart from each other in a second horizontal direction (Annotated Fig. 1E: 104s are spaced apart from each other in D2) that intersects with the first horizontal direction (Annotated Fig. 1E: D1 and D2 intersect at a right angle);
a device isolation film (Annotated Fig. 1E: 106) adjacent to the plurality of fin-type active regions (Annotated Fig. 1E: 106 is adjacent to the vertical sidewalls of the 104s);
a plurality of first gate lines (Annotated Fig. 1E: G1/G1’ of 110s) extending lengthwise in the second horizontal direction on the plurality of fin-type active regions (Annotated Fig. 1E: G1/G1’ extend lengthwise in D2 with G1 on the leftmost 104);
a plurality of second gate lines (Annotated Fig. 1E: G2/G2’ of 110s) separated from the plurality of first gate lines in the second horizontal direction (Annotated Fig. 1E: G2/G2’ separated from G1/G1’ in D2 by leftmost 122 of 130/122s) by a gate cut insulating pattern (Annotated Fig. 1E: 130/122s) disposed above a dummy active fin (Annotated Fig. 1E: 104A, above which is 130 of 130/122s) between a first fin-type active region (Annotated Fig. 1E: F1 of 104s) and a second fin-type active region (Annotated Fig. 1E: F2 of 104s),
wherein the dummy active fin protrudes in the vertical direction from the substrate and extends lengthwise in the first horizontal direction (Fig. 1C & 1D: 104A is formed from the top portion of the middle 104, Par. 36. Therefore, as the other 104s protrude in DV from the substrate and extend lengthwise in D1, so does 104A);
and the gate cut insulating pattern extending lengthwise in the first horizontal direction (Annotated Fig. 1E: 122s of 130/122s extend lengthwise in D1) between the plurality of first gate lines and the plurality of second gate lines (Annotated Fig. 1E: leftmost 122 of 130/122s is between G1/G1’ and G2/G2’) and overlapping the dummy active fin in the vertical direction (Annotated Fig. 1E: 130 of 130/122s overlaps 140A in DV),
wherein the device isolation film comprises a first local isolation portion (Annotated Fig. 1E: portion of 106 between the F1 and 104A) between the first fin-type active region and the dummy active fin and a second local isolation portion (Annotated Fig. 1E: portion of 106 between F2 and 104A) between the second fin-type active region and the dummy active fin, and
wherein a width (Annotated Fig. 1E: W1, a partial width of 130) of the gate cut insulating pattern (130/122s) between the plurality of first gate lines (G1/G1’) and the plurality of second gate lines (G2/G2’) is the same as a width (Annotated Fig. 1E: W2) of a top surface of the dummy active fin (104A).
(Note, as the gate cut insulating pattern of GULER comprises a leftmost 122, a rightmost 122, and 130, any width of any of these components—alone or in combination—in any direction may be construed as “a width of the gate cut insulating pattern” under a broadest reasonable interpretation. Therefore, any such width provided between G1/G1’ and G2/G2’ with the same width as W2 satisfies this limitation. Further still, the phrase “a width” does not preclude the interpretation of “a width” from being “a partial width” under a broadest reasonable interpretation. Accordingly, the partial width W1 of 130 may be construed to be a width of 130/122s under a broadest reasonable interpretation, and W1 is disposed between G1/G1’ and G2/G2’ and has the same width as W2 of 104A as seen in Annotated Fig. 1E, satisfying the limitations of this claim.)
Regarding Claim 15,
GULER discloses:
The integrated circuit device of claim 14,
wherein the dummy active fin and the plurality of fin-type active regions are integrally connected to the substrate (Par. 32 states that the 104s—and 104A, as per Par. 36—“may be extending from a substrate, such as silicon sub-fins extending from a silicon substrate”. Further, the term “integrally connected” refers to a relationship or connection essential as a part of a whole. Therefore, a person of ordinary skill in the art would understand that the 104s and 104A in Annotated Fig. 1E are integrally connected to the substrate. Accordingly, GULER meets and anticipates the recited limitation.)
Regarding Claim 16,
GULER discloses:
The integrated circuit device of claim 14,
further comprising a plurality of nanosheet stacks (Annotated Fig. 1E & Fig. 1F, 150: 108s) arranged over each of the plurality of fin-type active regions (Annotated Fig. 1E: 108s arranged over each of the 104s),
each of the plurality of nanosheet stacks comprising at least one nanosheet surrounded by one gate line selected from the plurality of first gate lines and the plurality of second gate lines (Annotated Fig. 1E: each 108 comprises four nanosheets, wherein the leftmost 108 is surrounded by G1 of G1/G1’ and the rightmost 108 is surrounded by G2 of G2/G2’),
wherein a vertical level of an upper surface of the gate cut insulating pattern (Annotated Fig. 1E: S1) is farther from the substrate than a vertical level of an upper surface of each of the plurality of first gate lines and the plurality of second gate lines (Annotated Fig. 1E: S2s, wherein the vertical level of S1 is farther from the substrate than the vertical level of the S2s).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over GULER.
Regarding Claim 20,
GULER discloses for an embodiment:
An integrated circuit device (Annotated Fig. 1E) comprising:
a first fin-type active region (Annotated Fig. 1E: F1 of 104s) and a second fin-type active region (Annotated Fig. 1E: F2 of 104s), which protrude in a vertical direction from a substrate (Annotated Fig. 1E: 104s protrude in DV; Further, Par. 32 teaches the 104s “may be extending from a substrate” where “protrude from” and “extend from” are synonymous in this context) and are adjacent to each other (Annotated Fig. 1E: F1 and F2 are adjacent to each other);
a device isolation film (Annotated Fig. 1E: 106) covering both sidewalls of each of the first fin-type active region and the second fin-type active region (Annotated Fig. 1E: 106 covers both sidewalls of F1 and F2; Further, Par. 32 states each 104 “protrude[s] through” 106, thereby covering both sidewalls of each 104);
a first nanosheet stack (Annotated Fig. 1E: leftmost 108 arranged over F1), including at least one nanosheet (Annotated Fig. 1E: each 108 comprises four nanosheets), arranged over the first fin-type active region;
a first gate line (Annotated Fig. 1E: G1 surrounding the leftmost 108) surrounding the first nanosheet stack;
a second nanosheet stack (Annotated Fig. 1E: rightmost 108 arranged over F2), including at least one nanosheet (Annotated Fig. 1E: each 108 comprises four nanosheets), arranged over the second fin-type active region:
a second gate line (Annotated Fig. 1E: G2 surrounding the rightmost 108) surrounding the second nanosheet stack;
a dummy active fin (Annotated Fig. 1E: 104A) separating the first fin-type active region from the second fin-type active region and protruding in the vertical direction from the substrate (Annotated Fig. 1E: 104A separates F1 from F2 and protrudes in DV; Further, Par. 32 teaches the 104s—including 104A, as per Fig. 1C, Fig. 1D, and Par. 36–“may be extending from a substrate” where “protrude from” and “extend from” are synonymous in this context);
a gate cut insulating pattern (Annotated Fig. 1E: 130/122s) separating the first gate line from the second gate line (Annotated Fig. 1E: 130/122s separate G1 from G2),
wherein the gate cut insulating pattern is on the dummy active fin in the vertical direction (Annotated Fig. 1E: 130 of 130/122s is on 104A in DV)…;
a first gate dielectric film (Annotated Fig. 1E: A1 of 112s separating the nanosheets of the leftmost 108 from G1) separating the at least one nanosheet of the first nanosheet stack from the first gate line,
wherein the first gate dielectric film contacts a first sidewall of the gate cut insulating pattern (Annotated Fig. 1E: A1 contacts the leftmost sidewall of 130/122s at P1);
and a second gate dielectric film (Annotated Fig. 1E: A2 of 112s separating the nanosheets of the rightmost 108 from G2) separating the at least one nanosheet of the second nanosheet stack from the second gate line,
wherein the second gate dielectric film contacts a second sidewall of the gate cut insulating pattern opposite the first sidewall (Annotated Fig. 1E: A2 contacts the rightmost sidewall of 130/122s at P2 where the rightmost sidewall of 130/122s is opposite the leftmost sidewall of 130/122s),
wherein the device isolation film comprises a first local isolation portion (Annotated Fig. 1E: portion of 106 between the F1 and 104A) between the first fin-type active region and the dummy active fin, and a second local isolation portion (Annotated Fig. 1E: portion of 106 between the F2 and 104A) between the second fin-type active region and the dummy active fin, and
wherein a width (Annotated Fig. 1E: W1, a partial width of 130) of the gate cut insulating pattern (130/122s) between the first gate line (G1) and the second gate line (G2) is the same as a width (Annotated Fig. 1E: W2) of a top surface of the dummy active fin (104A).
(Note, as the gate cut insulating pattern of GULER comprises a leftmost 122, a rightmost 122, and 130, any width of any of these components—alone or in combination—in any direction may be construed as “a width of the gate cut insulating pattern” under a broadest reasonable interpretation. Therefore, any such width provided between G1 and G2 with the same width as W2 satisfies this limitation. Further still, the phrase “a width” does not preclude the interpretation of “a width” from being “a partial width” under a broadest reasonable interpretation. Accordingly, the partial width W1 of 130 may be construed to be a width of 130/122s under a broadest reasonable interpretation, and W1 is disposed between G1 and G2 and has the same width as W2 of 104A as seen in Annotated Fig. 1E, satisfying the limitations of this claim.)
However, GULER does not disclose for the same embodiment:
…and the gate cut insulating pattern extends above the first gate line and the second gate line;
Although, for a similar embodiment, GULER discloses:
…and the gate cut insulating pattern extends above the first gate line and the second gate line (Fig. 4B: the gate cut insulating pattern—464—extends above the first gate line—leftmost 458/460—and the second gate line—rightmost 458/460);
For the similar embodiment, GULER further discloses:
a dielectric gate cap (Fig. 4B: 462) over the first gate line (leftmost 458/460) and the second gate line (rightmost 458/460), wherein the gate cut insulating pattern (464) extends above the first gate line and the second gate line (Par. 60).
As such, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the previously mentioned embodiments of GULER, as these inventions are from the same field of endeavor, and the formation of such a dielectric gate cap would have been known to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a means to protect the underlying gate lines. Additionally, GULER suggests such a combination, Par. 124.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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