DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, as presented by at least Fig. 2A, in the reply filed on 1 December 2025 is acknowledged.
Applicant’s withdrawal of Claims 6, 8, 18, & 19 from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim is acknowledged. Election was made without traverse in the reply filed on 1 December 2025.
Examiner also withdraws Claims 1 – 5, 7, 9 – 13, & 17 from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Regarding Claim 1, in light of the elected Species I of Fig. 2A, this claim recites the limitation “the first local isolation portion [112A] and the second local isolation portion [112B] being apart from each other in the second horizontal direction [Y] with the gate cut insulating pattern [150] therebetween”.
However, this limitation does not describe the elected species, as the gate cut insulating pattern [150] is not between the first local isolation portion [112A] and the second local isolation portion [112B].
Further, this limitation does describe the nonelected Species II of Fig. 3 and Species IV of Fig. 5, which is evidenced by the instant specification, wherein Par. 68 states “The gate cut insulating pattern 250 [of Fig. 3, Species II] may have substantially the same configuration as the gate cut insulating pattern 150 described with reference to FIGS. 1 and 2A to 2D. However, the gate cut insulating pattern 250 may include a lower extension portion 250E between the first local isolation portion 112A and the second local isolation portion 112B.” and wherein Par. 78 states “The gate cut insulating pattern 450 [of Fig. 5, Species IV] may have substantially the same configuration as the gate cut insulating pattern 150 described with reference to FIGS. 1 and 2A to 2D. However, the gate cut insulating pattern 450 may include a lower extension portion 450E between the first local isolation portion 112A and the second local isolation portion 112B.”
Regarding Claims 2 – 13, these claims are dependent upon Claim 1.
Regarding Claim 17, in light of the elected Species I of Fig. 2A, this claim recites the limitation “a vertical level of a lower surface of the gate cut insulating pattern [150B] is closer to the substrate [102] than a vertical level of a lower surface of each of the plurality of first gate lines [160] and the plurality of second gate lines [160]”.
However, this limitation does not describe the elected species, as the vertical level of the lower surface of the gate cut insulating pattern [150B] is not closer to the substrate [102] than the vertical level of the lower surface of each of the plurality of first gate lines [160] and the plurality of second gate lines [160].
Further, this limitation does describe the nonelected Species II of Fig. 3 and Species IV of Fig. 5, which is evidenced by the instant specification in at least Par. 86 & 78, as mentioned above, and their corresponding figures.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8 August 2023 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “a plurality of second gate lines separated from the plurality of first gate lines in the second horizontal direction by a dummy active fin” as cited in Claim 14 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GAA-FET WITH GATE CUT AND DUMMY ACTIVE FIN
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "a plurality of second gate lines separated from the plurality of first gate lines in the second horizontal direction by a dummy active fin " on Pag. 36, Lin. 3 & 4. However, the meaning of this limitation is unclear, as this language does not describe any elected or nonelected species presented in the instant figures.
For the purposes of examination, this limitation will be interpreted as “a plurality of second gate lines separated from the plurality of first gate lines in the second horizontal direction by a gate cut insulating pattern above a dummy active fin”.
Further, to avoid the antecedent basis issue this interpretation generates, the limitation “a gate cut insulating pattern” on Pag. 36, Lin. 7 of this claims will be interpreted for the purposes of examination as “the gate cut insulating pattern”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 14 – 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by GULER (US 20240105804 A1).
PNG
media_image1.png
823
897
media_image1.png
Greyscale
Regarding Claim 14,
GULER discloses:
An integrated circuit device (Annotated Fig. 1E) comprising:
a plurality of fin-type active regions (Annotated Fig. 1E: 104s) protruding in a vertical direction from a substrate (Annotated Fig. 1E: 104s protrude in DV; Further, Par. 32 teaches the 104s “may be extending from a substrate” where “protrude from” and “extend from” are synonymous in this context) and extending parallel to each other in a first horizontal direction (Annotated Fig. 1E: 104s extend parallel to each other in D1), the plurality of fin-type active regions being spaced apart from each other in a second horizontal direction (Annotated Fig. 1E: 104s are spaced apart from each other in D2) that intersects with the first horizontal direction (Annotated Fig. 1E: D1 and D2 intersect at a right angle);
a device isolation film (Annotated Fig. 1E: 106) adjacent to the plurality of fin-type active regions (Annotated Fig. 1E: 106 is adjacent to the vertical sidewalls of the 104s);
a plurality of first gate lines (Annotated Fig. 1E: G1/G1’ of 110s) extending lengthwise in the second horizontal direction on the plurality of fin-type active regions (Annotated Fig. 1E: G1/G1’ extend lengthwise in D2 with G1 on the leftmost 104);
a plurality of second gate lines (Annotated Fig. 1E: G2/G2’ of 110s) separated from the plurality of first gate lines in the second horizontal direction (Annotated Fig. 1E: G2/G2’ separated from G1/G1’ in D2 by leftmost 122 of 130/122s) by a gate cut insulating pattern (Annotated Fig. 1E: 130/122s) above a dummy active fin (Annotated Fig. 1E: 104A, above which is 130 of 130/122s) between a first fin-type active region (Annotated Fig. 1E: F1 of 104s) and a second fin-type active region (Annotated Fig. 1E: F2 of 104s),
wherein the dummy active fin protrudes in the vertical direction from the substrate and extends lengthwise in the first horizontal direction (Fig. 1C & 1D: 104A is formed from the top portion of the middle 104, Par. 36. Therefore, as the other 104s protrude in DV from the substrate and extend lengthwise in D1, so does 104A);
and the gate cut insulating pattern extending lengthwise in the first horizontal direction (Annotated Fig. 1E: 122s of 130/122s extend lengthwise in D1) between the plurality of first gate lines and the plurality of second gate lines (Annotated Fig. 1E: leftmost 122 of 130/122s is between G1/G1’ and G2/G2’) and overlapping the dummy active fin in the vertical direction (Annotated Fig. 1E: 130 of 130/122s overlaps 140A in DV),
wherein the device isolation film comprises a first local isolation portion (Annotated Fig. 1E: portion of 106 between the F1 and 104A) between the first fin-type active region and the dummy active fin and a second local isolation portion (Annotated Fig. 1E: portion of 106 between F2 and 104A) between the second fin-type active region and the dummy active fin.
Regarding Claim 15,
GULER discloses:
The integrated circuit device of claim 14,
wherein the dummy active fin and the plurality of fin-type active regions are integrally connected to the substrate (Par. 32 states that the 104s—and 104A, as per Par. 36—“may be extending from a substrate, such as silicon sub-fins extending from a silicon substrate”. Further, the term “integrally connected” refers to a relationship or connection essential as a part of a whole. Therefore, a person of ordinary skill in the art would understand that the 104s and 104A in Annotated Fig. 1E are integrally connected to the substrate. Accordingly, GULER meets and anticipates the recited limitation.)
Regarding Claim 16,
GULER discloses:
The integrated circuit device of claim 14,
further comprising a plurality of nanosheet stacks (Annotated Fig. 1E & Fig. 1F, 150: 108s) arranged over each of the plurality of fin-type active regions (Annotated Fig. 1E: 108s arranged over each of the 104s),
each of the plurality of nanosheet stacks comprising at least one nanosheet surrounded by one gate line selected from the plurality of first gate lines and the plurality of second gate lines (Annotated Fig. 1E: each 108 comprises four nanosheets, wherein the leftmost 108 is surrounded by G1 of G1/G1’ and the rightmost 108 is surrounded by G2 of G2/G2’),
wherein a vertical level of an upper surface of the gate cut insulating pattern (Annotated Fig. 1E: S1) is farther from the substrate than a vertical level of an upper surface of each of the plurality of first gate lines and the plurality of second gate lines (Annotated Fig. 1E: S2s, wherein the vertical level of S1 is farther from the substrate than the vertical level of the S2s).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over GULER.
Regarding Claim 20,
GULER discloses for an embodiment:
An integrated circuit device (Annotated Fig. 1E) comprising:
a first fin-type active region (Annotated Fig. 1E: F1 of 104s) and a second fin-type active region (Annotated Fig. 1E: F2 of 104s), which protrude in a vertical direction from a substrate (Annotated Fig. 1E: 104s protrude in DV; Further, Par. 32 teaches the 104s “may be extending from a substrate” where “protrude from” and “extend from” are synonymous in this context) and are adjacent to each other (Annotated Fig. 1E: F1 and F2 are adjacent to each other);
a device isolation film (Annotated Fig. 1E: 106) covering both sidewalls of each of the first fin-type active region and the second fin-type active region (Annotated Fig. 1E: 106 covers both sidewalls of F1 and F2; Further, Par. 32 states each 104 “protrude[s] through” 106, thereby covering both sidewalls of each 104);
a first nanosheet stack (Annotated Fig. 1E: leftmost 108 arranged over F1), including at least one nanosheet (Annotated Fig. 1E: each 108 comprises four nanosheets), arranged over the first fin-type active region;
a first gate line (Annotated Fig. 1E: G1 surrounding the leftmost 108) surrounding the first nanosheet stack;
a second nanosheet stack (Annotated Fig. 1E: rightmost 108 arranged over F2), including at least one nanosheet (Annotated Fig. 1E: each 108 comprises four nanosheets), arranged over the second fin-type active region:
a second gate line (Annotated Fig. 1E: G2 surrounding the rightmost 108) surrounding the second nanosheet stack;
a dummy active fin (Annotated Fig. 1E: 104A) separating the first fin-type active region from the second fin-type active region and protruding in the vertical direction from the substrate (Annotated Fig. 1E: 104A separates F1 from F2 and protrudes in DV; Further, Par. 32 teaches the 104s—including 104A, as per Fig. 1C, Fig. 1D, and Par. 36–“may be extending from a substrate” where “protrude from” and “extend from” are synonymous in this context);
a gate cut insulating pattern (Annotated Fig. 1E: 130/122s) separating the first gate line from the second gate line (Annotated Fig. 1E: 130/122s separate G1 from G2),
wherein the gate cut insulating pattern is on the dummy active fin in the vertical direction (Annotated Fig. 1E: 130 of 130/122s is on 104A in DV)…;
a first gate dielectric film (Annotated Fig. 1E: A1 of 112s separating the nanosheets of the leftmost 108 from G1) separating the at least one nanosheet of the first nanosheet stack from the first gate line,
wherein the first gate dielectric film contacts a first sidewall of the gate cut insulating pattern (Annotated Fig. 1E: A1 contacts the leftmost sidewall of 130/122s at P1);
and a second gate dielectric film (Annotated Fig. 1E: A2 of 112s separating the nanosheets of the rightmost 108 from G2) separating the at least one nanosheet of the second nanosheet stack from the second gate line,
wherein the second gate dielectric film contacts a second sidewall of the gate cut insulating pattern opposite the first sidewall (Annotated Fig. 1E: A2 contacts the rightmost sidewall of 130/122s at P2 where the rightmost sidewall of 130/122s is opposite the leftmost sidewall of 130/122s),
wherein the device isolation film comprises a first local isolation portion (Annotated Fig. 1E: portion of 106 between the F1 and 104A) between the first fin-type active region and the dummy active fin, and a second local isolation portion (Annotated Fig. 1E: portion of 106 between the F2 and 104A) between the second fin-type active region and the dummy active fin.
However, GULER does not disclose for the same embodiment:
…and the gate cut insulating pattern extends above the first gate line and the second gate line;
Although, for a similar embodiment, GULER discloses:
…and the gate cut insulating pattern extends above the first gate line and the second gate line (Fig. 4B: the gate cut insulating pattern—464—extends above the first gate line—leftmost 458/460—and the second gate line—rightmost 458/460);
For the similar embodiment, GULER further discloses:
a dielectric gate cap (Fig. 4B: 462) over the first gate line and the second gate line (Fig. 4B: 480), resulting in the gate cut insulating pattern extending above the first gate line and the second gate line (Par. 60).
As such, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the previously mentioned embodiments of GULER, as these inventions are from the same field of endeavor, and the formation of such a dielectric gate cap would have been known to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a means to protect the underlying gate lines. Additionally, GULER suggests such a combination, Par. 124.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
Examiner interviews are available via telephone and video conferencing—preferably at 4 P.M. (EST)—using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898